JP7002899B2 - 記憶装置 - Google Patents

記憶装置 Download PDF

Info

Publication number
JP7002899B2
JP7002899B2 JP2017181980A JP2017181980A JP7002899B2 JP 7002899 B2 JP7002899 B2 JP 7002899B2 JP 2017181980 A JP2017181980 A JP 2017181980A JP 2017181980 A JP2017181980 A JP 2017181980A JP 7002899 B2 JP7002899 B2 JP 7002899B2
Authority
JP
Japan
Prior art keywords
electrode
storage device
peripheral circuit
laminated film
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017181980A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019057662A (ja
Inventor
浩司 松尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Priority to JP2017181980A priority Critical patent/JP7002899B2/ja
Priority to TW106146445A priority patent/TWI656624B/zh
Priority to CN201810092383.8A priority patent/CN109545789A/zh
Priority to US15/927,318 priority patent/US10319730B2/en
Publication of JP2019057662A publication Critical patent/JP2019057662A/ja
Application granted granted Critical
Publication of JP7002899B2 publication Critical patent/JP7002899B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/145—Read-only memory [ROM]
    • H01L2924/1451—EPROM
    • H01L2924/14511—EEPROM

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2017181980A 2017-09-22 2017-09-22 記憶装置 Active JP7002899B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2017181980A JP7002899B2 (ja) 2017-09-22 2017-09-22 記憶装置
TW106146445A TWI656624B (zh) 2017-09-22 2017-12-29 Memory device
CN201810092383.8A CN109545789A (zh) 2017-09-22 2018-01-26 存储装置
US15/927,318 US10319730B2 (en) 2017-09-22 2018-03-21 Memory device having a plurality of first conductive pillars penetrating through a stacked film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017181980A JP7002899B2 (ja) 2017-09-22 2017-09-22 記憶装置

Publications (2)

Publication Number Publication Date
JP2019057662A JP2019057662A (ja) 2019-04-11
JP7002899B2 true JP7002899B2 (ja) 2022-01-20

Family

ID=65807815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017181980A Active JP7002899B2 (ja) 2017-09-22 2017-09-22 記憶装置

Country Status (4)

Country Link
US (1) US10319730B2 (zh)
JP (1) JP7002899B2 (zh)
CN (1) CN109545789A (zh)
TW (1) TWI656624B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6203152B2 (ja) 2014-09-12 2017-09-27 東芝メモリ株式会社 半導体記憶装置の製造方法
US10892269B2 (en) 2014-09-12 2021-01-12 Toshiba Memory Corporation Semiconductor memory device having a bonded circuit chip including a solid state drive controller connected to a control circuit
US11227860B2 (en) 2019-09-02 2022-01-18 Samsung Electronics Co., Ltd. Memory device
KR20210027706A (ko) 2019-09-02 2021-03-11 삼성전자주식회사 메모리 장치
KR20210028438A (ko) 2019-09-04 2021-03-12 삼성전자주식회사 메모리 장치
US11289467B2 (en) 2019-09-04 2022-03-29 Samsung Electronics Co., Ltd. Memory device
JP2021044358A (ja) 2019-09-10 2021-03-18 キオクシア株式会社 半導体装置及び半導体装置の製造方法
KR20210093045A (ko) 2020-01-17 2021-07-27 삼성전자주식회사 메모리 장치
KR20210100235A (ko) * 2020-02-05 2021-08-17 에스케이하이닉스 주식회사 반도체 메모리 장치
US11594506B2 (en) * 2020-09-23 2023-02-28 Advanced Semiconductor Engineering, Inc. Semiconductor package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012146861A (ja) 2011-01-13 2012-08-02 Toshiba Corp 半導体記憶装置
JP2012234885A (ja) 2011-04-28 2012-11-29 Toshiba Corp 半導体装置及びその製造方法
JP2015133458A (ja) 2014-01-16 2015-07-23 株式会社東芝 不揮発性半導体記憶装置
JP2016062901A (ja) 2014-09-12 2016-04-25 株式会社東芝 半導体記憶装置及びその製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4322347B2 (ja) * 1999-03-15 2009-08-26 エルピーダメモリ株式会社 半導体装置およびその製造方法
KR100824637B1 (ko) * 2007-06-26 2008-04-25 주식회사 동부하이텍 Ｎｏｒ 플래쉬 디바이스 및 그의 제조 방법
JP2009054951A (ja) * 2007-08-29 2009-03-12 Toshiba Corp 不揮発性半導体記憶素子及びその製造方法
JP2011014817A (ja) * 2009-07-06 2011-01-20 Toshiba Corp 不揮発性半導体記憶装置
JP2011258776A (ja) 2010-06-09 2011-12-22 Toshiba Corp 不揮発性半導体メモリ
CN102623457B (zh) * 2011-01-26 2015-04-15 旺宏电子股份有限公司 半导体结构及其制造方法与操作方法
KR20130070150A (ko) * 2011-12-19 2013-06-27 에스케이하이닉스 주식회사 3차원 비휘발성 메모리 소자, 메모리 시스템 및 그 제조 방법
JP2013239622A (ja) * 2012-05-16 2013-11-28 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
KR102059196B1 (ko) 2013-01-11 2019-12-24 에프아이오 세미컨덕터 테크놀로지스, 엘엘씨 3차원 반도체 장치 및 그 제조 방법
TWI545696B (zh) * 2013-09-10 2016-08-11 Toshiba Kk Semiconductor memory device and manufacturing method thereof
JP6129756B2 (ja) * 2014-01-24 2017-05-17 株式会社東芝 半導体装置及びその製造方法
US9449987B1 (en) * 2015-08-21 2016-09-20 Sandisk Technologies Llc Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors
US11956952B2 (en) * 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US10269620B2 (en) * 2016-02-16 2019-04-23 Sandisk Technologies Llc Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
US9721663B1 (en) * 2016-02-18 2017-08-01 Sandisk Technologies Llc Word line decoder circuitry under a three-dimensional memory array
US10256248B2 (en) * 2016-06-07 2019-04-09 Sandisk Technologies Llc Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012146861A (ja) 2011-01-13 2012-08-02 Toshiba Corp 半導体記憶装置
JP2012234885A (ja) 2011-04-28 2012-11-29 Toshiba Corp 半導体装置及びその製造方法
JP2015133458A (ja) 2014-01-16 2015-07-23 株式会社東芝 不揮発性半導体記憶装置
JP2016062901A (ja) 2014-09-12 2016-04-25 株式会社東芝 半導体記憶装置及びその製造方法

Also Published As

Publication number Publication date
US10319730B2 (en) 2019-06-11
TW201916326A (zh) 2019-04-16
TWI656624B (zh) 2019-04-11
US20190096900A1 (en) 2019-03-28
CN109545789A (zh) 2019-03-29
JP2019057662A (ja) 2019-04-11

Similar Documents

Publication Publication Date Title
JP7002899B2 (ja) 記憶装置
TWI600160B (zh) 高電壓電晶體與低電壓非平面電晶體的單體集成
US10825820B2 (en) Method for manufacturing a microelectronic circuit and corresponding microelectronic circuit
JP2018163970A (ja) 半導体装置及びその製造方法
US20200106013A1 (en) Resistive random access memory device and methods of fabrication
US9721951B2 (en) Semiconductor device using Ge channel and manufacturing method thereof
US10128256B2 (en) One-time programming cell
TW201230050A (en) Electronics system, anti-fuse memory and method for the same
TW201601160A (zh) 記憶體裝置
US10355019B1 (en) Semiconductor device
JP7359754B2 (ja) 半導体装置
KR20210093934A (ko) 이차 전지의 이상 검출 장치 및 반도체 장치
US10741469B2 (en) Thermal via arrangement for multi-channel semiconductor device
US9318532B2 (en) Semiconductor memory device
KR20210106470A (ko) 단극성 트랜지스터를 사용하여 구성된 논리 회로, 및 반도체 장치
TWI566401B (zh) 具有低電阻閘極結構之多鰭鰭式場效電晶體
WO2019055008A1 (en) SELECTOR DEVICES
KR20210077716A (ko) 단극성 레벨 시프트 회로 및 반도체 장치
JP7335376B2 (ja) 三進インバータ及びその製造方法
JP5931583B2 (ja) 半導体装置の作製方法
US20230178549A1 (en) Stacked field effect transistors
JP7570483B2 (ja) 半導体装置
US20230197654A1 (en) Ic's with multple levels of embedded memory
US20240015958A1 (en) One-time programmable memory structure
JP2005123235A (ja) アモルファス金属電極キャパシタ

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20180911

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191122

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200928

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20201006

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20201201

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210601

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20211130

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20211228

R150 Certificate of patent or registration of utility model

Ref document number: 7002899

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150