JP7002899B2 - 記憶装置 - Google Patents
記憶装置 Download PDFInfo
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- JP7002899B2 JP7002899B2 JP2017181980A JP2017181980A JP7002899B2 JP 7002899 B2 JP7002899 B2 JP 7002899B2 JP 2017181980 A JP2017181980 A JP 2017181980A JP 2017181980 A JP2017181980 A JP 2017181980A JP 7002899 B2 JP7002899 B2 JP 7002899B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/145—Read-only memory [ROM]
- H01L2924/1451—EPROM
- H01L2924/14511—EEPROM
Description
10 積層膜
12 絶縁膜
12a 第1の絶縁膜
12b 第2の絶縁膜
12c 第3の絶縁膜
12d 第4の絶縁膜
14 半導体膜
14a 第1の半導体膜
14b 第2の半導体膜
14c 第3の半導体膜
14d 第4の半導体膜
36 第1の導電ピラー
38 第2の導電ピラー
40 第1のメモリセル絶縁体
42 第2のメモリセル絶縁体
44 第1の電極
46 第2の電極
48 メモリセル
58 配線
60 周辺回路基板
62 周辺回路絶縁体
64 第3の電極
66 第4の電極
68 素子分離領域
74 ソース部
76 ドレイン部
80 チャネル部
82 ゲート絶縁膜
84 ゲート部
88 トランジスタ
100 記憶装置
Claims (5)
- 複数の半導体膜と、前記複数の半導体膜のそれぞれの間に設けられた複数の絶縁膜と、を有する積層膜と、
前記積層膜の上方に設けられた第1の電極と、
前記積層膜の上方に設けられた第2の電極と、
前記積層膜を貫通し、一端が前記第1の電極に電気的に接続され、前記積層膜の下方に位置する他端は互いに接続されていない複数の第1の導電ピラーと、
前記複数の第1の導電ピラーと前記半導体膜の間のそれぞれに設けられた複数のメモリセルと、
前記複数の半導体膜のそれぞれと前記第2の電極に電気的に接続される複数の第2の導電ピラーと、
前記第1の電極及び前記第2の電極の上方に設けられた周辺回路基板と、
前記第1の電極と前記周辺回路基板との間に設けられ、前記第1の電極に電気的に接続された第3の電極と、
前記第2の電極と前記周辺回路基板との間に設けられ、前記第2の電極に電気的に接続された第4の電極と、
前記第3の電極又は前記第4の電極に電気的に接続され前記周辺回路基板内に設けられたトランジスタと、
を備える記憶装置。 - 前記複数の第1の導電ピラーは、複数のゲート電極である請求項1記載の記憶装置。
- 前記複数の半導体膜のうちの一の前記半導体膜の面積は、前記一の前記半導体膜より下方に設けられた他の前記半導体膜の面積よりも小さい請求項1又は請求項2記載の記憶装置。
- 前記第1の電極及び前記第2の電極の周囲に設けられた第1のメモリセル絶縁体と、
前記第3の電極及び前記第4の電極の周囲に設けられた周辺回路絶縁体と、
をさらに備え、
前記第1の電極、前記第2の電極、前記第3の電極及び前記第4の電極は銅を含む、
請求項1ないし請求項3いずれか一項記載の記憶装置。 - 前記第1のメモリセル絶縁体及び前記周辺回路絶縁体は、酸化シリコン、酸化窒化シリコン又は炭素添加酸化シリコンを含む請求項4記載の記憶装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017181980A JP7002899B2 (ja) | 2017-09-22 | 2017-09-22 | 記憶装置 |
TW106146445A TWI656624B (zh) | 2017-09-22 | 2017-12-29 | Memory device |
CN201810092383.8A CN109545789A (zh) | 2017-09-22 | 2018-01-26 | 存储装置 |
US15/927,318 US10319730B2 (en) | 2017-09-22 | 2018-03-21 | Memory device having a plurality of first conductive pillars penetrating through a stacked film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017181980A JP7002899B2 (ja) | 2017-09-22 | 2017-09-22 | 記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019057662A JP2019057662A (ja) | 2019-04-11 |
JP7002899B2 true JP7002899B2 (ja) | 2022-01-20 |
Family
ID=65807815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017181980A Active JP7002899B2 (ja) | 2017-09-22 | 2017-09-22 | 記憶装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10319730B2 (ja) |
JP (1) | JP7002899B2 (ja) |
CN (1) | CN109545789A (ja) |
TW (1) | TWI656624B (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6203152B2 (ja) * | 2014-09-12 | 2017-09-27 | 東芝メモリ株式会社 | 半導体記憶装置の製造方法 |
US10892269B2 (en) | 2014-09-12 | 2021-01-12 | Toshiba Memory Corporation | Semiconductor memory device having a bonded circuit chip including a solid state drive controller connected to a control circuit |
US11227860B2 (en) | 2019-09-02 | 2022-01-18 | Samsung Electronics Co., Ltd. | Memory device |
KR20210027706A (ko) | 2019-09-02 | 2021-03-11 | 삼성전자주식회사 | 메모리 장치 |
KR20210028438A (ko) | 2019-09-04 | 2021-03-12 | 삼성전자주식회사 | 메모리 장치 |
US11289467B2 (en) | 2019-09-04 | 2022-03-29 | Samsung Electronics Co., Ltd. | Memory device |
JP2021044358A (ja) | 2019-09-10 | 2021-03-18 | キオクシア株式会社 | 半導体装置及び半導体装置の製造方法 |
KR20210093045A (ko) | 2020-01-17 | 2021-07-27 | 삼성전자주식회사 | 메모리 장치 |
KR20210100235A (ko) * | 2020-02-05 | 2021-08-17 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
US11594506B2 (en) * | 2020-09-23 | 2023-02-28 | Advanced Semiconductor Engineering, Inc. | Semiconductor package |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2012146861A (ja) | 2011-01-13 | 2012-08-02 | Toshiba Corp | 半導体記憶装置 |
JP2012234885A (ja) | 2011-04-28 | 2012-11-29 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2015133458A (ja) | 2014-01-16 | 2015-07-23 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2016062901A (ja) | 2014-09-12 | 2016-04-25 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
Family Cites Families (16)
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JP4322347B2 (ja) * | 1999-03-15 | 2009-08-26 | エルピーダメモリ株式会社 | 半導体装置およびその製造方法 |
KR100824637B1 (ko) * | 2007-06-26 | 2008-04-25 | 주식회사 동부하이텍 | Nor 플래쉬 디바이스 및 그의 제조 방법 |
JP2009054951A (ja) * | 2007-08-29 | 2009-03-12 | Toshiba Corp | 不揮発性半導体記憶素子及びその製造方法 |
JP2011014817A (ja) * | 2009-07-06 | 2011-01-20 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2011258776A (ja) | 2010-06-09 | 2011-12-22 | Toshiba Corp | 不揮発性半導体メモリ |
CN102623457B (zh) * | 2011-01-26 | 2015-04-15 | 旺宏电子股份有限公司 | 半导体结构及其制造方法与操作方法 |
KR20130070150A (ko) * | 2011-12-19 | 2013-06-27 | 에스케이하이닉스 주식회사 | 3차원 비휘발성 메모리 소자, 메모리 시스템 및 그 제조 방법 |
JP2013239622A (ja) * | 2012-05-16 | 2013-11-28 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
KR102059196B1 (ko) | 2013-01-11 | 2019-12-24 | 에프아이오 세미컨덕터 테크놀로지스, 엘엘씨 | 3차원 반도체 장치 및 그 제조 방법 |
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JP6129756B2 (ja) * | 2014-01-24 | 2017-05-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
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-
2017
- 2017-09-22 JP JP2017181980A patent/JP7002899B2/ja active Active
- 2017-12-29 TW TW106146445A patent/TWI656624B/zh not_active IP Right Cessation
-
2018
- 2018-01-26 CN CN201810092383.8A patent/CN109545789A/zh active Pending
- 2018-03-21 US US15/927,318 patent/US10319730B2/en active Active
Patent Citations (4)
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JP2012146861A (ja) | 2011-01-13 | 2012-08-02 | Toshiba Corp | 半導体記憶装置 |
JP2012234885A (ja) | 2011-04-28 | 2012-11-29 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2015133458A (ja) | 2014-01-16 | 2015-07-23 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2016062901A (ja) | 2014-09-12 | 2016-04-25 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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TW201916326A (zh) | 2019-04-16 |
JP2019057662A (ja) | 2019-04-11 |
CN109545789A (zh) | 2019-03-29 |
TWI656624B (zh) | 2019-04-11 |
US10319730B2 (en) | 2019-06-11 |
US20190096900A1 (en) | 2019-03-28 |
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