TWI566401B - 具有低電阻閘極結構之多鰭鰭式場效電晶體 - Google Patents

具有低電阻閘極結構之多鰭鰭式場效電晶體 Download PDF

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TWI566401B
TWI566401B TW104109943A TW104109943A TWI566401B TW I566401 B TWI566401 B TW I566401B TW 104109943 A TW104109943 A TW 104109943A TW 104109943 A TW104109943 A TW 104109943A TW I566401 B TWI566401 B TW I566401B
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古拉梅 伯奇
奇宏 安迪 韋
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格羅方德半導體公司
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Description

具有低電阻閘極結構之多鰭鰭式場效電晶體
本發明一般有關半導體製造，更具體而言，有關於具有低電阻閘極結構的電晶體。
隨著技術進步，為了趕上電子裝置行動、輕量和有效率的潮流，必須改善電子裝置的製造。然而，隨著裝置的尺寸，例如輸入輸出(IO)功能的某些功能變得有挑戰性。該IO功能可能控制來自功能電路的訊號和電源，例如提供至外部電路的連結。該IO功能的電流需求使某些裝置的微縮變得困難，因為隨裝置尺寸而增加的閘極電阻。正因如此，而期望對鰭式場效電晶體改良以設法解決如前述的挑戰。
本發明的實施例提供一種有低電阻閘極結構的多鰭鰭式場效電晶體(finFET)。金屬化線形成平行於閘極且複數個接點形成於鰭件上方，以連接該金屬化線至該閘極。該金屬化線提供减少的閘極電阻，使得能使用較少電晶體來提供輸入輸出功能，因此提供省下的空間而能夠 增加電路密度。
在第一態樣中，本發明的一些實施例提供一種半導體結構，包括：半導體基板；複數個鰭件形成於該半導體基板中；閘極設置於該複數個鰭件上方；複數個接點直接實體接觸該閘極且直接於該複數個鰭件上方；以及金屬化線設置於該複數個接點上方，其中該金屬化線電氣接觸該複數個接點。
在第二態樣中，本發明的一些實施例提供一種半導體積體電路，包括：複數個輸入輸出電路，其中各輸入輸出電路包括至少一個鰭式場效電晶體裝置，其中該至少一個鰭式場效電晶體裝置包括具有範圍自16至60的長度/寬度的長寬比的閘極。
在第三態樣中，本發明的實施例提供一種半導體結構，包括：半導體基板；複數個鰭件形成於該半導體基板中；閘極設置於該複數個鰭件上，其中該複數個鰭件包括從40個鰭件至100個鰭件；複數個接點直接實體接觸該閘極且直接於該鰭件上方，其中每個接點鰭件的參數的範圍自5個鰭件至20個鰭件；以及金屬化線設置於該複數個接點上方，其中該金屬化線電氣接觸該複數個接點。
100‧‧‧半導體結構
105‧‧‧STI區域
110‧‧‧半導體區域
115‧‧‧鰭件
120‧‧‧閘極
125‧‧‧接點
200‧‧‧半導體結構
205‧‧‧半導體基板
210‧‧‧絕緣層
215‧‧‧半導體基板
220‧‧‧鰭件
225‧‧‧鰭件區域
227‧‧‧介電層
230‧‧‧閘極
235‧‧‧接點
240‧‧‧金屬化線
245‧‧‧符號
300‧‧‧半導體結構
305‧‧‧半導體基板
310‧‧‧鰭件
315‧‧‧閘極
320‧‧‧接點
325‧‧‧符號
327‧‧‧介電層
330‧‧‧金屬化線
L1‧‧‧長度
L2‧‧‧長度
W‧‧‧寬度
併入且作為此說明書的一部份的附圖繪製數個本教示的實施例並且搭配該說明作為解釋本教示的原則。
為了清楚說明，該附圖式的部份當中的某些元素可能被省略或未按照尺度比例繪製。為了清楚說明，該截面圖可能為“切片”(slices)的形式，或“近視的(near-sighted)”截面圖，省略某些背景線其可能反之在“真實”截面圖中將會看見的。此外，為了明確性，一些元件符號可能在某些圖示中被省略。
第1圖顯示根據本發明的實施例的半導體結構的俯視圖。
第2圖顯示根據本發明的實施例的半導體結構的截面圖。
第3圖顯示根據本發明的替代的實施例的半導體結構的截面圖。
作為說明的實施例現將參考所附顯示有實施例的圖式更完整描述於此。然而，本發明可能以不同的形式實現，且不應被解釋為限定於此所闡述的該實施例。相反地，這些實施例被提供以使此發明揭露全面和完整並且將對熟悉本領域技術者完全傳達本發明的範圍。於該描述中，衆所皆知的特徵和技術的細節可能被省略以避免多餘地模糊本發明的實施例。
本發明的實施例提供具有低電阻閘極結構的多鰭鰭式場效電晶體(finFET)。金屬化線形成平行閘極，以及多個接點形成於鰭件上方、連接該金屬化線至該閘極。該金屬化線提供减少的閘極電阻，使得較少的電晶 體用於提供輸出輸入(IO)功能，從而提供省下的空間能夠增加電路密度。
於此使用的專門用語僅是為了描述特定具 體實施例的目的，而非意圖為了限制本發明。除非該上下文中明確指示，否則如於此所使用單數形式“一”和“該”意圖也包括該多個的形式。此外，該術語“一”等的使用並不代表對數量的限制，反而是代表該參考物件存在至少一個。術語“集合”(“set”)意圖指至少一個的數量。應進一步瞭解的是術語“包括”，或“包含”於此可交替地被使用，當用於本說明書中，明確指出所陳述的特徵、區域、整體、步驟、操作、元件、和/或組成的存在，但並非排除一或多個其他特徵、區域、整體、步驟、操作、元件、組成、和/或其群組的存在或添加。
說明書全文中提及“一(個)實施例”、“實 施例”、“例示性的實施例”或相似的用語時意指與該實施例有關的所述特定特徵、結構、或特性被包括於本發明的至少一個實施例中。因此，在說明書全文中，片語“於一(個)實施例中”、“於實施例中”、“於一些實施例中”和相似的用語的出現時，可能但非必要，全部指的是相同實施例。
該術語“覆於…之上”(“overlying”)或“在…之頂”(“atop”)、“位於…上”、“位於…之頂”、或“設置於…上”、“襯於…之下”(“underlying”)、“在…下方”或“下方”，意指例 如第一結構(如第一層)的第一元件在例如第二結構(如第二層)的第二元件上，其中介於中間的例如中間結構(如中間層)的元件可在該第一元件和該第二元件之間。
第1圖顯示根據本發明的實施例的半導體 結構的俯視圖。半導體結構100包括具有鰭件合併半導體區域110的STI區域105，其可為磊晶矽或矽鍺(SiGe)。複數個鰭件115形成於該半導體基板中(即，在該鰭件合併區域110上)。於一些實施例中，該複數個鰭件115的範圍為自20個鰭件至30個鰭件。於一些實施例中，該複數個鰭件115的範圍為自31個鰭件至60個鰭件。於一些實施例中，該複數個鰭件115的範圍為自61個鰭件至200個鰭件。該鰭件可為矽或矽鍺(SiGe)，且可藉由側壁影像轉換(sidewall image transfer(SIT))或其他適合的製程而形成。 閘極120形成於該鰭件115上方。該閘極120可為鎢、鋁、或其他適合的材料或其組合。該閘極可藉由替代金屬閘極製程或其他適合的方法而形成。閘極120具有寬度W。於一些實施例中，W的範圍自約20奈米至約30奈米。閘極120具有長度L。於一些實施例，L的範圍自約480奈米至約1200奈米。因此，於一些實施例中，該長度/寬度長寬比的範圍自16至60。複數個接點125形成直接實體接觸該閘極120且直接於該複數個鰭件115上方。接點125可為鎢、鋁、銅、任何其他適合的導體、或其任何組合。金屬化線(未顯示)設置於該複數個接點125上方，並電氣接觸該複數個接點125。金屬化線可為銅、鎢、鋁、任何其 他適合的導體、或其任何組合。藉由把該金屬化線平行於該閘極放置(而非嘗試設計較好的閘極材料，此非常困難)，將實現减少的等效閘極電阻。這樣，避免沿著延伸的閘極線而下降的電壓。此安排亦節省空間，使得I/O裝置所需的空間量减少，因此能夠在晶片上有較多的裝置(增加電路密度)。因為使用具有减少閘極電阻的單一電晶體，取代了需要多個電晶體以設法解決閘極電阻的問題，而實現了該省下的空間的增加。
第2圖顯示根據本發明的實施例的半導體 結構截面圖。此圖相似但不相同於第1圖沿著A-A’的截面。半導體結構200包括塊體半導體基板205。絕緣層210設置於該塊體半導體基板上。絕緣體上半導體基板215設置於該絕緣層210上。複數個鰭件220形成以代表該絕緣體上半導體基板215中的鰭件區域225。於一些實施例，該複數個鰭件220的範圍為自20個鰭件至30個鰭件。於一些實施例，該複數個鰭件220的範圍為自31個鰭件至60個鰭件。於一些實施例，該複數個鰭件220的範圍為自61個鰭件至200個鰭件。閘極230可設置於該複數個鰭件220上。介電層227設置於該閘極230和金屬化線240之間。於實施例中，該介電層可包括二氧化矽、SiOC,SiCON、或其他適合的介電材料。複數個接點235形成直接實體接觸該閘極230且直接於該複數個鰭件220上方，以及可橫穿過該介電層227。接點235可為鎢、鋁、銅、任何其他適合的導體、或其任何組合。該複數個鰭件220的子集合 和該複數個接點235的各個相關聯。於此所顯示的實施例中，4個鰭件的群組和各接點關聯，因此本實例中，每個接點鰭件(fins/contact)的參數為4。此種群組的一群組的實例顯示為元件符號245。於一些實施例中，鰭件每個接點鰭件的參數範圍為自5個鰭件至20個鰭件。該金屬化線240設置於該複數個接點235上，並電氣接觸該複數個接點235。金屬化線240可為銅、鎢、鋁、和任何其他適合的導體、或任何其組合。閘極230包括長度L1。於一些具體實施例中，L1的範圍自約200奈米至約500奈米。為了實現該電晶體，額外的接點可使用於存取該源極和汲極(未顯示)。
第3圖顯示根據本發明的替代的實施例的半導體結構的截面圖。半導體結構300包括半導體基板305，其可為塊體半導體基板。複數個鰭件310形成於該半導體基板305中。閘極315設置於該複數個鰭件310上。介電層327設置於該閘極315和金屬化線330之間。實施例中，該介電層可包括二氧化矽、SiOC,SiCON、或其他適合的介電材料。於一些實施例中，該複數個鰭件310包括從40個鰭件至100個鰭件。一些實施例中，可包括較多或較少的鰭件，並不脫離本發明的範疇。複數個接點320直接實體接觸該閘極315並直接於該複數個鰭件310上，以及可橫穿過該介電層327。接點320可為鎢、鋁、銅、任何其他適合的導體、或其任何組合。於一些實施例中，每個接點鰭件的數量範圍自5個鰭件至20個鰭件。顯 示於此的實施例中，4個鰭件的群組相關聯於各接點。此種群組的群組的實例顯示為元件符號325。該金屬化線330設置於該複數個接點320上並電氣接觸該複數個接點320。金屬化線330可為銅、鎢、鋁、任何其他適合的導體、或任何其組合。閘極315包括長度L2。於一些實施例中，L2的範圍自約200奈米至約500奈米。於一些實施例中，該接點320可以規律的間隔形成，將該閘極315連接至該金屬化線330以避免沿著閘極315形成大的電壓下降。
於實施例中，該接點(如第1圖的125、第2 圖的235、和第3圖的320)可使用具有二個不同覆蓋層之製程而形成。該二個不同覆蓋層由不同材料組成且選擇性地可蝕刻彼此。於實施例中，一覆蓋層可由氧化物，例如二氧化矽，組成，而另一覆蓋層則由氮化物組成，例如氮化矽。一覆蓋層用於閘極覆蓋，而另一覆蓋層則被用於源極/汲極通道access覆蓋。選擇性蝕刻製程在各式位置打開該所期望的閘極，而阻擋遮罩則用於覆蓋非連接結構部分的元件。接著沉積該接點材料，接觸該閘極以能夠平行電氣連接於該閘極(如，第1圖的120、第2圖的220、和第3圖的315)和在其上的該金屬化線(如，第2圖的240和第3圖的330)之間。此特定的結構能夠在主動矽區域上形成至閘極的接點和至源極/汲極區域的接點。
現在可以理解，本發明的實施例提供改良 的場效電晶體，其具有沿著該閘極减少的電壓下降。此有助於使用單一、較大的電晶體取代多個較小電晶體，致使 全面地省下空間，允許增加的電路密度。雖然本發明已配合例示性的具體實施例被具體顯示和描述，應理解的是，變化和調整將可被熟悉本技術領域者思及。例如，雖然該作為說明的具體實施例於此被描述為一連串的動作或事件，但應理解到本發明並不被此種動作或事件的該說明順序限制，除非有特定聲明。根據本發明，一些動作可能依不同順序發生和/或與其他那些除了於此被說明和/或被描述以外之動作或事件同時發生。此外，根據本發明，並非全部被說明的步驟都可能為實施方法所必需的。而且，根據本發明的方法可能被實施，和於此說明或描述之結構的形成和/或過程相關，以及和其他未說明的結構相關。因此，應該被瞭解的是，申請專利範圍意圖涵蓋全部此類落於本發明真正精神的調整和改變。
100‧‧‧半導體結構
105‧‧‧STI區域
110‧‧‧半導體區域
115‧‧‧鰭件
120‧‧‧閘極
125‧‧‧接點
W‧‧‧寬度

Claims (20)

  1. 一種半導體結構，係包括：半導體基板；複數個鰭件，係形成於該半導體基板中；閘極，係設置於該複數個鰭件上方；複數個接點，係直接實體接觸該閘極，其中，該複數個接點之至少一者直接設置於該複數個鰭件之對應一者上方；以及金屬化線，係設置於該複數個接點上方，其中，該金屬化線係電氣接觸該複數個接點。
  2. 如申請專利範圍第1項所述的半導體結構，其中，該複數個鰭件的範圍自20個鰭件至30個鰭件。
  3. 如申請專利範圍第1項所述的半導體結構，其中，該複數個鰭件的範圍自31個鰭件至60個鰭件。
  4. 如申請專利範圍第1項所述的半導體結構，其中，該複數個鰭件的範圍自61個鰭件至200個鰭件。
  5. 如申請專利範圍第1項所述的半導體結構，其中，該複數個鰭件由矽所構成。
  6. 如申請專利範圍第1項所述的半導體結構，其中，該複數個鰭件由矽鍺所構成。
  7. 如申請專利範圍第1項所述的半導體結構，還包括介電層，係設置於該金屬化線和該閘極之間。
  8. 如申請專利範圍第7項所述的半導體結構，其中，該介電層由二氧化矽所構成。
  9. 如申請專利範圍第1項所述的半導體結構，其中，該金屬化線由銅所構成。
  10. 如申請專利範圍第1項所述的半導體結構，其中，該複數個接點由鎢所構成。
  11. 如申請專利範圍第1項所述的半導體結構，還包括鰭件合併半導體區域。
  12. 如申請專利範圍第11項所述的半導體結構，其中，該鰭件合併半導體區域包括矽。
  13. 如申請專利範圍第11項所述的半導體結構，其中，該鰭件合併半導體區域包括矽鍺。
  14. 一種半導體積體電路，係包括：複數個輸入輸出電路，其中，各個輸入輸出電路包括至少一個鰭式場效電晶體裝置，其中，該至少一個鰭式場效電晶體裝置包括具有範圍自16至60的長度/寬度的長寬比的閘極，該至少一個鰭式場效電晶體裝置還包括複數個鰭件以及複數個接點，且該複數個接點之至少一者直接設置於該複數個鰭件之對應一者上方。
  15. 如申請專利範圍第14項所述的半導體積體電路，其中該半導體積體電路還包括金屬化線，係設置於該閘極之上並和該閘極成一直線，其中，該金屬化線的電阻值小於該閘極的電阻值。
  16. 如申請專利範圍第15項所述的半導體積體電路，其中，該複數個接點以規律的間隔排列連接該閘極至該 金屬化線。
  17. 一種半導體結構，係包括：半導體基板；複數個鰭件，係形成於該半導體基板中；閘極，係設置於該複數個鰭件上方，其中，該複數個鰭件包括從40個鰭件至100個鰭件；複數個接點，係直接實體接觸該閘極以及直接於該複數個鰭件上方，其中，每個接點鰭件的參數範圍自5個鰭件至20個鰭件；以及金屬化線，係設置於該複數個接點上方，其中，該金屬化線係電氣接觸該複數個接點。
  18. 如申請專利範圍第17項所述的半導體結構，其中，該金屬化線由銅構成。
  19. 如申請專利範圍第18項所述的半導體結構，其中，該複數個接點由鎢構成。
  20. 如申請專利範圍第19項所述的半導體結構，還包括介電層，係設置於該金屬化線和該閘極之間。
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