JP7335376B2 - 三進インバータ及びその製造方法 - Google Patents
三進インバータ及びその製造方法 Download PDFInfo
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- JP7335376B2 JP7335376B2 JP2022022869A JP2022022869A JP7335376B2 JP 7335376 B2 JP7335376 B2 JP 7335376B2 JP 2022022869 A JP2022022869 A JP 2022022869A JP 2022022869 A JP2022022869 A JP 2022022869A JP 7335376 B2 JP7335376 B2 JP 7335376B2
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Description
200 定電流形成層
320 ゲート絶縁膜
330 ゲートスペーサ
340 層間絶縁膜
Claims (9)
- シリコン(Si)を含み、ドーピングされて第1導電型を有する、定電流形成層と、
前記定電流形成層上に位置して前記定電流形成層にコンタクトし、相互離隔されて位置し、ドーピングされて前記第1導電型を有する第1ソース及びドーピングされて前記第1導電型と異なる第2導電型を有する第1ドレインと、
前記第1ソース上に位置する層間絶縁膜と、
前記層間絶縁膜上に位置する第2ソース、及び前記第1ドレイン上に位置する第2ドレインと、
前記第1ソースと前記第1ドレインとの間に介在され、前記第1ソース方向の第1-1端部面が、前記第1ソースにコンタクトし、前記第1ドレイン方向の第1-2端部面が、 前記第1ドレインにコンタクトする、第1チャネルと、
前記第1チャネルから離隔され、前記第1チャネル上部に位置し、前記第2ソースと前記第2ドレインとの間に介在され、前記第2ソース方向の第2-1端部面が、前記第2ソースにコンタクトし、前記第2ドレイン方向の第2-2端部面が、前記第2ドレインにコンタクトする、第2チャネルと、
前記第1チャネルの外側面と、前記第2チャネルの外側面と、前記第1ソースの前記第1ドレイン方向の面とのうち、前記第1チャネルとコンタクトする部分以外の部分;前記第2ソースの前記第2ドレイン方向の面のうち、前記第2チャネルとコンタクトする部分以外の部分;前記第1ドレインの前記第1ソース方向の面のうち、前記第1チャネルとコンタクトする部分以外の部分;及び前記第2ドレインの前記第2ソース方向の面のうち、前記第2チャネルとコンタクトする部分以外の部分を覆うゲート絶縁膜と、
前記第1ソースと前記第1ドレインとの間、及び前記第2ソースと前記第2ドレインとの間に介在されるゲート電極と、を具備する、三進インバータ。 - 前記第1ソースと前記第2ソースは、異なる導電型にドーピングされた、請求項1に記載の三進インバータ。
- 前記第1ドレインと前記第2ドレインは、異なる導電型にドーピングされた、請求項2に記載の三進インバータ。
- 前記ゲート電極は、前記第1チャネルと前記第2チャネルとの間を充填する、請求項1に記載の三進インバータ。
- 前記ゲート電極は、前記ゲート絶縁膜の前記第1チャネルを取り囲む部分と、前記ゲート絶縁膜の前記第2チャネルを取り囲む部分と、を取り囲む、請求項4に記載の三進インバータ。
- 基板上に、ドーピングされて第1導電型を有する定電流形成層を形成する段階と、
定電流形成層上に、第1犠牲層、第1犠牲層上の第1チャネル、第1チャネル上の第2犠牲層、第2犠牲層上の第2チャネル、及び第2チャネル上の第3犠牲層を含み、第1方向に延長された、ゲート構造体を形成する段階と、
第1方向と交差する第2方向に延長され、ゲート構造体と交差するダミーゲートを形成する段階と、
定電流形成層上に位置して定電流形成層にコンタクトするように、該ダミーゲートの一側に、第1チャネルの第1-1端部面にコンタクトする第1ソースを形成し、定電流形成層上に位置して定電流形成層にコンタクトするように、該ダミーゲートの他側に、第1チャネルの第1-2端部面にコンタクトする第1ドレインを形成する段階と、
第1ソースが第1導電型を有するようにドーピングし、第1ドレインが第1導電型と異なる第2導電型を有するようにドーピングする段階と、
該第1ソース上に、層間絶縁層を形成する段階と、
該層間絶縁層上に、第2チャネルの第2-1端部面にコンタクトする第2ソースを形成し、第1ドレイン上に、第2チャネルの第2-2端部面にコンタクトする第2ドレインを形成する段階と、
該ダミーゲートを除去する段階と、
該第1犠牲層、該第2犠牲層及び該第3犠牲層を除去する段階と、
該第1チャネルの外側面と、該第2チャネルの外側面と、該第1ソースの第1ドレイン方向の面とのうち、該第1チャネルとコンタクトする部分以外の部分;該第2ソースの第2ドレイン方向の面のうち、該第2チャネルとコンタクトする部分以外の部分;該第1ドレインの第1ソース方向の面のうち、該第1チャネルとコンタクトする部分以外の部分;及び該第2ドレインの第2ソース方向の面のうち、該第2チャネルとコンタクトする部分以外の部分と、を覆うゲート絶縁膜を形成する段階と、
該第1ソース及び該第1ドレインと、該第2ソースと該第2ドレインとの間に介在されるゲート電極を形成する段階と、を含む、三進インバータ製造方法。 - 第2ソースを第1ソースと異なる導電型にドーピングし、第2ドレインを第1ドレインと異なる導電型にドーピングする段階をさらに含む、請求項6に記載の三進インバータ製造方法。
- 前記ゲート電極を形成する段階は、第1ソースと第1ドレインとの間と、第2ソースと第2ドレインとの間とのダミーゲートが除去された空間を充填するように、該ゲート電極を形成する段階である、請求項6に記載の三進インバータ製造方法。
- 前記ゲート電極を形成する段階は、ゲート絶縁膜の第1チャネルを取り囲む部分と、該ゲート絶縁膜の第2チャネルを取り囲む部分とを取り囲むように、該ゲート電極を形成する段階である、請求項6に記載の三進インバータ製造方法。
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JP2007013156A (ja) | 2005-06-28 | 2007-01-18 | Samsung Electronics Co Ltd | フィンfetcmosとその製造方法及びそれを備えるメモリ素子 |
US20160020305A1 (en) | 2014-07-21 | 2016-01-21 | Samsung Electronics Co., Ltd. | Thermionically-overdriven tunnel fets and methods of fabricating the same |
JP2018517331A (ja) | 2015-07-10 | 2018-06-28 | ユニスト(ウルサン ナショナル インスティテュート オブ サイエンス アンド テクノロジー) | 3進数論理回路 |
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JP2007013156A (ja) | 2005-06-28 | 2007-01-18 | Samsung Electronics Co Ltd | フィンfetcmosとその製造方法及びそれを備えるメモリ素子 |
US20160020305A1 (en) | 2014-07-21 | 2016-01-21 | Samsung Electronics Co., Ltd. | Thermionically-overdriven tunnel fets and methods of fabricating the same |
JP2018517331A (ja) | 2015-07-10 | 2018-06-28 | ユニスト(ウルサン ナショナル インスティテュート オブ サイエンス アンド テクノロジー) | 3進数論理回路 |
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