TW202221899A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW202221899A
TW202221899A TW110125234A TW110125234A TW202221899A TW 202221899 A TW202221899 A TW 202221899A TW 110125234 A TW110125234 A TW 110125234A TW 110125234 A TW110125234 A TW 110125234A TW 202221899 A TW202221899 A TW 202221899A
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Taiwan
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semiconductor
dummy
stack
layer
gate
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TW110125234A
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English (en)
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楊智銓
徐國修
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置以及半導體裝置的製造方法在此揭露。一種半導體裝置的範例包含第一半導體堆疊以及第二半導體堆疊，該等堆疊位於基板上方，其中各第一半導體堆疊與第二半導體堆疊包含層疊的且相互分開的半導體層；虛設間隔物，位於第一半導體堆疊以及第二半導體堆疊之間，其中虛設間隔物接觸第一半導體堆疊與第二半導體堆疊的各半導體層的第一側壁；以及閘極結構，環繞第一半導體堆疊與第二半導體堆疊的各半導體層的第二側壁、頂面、以及底面。

Description

半導體裝置
本揭露係有關於半導體裝置及其製造方法，且特別係有關於具有魚骨結構之半導體裝置及其製造方法。
積體電路（IC）產業經歷了指數成長。 引入了多閘極裝置以提高裝置性能。其中多閘極裝置的一種實例為鰭式場效電晶體(fin-like field effect transistor；FinFET)裝置。多閘極裝置的另一種實例為奈米片裝置(亦稱為奈米線裝置、奈米環裝置、閘極環繞裝置、閘極全環(gate-all-around；GAA)裝置；或多橋通道(multi-bridge channel)裝置。多閘極裝置與習知互補式金氧半導體(CMOS)製程相容，且能使電晶體的尺寸更大幅度地(aggressive)縮小。
縮小尺寸（例如，較小的間距和臨界尺寸）一直是積體電路（IC）製程中的趨勢。與FinFET裝置相比，雖然奈米片裝置可提供較好的閘極控制效能，但奈米片裝置的最小通道尺寸(minimum channel dimension)比FinFET裝置的最小通道尺寸大許多。除此之外，更大幅度地(aggressively)縮小尺寸對半導體裝置製程引入了更高的複雜度，且為半導體裝置帶來了一些問題。例如，一些製程的圖案形成窗口可能會受相鄰的奈米片堆疊之間有限的距離所拘束。因此，需要對奈米片裝置進行改善，以降低裝置尺寸以及減緩製程的一些問題。
本揭露提供許多不同的實施例。具有魚骨結構的半導體裝置以及其製造方法在此揭露。一種半導體裝置的範例包含：第一半導體堆疊以及第二半導體堆疊、虛設間隔物、以及閘極結構。第一半導體堆疊以及第二半導體堆疊設置於基板上方，其中各第一半導體堆疊與第二半導體堆疊包含層疊的且相互分開的半導體層。虛設間隔物位於第一半導體堆疊以及第二半導體堆疊之間，其中虛設間隔物接觸第一半導體堆疊與第二半導體堆疊的各半導體層的第一側壁。閘極結構環繞第一半導體堆疊與第二半導體堆疊的各半導體層的第二側壁、頂面、以及底面。
另一範例的半導體裝置包含：複數第一半導體堆疊、複數第二半導體堆疊、第一虛設間隔物、第二虛設間隔物、第一閘極結構、以及第二閘極結構。第一半導體堆疊位於基板的第一區之上，第二半導體堆疊位於基板的第二區之上，其中各第一導體堆疊與第二半導體堆疊包含層疊的且相互分開的半導體層。第一虛設間隔物位於第一半導體堆疊之間，第二虛設間隔物位於第二半導體堆疊之間，其中第一虛設間隔物與第一半導體堆疊的半導體層的側壁接觸，且第二虛設間隔物與第二半導體堆疊的半導體層的側壁接觸。第一閘極結構環繞第一半導體堆疊的各半導體層，以及第二閘極結構環繞第二半導體堆疊的各半導體層，其中第一閘極結構的頂部由第一虛設間隔物分開，且第二閘極結構的頂部在第二虛設間隔物的頂面上連續地延伸。
一種半導體裝置的製造方法包含：在基板上形成第一半導體堆疊以及第二半導體堆疊，其中各第一半導體堆疊與該第二半導體堆疊包含複數第一半導體層與複數第二半導體層，第一半導體層與第二半導體層包含不同材料且為交叉堆疊。在第一半導體堆疊以及第二半導體堆疊之間形成虛設間隔物，其中虛設間隔物與第一半導體堆疊的第一半導體層與第二半導體層的第一側壁接觸，且虛設間隔物與第二半導體堆疊的第一半導體層與第二半導體層的第一側壁接觸。選擇性地移除第一半導體堆疊與第二半導體堆疊的第二半導體層。形成金屬閘極結構，金屬閘極結構環繞第一半導體堆疊與第二半導體堆疊的第一半導體層的第二側壁、頂面、以及底面。
以下揭露內容提供了用於實施所提供標的的不同特徵的許多不同實施例或實例。以下描述了部件以及佈置等的特定實例以簡化本揭露內容。當然，該等僅僅是實例，而並不旨在為限制性的。例如，在以下描述中在第二特徵上方或之上形成第一特徵可以包括第一特徵和第二特徵形成為直接接觸的實施例，並且亦可以包括可以在第一特徵與第二特徵之間形成額外特徵，使得第一特徵和第二特徵可以不直接接觸的實施例。
另外，本揭露可以在各種實例中重複參考數字及/或字母。該重複是為了簡單和清楚的目的，並且本身並不代表所論述的各種實施例及/或配置之間的關係。除此之外，在本揭露當中之一特徵在另一特徵之上、與之連接和/或耦合的形成可以包括其中特徵形成為直接接觸的實施方式，並且還可以包括其中可以夾設額外的特徵的形成實施方式，以使得特徵可能不直接接觸。 另外，在空間上相對的用語，例如“下部”，“上部”，“水平”，“垂直”，“上方”，“之上”，“下方”，“之下”，“上”，“下”，“頂部”、 “底部”等及其派生詞（例如，“水平的”，“向下的”，“向上的”等）皆用以使本揭露更容易地描述一個特徵與另一特徵之間的關係。 空間相對術語意在涵蓋裝備以及裝備之特徵的不同取向。更進一步，當一數字或一範圍的數字係用「大約」、「近似」以及類似方式形容時，該字彙的目的是涵蓋包括所述的數字的一定合理範圍內的其他數字，例如在所述的數字+/-10%的範圍或者對於所屬領域的技術人員所能夠理解的其他數值。舉例來說，「大約5nm」這詞彙涵蓋從4.5奈米至5.5奈米的尺寸範圍。
在奈米片裝置中，單一裝置的通道區可包含相互分離的複數層半導體材料(亦可稱為通道半導體層)。在一些實例中，此裝置的閘極設置在裝置的半導體層上方、並排、或是之間。然而，相比於FinFET，奈米片裝置的通道的最小尺寸(minimum dimension)大約為FinFET的鰭片厚度的三倍大。除此之外，由於半導體裝置的大幅度(aggressive)縮小，用以分離相鄰的閘極和磊晶源極/汲極(source/drain)結構的微影製程可能受限於最小相片尺寸(minimum photo size constraints)。
在本揭露中，揭示一種具有魚骨結構的奈米片裝置，以縮小半導體裝置(例如SRAM)的尺寸。虛設間隔物(dummy spacer)設置在鄰近相同類型(N型或P型)的半導體堆疊之間。虛設間隔物可以將相鄰的N型或P型金屬閘極及/或相鄰的N型或P型磊晶源極/汲極(S/D)分離，以減緩製程當中的疊對偏移(overlay shifting)問題。更進一步，相同類型的半導體裝置堆疊之間的距離將被縮小，且半導體裝置(例如，SRAM的單元區域(cell area))的尺寸亦可有效地縮小。
第1圖描繪根據本揭露的一些實施例的方法100的流程圖，而此方法100為製作實例半導體裝置 (以下稱為裝置200)。方法100僅為一實例，而非意圖在請求項所明確地敘述的範圍外限制本揭露。為了執行該方法的不同的實施例，額外的操作可在方法100之前、之中、或之後執行，且部分描述的操作可被取代、移除、或移動。方法100在下面做描述，並且結合其他圖式。其他圖式描述裝置200在方法100的中間步驟的一些三維視圖和剖視圖。特別而言，第2圖描繪實例6T SRAM位元單元的示意圖。第3圖描繪包含單元區域201的實例6T SRAM的俯視佈局圖。第4圖係根據本揭露的一些實施例的單元區域201的初始結構(在此之後稱為裝置200)的三維圖。第5A-18A圖描繪在第3圖與第4圖所示的方法100在中間步驟，沿著A-A’平面(亦即，切在X-Z平面的閘極)拍攝的裝置200的剖面圖。第9B-18B圖描繪在第3圖與第4圖所示的方法100在中間步驟，沿著B-B’平面(亦即，切在X-Z平面的源極/汲極)拍攝的裝置200的剖面圖。需了解的是，在形成虛設閘極結構之前(亦極，第9A圖與第9B圖之前)，沿著A-A’和B-B’平面的剖面圖會是一樣的。
如第2圖所描繪，6T SRAM單元通常包含兩個P型上拉(pull-up；PU)電晶體、兩個N型下拉(pull-down；PD)電晶體、以及兩個N型通道閘(pass-gate；PG)電晶體。PD電晶體與PU電晶體形成交叉偶接的反向器。參考第3圖，6T SRAM佈局包含裝置200，而裝置200包含相鄰的N型FET(亦即NFET，在裝置200的左手方)以及相鄰的P型FET(亦即PFET，在裝置200的右手方)。本揭露揭示了裝置200的結構與製作方法。雖然本揭露以6T SRAM的單元區(亦即，裝置200)為實例，可以了解裝置200可為在積體電路(IC)製程中製造的另一中間裝置，或者積體電路的一部份，而該IC或IC之一部份可包含邏輯電路(例如，8電晶體 SRAM、10電晶體 SRAM、以及/或其他邏輯電路)、靜態部件(如電阻、電容以及電感)，動態部件(如P型FET(PFET)、N型FET(NFET)、金氧半導體場效電晶體(MOSFET)、互補式金氧半導體(CMOS)電晶體、雙極電晶體、高電壓電晶體；高頻率電晶體、以及/或其他記憶單元)。裝置200可為積體電路(IC)的一部分或核心區域(常稱為邏輯區域)、週邊區域(常稱為輸入/輸出(I/O)區域)、虛設(dummy)區域、其他合適的區域、或者前述的組合。在一些實施例中，裝置200可為IC晶片、系統上晶片(SoC)、或其中一部份。本揭露不只限於任何數量的裝置或裝置區域，或是任何裝置配置。
參考第1、4與5A圖，在步驟102中，形成裝置200的初步半導體結構。如第4與5A圖所描述，裝置200包含基板202。在描述的實施例中，基板202為塊材(bulk)矽基板。替代地或附加地，基板202包含另一單晶半導體，例如鍺、化合物半導體(compound semiconductor)、合金半導體、或者前述之組合。或者，基板202可為絕緣層上半導體(semiconductor-on-insulator；SGOI)基板，例如絕緣層上矽(silicon-on-insulator；SOI)基板、絕緣層上矽鍺(silicon germanium-on-insulator；SGOI)基板、或者絕緣層上鍺(germanium-on-insulator；GOI)基板。基板202可為不同的摻雜物所摻雜，而形成不同的摻雜區。在所描述的實施例中，基板202包含NFET區202N，NFET區202N包含被P型摻雜物所摻雜的P型摻雜基板區(例如p井)，而P型摻雜物例如硼(如 11B，BF 2)、銦、其他P型摻雜物、或前述之組合。基板202亦包含PFET區202P，PFET區202P包含被N型摻雜物所摻雜的N型摻雜基板區(例如n井)，而N型摻雜物例如磷(如 31P)、砷、其他N型摻雜物、或前述之組合。在一些實施例中，基板202包含P型摻雜物與N型摻雜物的組合所形成的摻雜區。電子注入製程、擴散製程、以及/或其他合適的摻雜製程皆可用以形成不同的摻雜區。
裝置200包含在基板202上形成的交替的半導體層，例如半導體層210A以及半導體層210B。半導體層210A包含第一半導體材料，而半導體層210B包含與第一半導體材料不同之第二半導體材料。前述半導體層210A與210B之不同的半導體材料具有不同的氧化速率以及/或蝕刻選擇性。在一些實施例中，半導體層210A的第一半導體材料與基板202的材料相同。例如，半導體層210A包含矽(Si，如基板202)，以及半導體210B包含矽鍺(silicon germanium；SiGe)。因此，交替的SiGe層/Si層/SiGe層/Si層/…從底至頂設置。在一些實施例中，最頂層的半導體層之材料可以與或是不與最底層的半導體層之材料相同。在所描述的實施例中，最頂層的半導體層為包含矽鍺的半導體層210B。最頂層的半導體層210B可當作硬遮罩層，使得下層的半導體層210A與210B能在後續的蝕刻製程受頂層的保護。在一些實施例中，半導體層210A的形成並沒有執行有意的摻雜。在其他之實施例中，半導體層210A可被P型摻雜物或N型摻雜物所摻雜。半導體層210A與210B的數量取決於裝置200的設計要求。例如，裝置200可包含半導體層210A與210B之各1至10層。在一些實施例中，半導體層210A與210B的不同層在Z方向具有相同的厚度。在一些實施例中，半導體層210A與210B的不同層在Z方向具有不同的厚度。在一些實施例中，半導體層210A及/或半導體層210B由合適的磊晶製程所形成。例如，包含矽鍺與矽的半導體層交替地在基板202上形成，而形成方式為分子束磊晶(molecular beam epitaxy；MBE)製程、化學氣相沉積(chemical vapor deposition；CVD)製程，例如金屬有機化學氣相沉積(metal organic CVD；MOCVD)製程、以及/或其他合適的磊晶成長製程。
在此之後，交替的半導體層210A與210B被圖案化以形成堆疊210(亦可稱為半導體堆疊)。在所描述的實施例中，堆疊210包含在NFET區202N形成的堆疊210N以及在PFET區202P形成的堆疊210P。在一些實施例中，為了形成第4與5A圖中鰭片狀的堆疊210，不同光阻微影製程以及蝕刻製程可被使用。例如，首先，在裝置200上形成圖案化的光阻遮罩。根據裝置200的設計要求，圖案化的光阻遮罩會覆蓋鰭片的位置。其次，利用圖案化的光阻遮罩執行一或多個蝕刻製程以移除半導體層210A及210B的暴露部分。半導體層210A及210B的剩餘部分形成鰭片形狀堆疊210。在一些實施例中，基板202的頂部部分也遭移除。蝕刻製程包含乾蝕刻、濕蝕刻、其他合適的蝕刻製程、或前述之組合。接下來利用任何妥當的方法(例如，電漿灰化(plasma ashing)製程)移除光阻遮罩。
參考第4與5A圖，在NFET區202N中的相鄰堆疊210N之間的距離為D1，在PFET區202P中的相鄰堆疊210P之間的距離為D2，以及堆疊210N與210P之間的最近距離為D3。在一些實施例中，距離D1為大約8奈米至大約10奈米；距離D2為大約8奈米至大約10奈米；以及距離D3為大約39奈米至大約42奈米。在一些實施例中，距離D3為距離D1或D2的大約4倍至大約7倍大。距離D1、D2及/或D3不能太大，否則裝置200的尺寸將無法有效地縮小。距離D1、D2以及/或D3不能太小，不然將很難在PFET區中的相鄰堆疊210P或NFET區中的相鄰堆疊210N之間的虛設間隔物212填滿，而使在一些情形下的寄生電容增加。
裝置200也包含在堆疊210之間的溝槽形成的隔離結構204，以分離與隔開裝置200的主動區。在一些實施例中，一或多個介電材料，例如二氧化矽(silicon dioxide；SiO)及/或氮化矽(silicon nitride；SiN)，在基板202上沿著堆疊210的側壁設置。介電材料亦可由CVD(例如，電漿增強化學氣相沉積法(plasma enhanced CVD；PECVD))、物理氣相沉積(physical vapor deposition；PVD)、熱氧化、或其他技術。接者，介電材料被凹陷(recessed)/回蝕(例如，被蝕刻以及/或化學機械研磨(chemical mechanical polishing；CMP))以形成隔離結構204。
參考第1、6A與7A圖，在步驟104中，虛設間隔物212N與212P(兩者皆稱為虛設間隔物212)在NFET區202N的相鄰堆疊210N之間形成，或者在PFET區202P的相鄰堆疊210P之間形成。換句話說，虛設間隔物212在同類型(N型或P型)FET的堆疊210之間形成。參考第6A圖，虛設間隔層212’在堆疊210與隔離結構204上設置。在一些實施例中，虛設間隔層包含基於氮化物的介電材料(例如，氮化矽(silicon nitride；SiN)、氮碳化矽(silicon carbonitride、SiCN)、其他基於氮化物的介電材料、或前述的組合)，或者是基於氧化物的介電材料(例如，氧化矽(silicon oxide；SiO)、碳氧化矽(silicon oxycarbide；SiOC)、其他基於氧化物的介電材料、或前述的組合)。在一些實施例中，虛設間隔層212’為沉積製程所形成，例如原子層沉積(atomic layer deposition；ALD)、CVD、PVD、其他沉積製程，或前述之組合)。沉積過程受控制，使得在NFET區202N中的堆疊210N之間的間隙與在PFET區202P中的堆疊210P之間的間隙被填補，而不同FET(意即相鄰堆疊210N及210P)的相鄰堆疊210之間的間隙沒有填補，因而於其間形成溝槽214。參考第6A圖，虛設間隔層212’的厚度T1本質上相等或大於堆疊210N之間的距離D1的一半(50%)及/或虛設間隔層212’的厚度T1本質上相等或大於堆疊210P之間的距離D2的一半(50%)。距離D1或D2本質上等於或小於兩倍(200%)的厚度T1。在所描述距離D1或D2為大約8奈米至大約10奈米的實施例中，厚度T1為大約4奈米至大約6奈米，使得虛設間隔層的介電材料能填充堆疊210N之間的間隙或堆疊210P之間的間隙。
在此之後，參考第7A圖，虛設間隔層212’的外層部分被移除，而保留了相鄰堆疊210N之間或相鄰堆疊210P之間的內層部分。在一些實施例中，虛設間隔層212’的外層部分由等向性蝕刻(isotropic etching)製程(例如乾蝕刻、濕蝕刻、或前述之組合)所移除。虛設間隔層212’所剩餘的內層部分在堆疊210N之間形成虛設間隔物212N，以及在堆疊210P之間形成虛設間隔物212P。在一些實施例中，虛設閘極間隔物212的頂層部分可由蝕刻製程的過程當中移除。虛設間隔物212的頂部表面位於半導體層210B的頂層之下，且位於半導體層210A的頂層之上，或實質上與半導體層210A的頂層共面。意即，蝕刻製程可被控制，使得虛設閘極間隔物212的最頂部所遭移除的部分比半導體層210B(當作蝕刻製程的硬遮罩)的最頂部的厚度還要少，而虛設間隔層212’的外層部分為實質上完全移除。如第7A圖所描述，同類型FET中的堆疊210(例如相鄰的堆疊210N或相鄰的堆疊210P)為分別由虛設間隔物212N或212P所分開。接觸堆疊210N的半導體層210A與210B之側壁的虛設間隔物212N在X方向具有寬度D1，且接觸堆疊210P的半導體層210A與210B之側壁的虛設間隔物212P在X方向具有寬度D2。
參考第1與8A圖，在步驟106中，虛設介電層216在基板202上形成。在形成虛設介電層216之前，從堆疊210的頂部移除最頂層的半導體層210B。在一些實施例中，可用選擇性的蝕刻製程來移除最頂層的半導體層210B，因為最頂層的半導體層210B的材料提供不同於下層的半導體層210A的氧化速率以及/或蝕刻選擇性。選擇性的蝕刻製程可以是乾蝕刻、濕蝕刻、或前述的組合。
在此之後，虛設介電層216設置在堆疊210、虛設間隔物212、以及隔離結構204之上。在以下的所敘述的閘極取代製程中，虛設介電層216可保護虛設間隔物以及或半導體層210A與210B。虛設介電層216的材料應提供虛設間隔物212的蝕刻選擇性。例如，若是虛設間隔物212包含基於氮化物的介電材料，虛設介電層216包含基於氧化物的介電材料；或者是虛設間隔物212包含基於氧化物的介電材料，虛設介電層216包含基於氮化物的介電材料。在一些實施例中，介電材料可包含氮化矽(SiN)、氮碳化矽(SiCN)、氧化矽(SiO)、碳氧化矽(SiOC)、其他合適的介電材料、或前述的組合。在一些實施例中，虛設介電層216由ALD、CVD、PVD、其他沉積製程、或前述的組合所形成。如第8圖所描述，虛設介電層216具有厚度T2。在一些實施例中，厚度T2為大約3奈米至大約10奈米，使得虛設介電層216的厚度夠厚，足以保護虛設間隔物212以及堆疊210，且夠薄，使得虛設介電層的形成與後續移除的時間及成本不會增加。
參考第1、9A以及9B圖，在步驟108中，虛設閘極結構220在堆疊210上形成。每個虛設閘極結構220作為後續形成金屬閘極結構的一個預留空間。在一些實施例中，虛設閘極結構220沿著X方向延伸且橫跨各個堆疊210。虛設閘極結構220覆蓋堆疊210的通道區，堆疊210的通道區夾設在源極區以及汲極區(兩者合稱為源極/汲極區)之間。每個虛設閘極結構220可包含許多虛設閘極層，例如，在堆疊210上的介面層、在介面層上的虛設閘極電極(例如，包含多晶矽)、在虛設閘極電極上的一或多個硬遮罩層、或其他合適的層。虛設閘極結構220由沉積製程、微影製程、蝕刻製程、其他合適製程、或前述的組合所形成。例如，不同的虛設閘極層沉積在堆疊210上。之後，執行微影製程以形成覆蓋在堆疊210上的遮罩。在此之後，利用微影遮罩蝕刻不同的虛設閘極層，以形成虛設閘極結構220。之後，微影遮罩用任何適當的方法進行移除。在一些實施例中，包含介電材料的閘極間隔物(未圖示)可沿著虛設閘極結構220的側壁形成，並且前述的閘極間隔物被認為是虛設閘極結構220的一部份。
參考第1、10A、10B、11A以及11B圖，在步驟110中，磊晶源極/汲極特徵230N與230P(兩者稱為磊晶源極/汲極特徵230)在堆疊210的源極/汲極區上形成。參考第10A與10B圖，首先，在源極/汲極區中的虛設介電層216以及堆疊210被蝕刻製程移除。在一些實施例中，沿著虛設閘極結構220的側壁移除虛設介電層216以及堆疊210以形成在第10B圖的源極/汲極溝槽224。在一些實施例中，在移除堆疊210之前先移除虛設介電層216。由於虛設介電層216以及虛設間隔物212的材料提供不同的蝕刻選擇性，移除虛設介電層216時，虛設間隔物212實質上不受影響。接著進行源極/汲極蝕刻製程以移除源極/汲極區上的堆疊210的部分。蝕刻製程可以為乾蝕刻(例如，反應離子蝕刻(reactive ion etching；RIE))、濕蝕刻、或前述的組合。蝕刻製程的持續時間受控制，使得在源極/汲極區的各半導體層210A與210B的部分遭移除，意即，在源極/汲極溝槽224中的各半導體層210A與210B的側壁為暴露的。在一些實施例中，內部間隔物(未圖示)可在此後沿著半導體層210B的邊緣部分形成。
之後，參考第11A及11B圖，分別地在NFET區202N以及PFET區202P上方的源極/汲極溝槽224中磊晶成長源極/汲極特徵230N與230P。磊晶源極/汲極特徵可包含不同類型(N型或P型) 源極/汲極特徵的不同半導體材料。例如，在NFET區202N中，N型磊晶源極/汲極特徵230N可包含例如矽以及/或碳的材料，其中包含矽的磊晶層或者包含矽-碳的磊晶層經由磷、砷、其他N型摻雜物、或前述的組合所摻雜(例如，形成Si:P磊晶層、Si:C磊晶層、或Si:C:P磊晶層)。在PFET區202P中，P型磊晶源極/汲極特徵230P可包含例如矽以及/或鍺的材料，其中包含矽-鍺的磊晶層經由硼、碳、其他P型摻雜物、或前述的組合所摻雜(例如，形成Si:Ge:B磊晶層、或Si:Ge:C磊晶層)。在一些實施例中，源極/汲極特徵230包含相互堆疊的多層結晶層。在一些實施例中，磊晶源極/汲極特徵230包含可在通道區達到理想拉張應力以及/或壓縮應力的材料以及/或摻雜物。在許多實施例中，磊晶源極/汲極特徵230的不同磊晶層可包含相同或不同的半導體材料。
在源極/汲極溝槽224中實施磊晶製程以長出源極/汲極特徵230。磊晶製程包含CVD沉積(例如，氣相磊晶(vapor-phase epitaxy；VPE)、超高真空CVD(ultra-high vacuum CVD；UHV-VCD)、LPCVD、以及/或PECVD)、分子束磊晶(molecular beam epitaxy)、其他合適的選擇性磊晶成長(SEG)製程、或前述的組合。參考第11B圖，基於虛設間隔物212，同類型FET的相鄰的源極/汲極特徵230，意即NFET區202N中的相鄰N型源極/汲極特徵或PFET區202P中的相鄰P型源極/汲極特徵，在X方向並沒有結合在一起。意即，虛設間隔物212將同類型FET的相鄰源極/汲極特徵230隔開。
在習知的奈米片半導體裝置中，為了隔開相鄰同類型的源極/汲極特徵，半導體堆疊需要特定的距離。然而，在本揭露中，同類型源極/汲極特徵由虛設間隔物隔開。因此，相同半導體堆疊之間的距離縮短至距離D1或D2，意即，虛設間隔物212N或212P的寬度。在一些實施例中，本揭露的同類型的半導體堆疊之間的距離可縮小為習知奈米片半導體裝置的的同類型的半導體堆疊之間的距離大約20%至大約40%。因此，裝置尺寸更大幅度地(aggressively)縮小了。此外，同類型源極/汲極特徵之間的虛設間隔物可用來隔開源極/汲極接點(參照第18B與19B圖)，因此形成源極/汲極接點時可緩解疊對偏移問題。
在此之後，參考第1、12A-17A、以及12B-17B圖，在步驟112中，執行閘極取代製程將虛設閘極結構220取代成金屬閘極結構244。參考第12A與12B圖，在源極/汲極區中的在磊晶源極/汲極特徵230、虛設間隔物212、以及隔離結構204上方形成層間介電(interlayer dielectric；ILD)層232。在一些實施例中，層間介電層232包含有別於虛設間隔物212的介電材料。在一些實施例中，層間介電質層232包含低介電系數(low-k)(K＜3.9)介電材料，例如，四乙氧基矽烷(tetraethylorthosilicate；TEOS)氧化物、未摻雜的矽酸鹽(silicate)玻璃、或摻雜過的氧化矽例如硼磷矽玻璃(borophosphosilicate glass；BPSG)、氟矽玻璃(FSG)、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼摻雜矽玻璃(boron doped silicon glass；BSG)、其他合適的介電材料、或前述的組合。層間介電層232可由沉積製程如CVD、流動式CVD(flowable CVD；FCVD)、旋塗式玻璃(spin-on-glass；SOG)、其他合適的方法、或前述的組合。在此之後，可執行平坦化製程(例如，CMP)以移除裝置200的頂部(例如，層間介電層232以及虛設閘極結構220的硬遮罩層的頂部)以暴露虛設閘極電極。參考第12B圖，剩餘的層間介電層232覆蓋在源極/汲極區中的虛設間隔物212，使得在源極/汲極區的虛設間隔物212在後續的虛設間隔物回蝕製程中受保護。
參考第13A與13B圖，移除虛設閘極結構220以形成閘極溝槽234，並暴露堆疊210的通道區。在一些實施例中，移除虛設閘極結構220包含一或多道蝕刻製程，例如濕蝕刻、乾蝕刻、或前述的組合。背向虛設間隔物212的半導體層210A與210B的側壁在閘極溝槽234為暴露狀態。
在此之後，參考第14A與14B圖，半導體層210B從閘極溝槽234選擇性地移除。基於半導體層210A的材料(例如，SiGe)以及半導體層210B的材料(例如，矽)的不同的氧化速率以及/或蝕刻選擇性，只有半導體層210B遭移除，而半導體層210A實質上維持不變。在一些實施例中，半導體層210B的選擇性移除可包含氧化製程，接著選擇性蝕刻製程。例如，先選擇性氧化半導體層210B以包含矽鍺氧化物(SiGeOx)材料。接著，執行選擇性蝕刻製程以利用合適的蝕刻劑例如氫氧化銨(ammonium hydroxide；NH4OH)或氟化氫(hydro fluoride；HF)以移除矽鍺氧化物。在一些實施例中，半導體層210A在選擇性蝕刻製程中僅些微地蝕刻或不蝕刻。經此，半導體層210A在通道區為懸空且沿著方向(Z方向)堆疊，該方向實質上與基板202(X-Y平面)的頂面垂直。懸空的半導體層210A亦稱為通道半導體層。參考第14A圖，同類型FET的半導體層210A以及在半導體層210A之間的虛設間隔物212在X-Z平面形成魚骨結構。意即，堆疊210N的半導體層210A以及虛設間隔物212N在NFET區202N形成魚骨結構，以及堆疊210P的半導體層210A以及虛設間隔物212P在PFET區202P形成魚骨結構。半導體層210A的側壁接觸虛設間隔物212N或212P，而半導體層210A的其他側(包含頂面、底面以及另外一側壁)在閘極溝槽234中暴露。
參考第3、15A、15B圖，沿著A-A’線上，裝置200的閘極結構在NFET區為不連接的，而在PFET區為連續的，並且在通道區的虛設間隔物212P的頂層部分會被回蝕(意即，虛設間隔物回蝕)。例如，可形成光阻遮罩236以覆蓋NFET區202N。在堆疊210P(在通道區)之間的虛設間隔物212P的頂層部分會被蝕刻製程(例如濕蝕刻、乾蝕刻、或前述的組合)所移除。由於層間介電層232的保護，磊晶源極/汲極特徵230P(在源極/汲極區)之間的虛設間隔物212P不受影響。如第15A、15B圖所描述，堆疊210P的頂面實質上與半導體層210A的頂部的頂面共面。如所描述的實施例中，通道區的虛設間隔物212P的頂面在源極/汲極區的虛設間隔物212P的頂面之下，而通道區的虛設間隔物212N的頂面實質上與源極/汲極區的虛設間隔物212N的頂面共面。
在此之後，參考第16A、16B、17A、17B圖，在堆疊210的通道區形成金屬閘極結構246N與246P(兩者稱為金屬閘極結構246)。金屬閘極結構246環繞著各懸空半導體層210A的暴露的側邊。在一些實施例中，各金屬閘極結構246N與246P包含閘極介電層、金屬閘極電極、以及其他合適的層。參考第16A與16B圖，沉積閘極介電層240N與240P(兩者稱為閘極介電層240)以環繞閘極溝槽234中的半導體層210A的暴露的側邊。具體而言，暴露的側邊包含半導體層210A之背向虛設間隔物212的側壁、頂面、以及底面。在一些實施例中，閘極介電層240包含高介電係數(high-k)(K＞3.9)介電材料，例如，二氧化鉿(HfO 2)、矽酸鉿(HfSiO)、氮氧化矽鉿(HfSiON)、鑭酸鉿(HfLaO)、鉭酸鉿(HfTaO)、鈦酸鉿(HfTiO)、鋯酸鉿(HfZrO)、鉿鋁氧化物(HfAlO x)、氧化鋯(ZrO)、二氧化鋯(ZrO 2)、矽酸鋯(ZrSiO 2)、一氧化鋁(AlO)、矽酸鋁(AlSiO)、氧化鋁(Al 2O 3)、氧化鈦(TiO)、二氧化鈦(TiO 2)、氧化鑭(LaO)、LaSiO、三氧化二鉭(Ta 2O 3)、五氧化二鉭(Ta 2O 5)、氧化釔(Y 2O 3)、鈦酸鍶(SrTiO 3)、鋯酸鋇(BaZrO)、鈦酸鋇(BaTiO 3；BTO)、鈦酸鍶鋇((Ba,Sr)TiO 3；BST)、氮化矽(Si 3N 4)、二氧化鉿-氧化鋁(hafnium dioxide-alumina；HfO 2-Al 2O 3)合金、其他合適的high-k介電材料、或前述的組合。閘極介電層240可由CVD、PVD、ALD、以及/或其他合適的方法沉積。參考第16A圖，閘極介電層240N的頂面在虛設間隔物212N的頂面之下，以及閘極介電層240P的頂面在虛設間隔物212P的頂面之上。意即，閘極介電層240N的頂層部分被虛設間隔物212N隔開，以及閘極介電層240P的頂層部分持續性地在虛設間隔物212P的頂面上延伸。
參考第17A與17B圖，在閘極介電層240N與240P上形成閘極電極。各閘極電極包含一個或多個功函數金屬(work function metal；WFM)層以及塊材金屬。WFM層被配置以調適電晶體的相應的功函數以達到理想的臨界電壓Vt。並且塊材金屬被配置以作為函數閘極結構的主要導電部分。參考第17A圖，功函數金屬(WFM)242N與WFM 242P(兩者稱為WFM 242)各別在閘極介電層240N與240P上形成。在一些實施例中，WFM層的材料可包含鋁化鈦(TiAl)、碳化鋁鈦(TiAlC)、碳化鋁鉭(TaAlC)、氮化鋁鈦(TiAlN)、氮化鈦(TiN)、鈦矽氮化物(TSN)、氮化鉭(TaN)、氮化碳鎢(WCN)、鉬(Mo)、其他材料、或前述的組合。WFM 240可由任何合適的方法形成，例如CVD、ALD、PVD、電鍍(plating)、化學氧化、熱氧化、其他合適的方法、或前述的組合。如第17A圖所描述，WFM 240環繞半導體層210A所暴露的側邊。WFM 240N的頂面為虛設間隔物212N的頂面之下，而WFM 240P的頂面為虛設間隔物212P的頂面之上。意即，WFM 242N的頂部為虛設間隔物212N所分開，而WFM 240P的頂部持續性地在虛設間隔物212P的頂面上延伸。
在此之後，塊材金屬244(例如包含鋁、鎢、銅、或前述的組合)在WFM 242的上方的閘極溝槽234中形成。在一些實施例中，塊材金屬244由任何合適的方法形成，例如CVD、ALD、PVD、電鍍、化學氧化、熱氧化、其他合適的方法、或前述的組合。在所描述的實施例中，閘極介電層240N、WFM 242N、以及塊材金屬244形成金屬閘極結構246N，以及閘極介電層240P、WFM 242P、以及塊材金屬244形成金屬閘極結構246P。接著執行平坦化製程(例如CMP)以移除多於塊材金屬材料，使得虛設間隔物212N的頂面為暴露的。由此，金屬閘極結構246N的頂部由虛設間隔物212N所分開，而金屬閘極結構246P的頂部持續性地在虛設間隔物212P上延伸。參考第17B圖，層間介電層232的頂部亦由平坦化製程移除，且在源極/汲極區的虛設間隔物212N與212P的頂面亦為暴露的。
請參考第1、18A以及18B圖，在步驟114中，在磊晶源極/汲極特徵230上形成源極/汲極接點250。在一些實施例中，源極/汲極接點250包含導電材料，例如鋁、鎢、銅、或前述的組合。源極/汲極接點250可由許多製程，包含微影製程、蝕刻製程、以及/或沉積製程所形成。例如，形成光阻遮罩以暴露源極/汲極接點位置上的層間介電層232的部分。接著，執行蝕刻製程以移除層間介電層232的暴露部分。由於層間介電層232的材料有別於虛設間隔物212，在蝕刻製程中虛設間隔物212實質上不受影響。接下來，形成源極/汲極接點250的導電材料以取代層間介電層232的移除部分。虛設間隔物212係用以分開源極/汲極接點250。
請參考第1、19A以及19B圖，在步驟116中，進一步執行製程以完成裝置200的製程。例如，在裝置200上形成其他多層相互連接特徵(例如金屬線/接點/導孔270、以及層間介電層260以及/或蝕刻停止層，相互連接特徵被配置以連接許多特徵以便形成包含不同半導體裝置的功能電路。
與習知的奈米片半導體裝置相比，習知的奈米片半導體裝置並沒有用以隔開同類型FET的虛設間隔物，而本揭露的半導體裝置具有較小的尺寸，因為虛設間隔物能分開以及縮小同類型半導體堆疊之間的距離。進一步而言，對應於半導體裝置的設計需求，虛設間隔物亦可以有效地分開同類型的磊晶源極/汲極特徵，且可用以分開金屬閘極結構。因此，可減緩微影製程中的疊對偏移問題同時能有效地縮小裝置尺寸。
雖然不意圖為限制性，但本揭露的一或多個實施例對半導體裝置以及半導體裝置的形成製程提供許多優點。例如，本揭露的實施例提供的半導體裝置具有在同類型FET的通道半導體層之間形成的虛設間隔物。通道半導體層與虛設間隔物形成魚骨結構，以縮小裝置尺寸，分隔磊晶源極/汲極特徵及/或金屬閘極結構，以及減緩製程當中的疊對偏移問題。
本揭露提供許多不同的實施例。具有魚骨結構的半導體裝置以及其製造方法在此揭露。一種半導體裝置的範例包含：第一半導體堆疊以及第二半導體堆疊、虛設間隔物、以及閘極結構。第一半導體堆疊以及第二半導體堆疊設置於基板上方，其中各第一半導體堆疊與第二半導體堆疊包含層疊的且相互分開的半導體層。虛設間隔物位於第一半導體堆疊以及第二半導體堆疊之間，其中虛設間隔物接觸第一半導體堆疊與第二半導體堆疊的各半導體層的第一側壁。閘極結構環繞第一半導體堆疊與第二半導體堆疊的各半導體層的第二側壁、頂面、以及底面。
在一些實施例中，半導體裝置的範例進一步包含：複數磊晶源極/汲極特徵，接觸虛設間隔物的側壁。在一些實施例中，半導體裝置的範例進一步包含複數源極/汲極接點，位於磊晶源極/汲極特徵之上且接觸虛設間隔物的側壁。在一些實施例中，半導體裝置的範例進一步包含隔離結構，隔開半導體裝置的複數主動區，並且接觸虛設間隔物的底面。在一些實施例中，虛設間隔物的頂面位於第一半導體堆疊與第二半導體堆疊的最頂層的半導體層的頂面之上，以及虛設間隔物將閘極結構分開，閘極結構包含閘極介電層以及在閘極介電層上的閘極電極。在一些實施例中，閘極結構包含閘極介電層以及在閘極介電層上的閘極電極，閘極介電層與閘極電極在虛設間隔物的頂面上連續地延伸。在一些實施例中，虛設間隔物的寬度為大約8奈米至大約10奈米。
另一範例半導體裝置包含：複數第一半導體堆疊、複數第二半導體堆疊、第一虛設間隔物、第二虛設間隔物、第一閘極結構、以及第二閘極結構。第一半導體堆疊位於基板的第一區之上，第二半導體堆疊位於基板的第二區之上，其中各第一導體堆疊與第二半導體堆疊包含層疊的且相互分開的半導體層。第一虛設間隔物位於第一半導體堆疊之間，第二虛設間隔物位於第二半導體堆疊之間，其中第一虛設間隔物與第一半導體堆疊的半導體層的側壁接觸，且第二虛設間隔物與第二半導體堆疊的半導體層的側壁接觸。第一閘極結構環繞第一半導體堆疊的各半導體層，以及第二閘極結構環繞第二半導體堆疊的各半導體層，其中第一閘極結構的頂部由第一虛設間隔物分開，且第二閘極結構的頂部在第二虛設間隔物的頂面上連續地延伸。
在一些實施例中，在通道區中的第二虛設間隔物的頂面位於在源極/汲極區中的第二虛設間隔物的頂面之下。在一些實施例中，第一半導體堆疊與第二半導體堆疊之間的最短距離為第一虛設間隔物的寬度或第二虛設間隔物的寬度的大約4倍至大約7倍大。
一種半導體裝置的製造方法包含：在基板上形成第一半導體堆疊以及第二半導體堆疊，其中各第一半導體堆疊與該第二半導體堆疊包含複數第一半導體層與複數第二半導體層，第一半導體層與第二半導體層包含不同材料且為交叉堆疊。在第一半導體堆疊以及第二半導體堆疊之間形成虛設間隔物，其中虛設間隔物與第一半導體堆疊的第一半導體層與第二半導體層的第一側壁接觸，且虛設間隔物與第二半導體堆疊的第一半導體層與第二半導體層的第一側壁接觸。選擇性地移除第一半導體堆疊與第二半導體堆疊的第二半導體層。形成金屬閘極結構，金屬閘極結構環繞第一半導體堆疊與第二半導體堆疊的第一半導體層的第二側壁、頂面、以及底面。
在一些實施例中，範例的製造方法進一步包含：在第一半導體堆疊與第二半導體堆疊之上沉積虛設間隔物層，虛設間隔物層的部份填滿第一半導體堆疊與第二半導體堆疊之間的空間。等向性地移除(isotropically remove)第一半導體堆疊與第二半導體堆疊外面的虛設間隔物層，且保留填滿第一半導體堆疊與第二半導體堆疊之間的空間的虛設間隔物層的部份以形成該虛設間隔物，其中虛設間隔物的頂面位於第一半導體堆疊與第二半導體堆疊的最頂層的第一半導體層的頂面之上。在一些實施例中，製造方法進一步包含：在第一半導體堆疊、第二半導體堆疊以及虛設間隔物之上沉積虛設介電層。在一些實施例中，製造方法進一步包含：在虛設間隔物、虛設介電層、第一半導體堆疊與第二半導體堆疊之上沉積虛設閘極結構。在一些實施例中，選擇性地移除第二半導體層包含：移除虛設閘極結構以形成一閘極溝槽，其中第一半導體層與第二半導體層的第二側壁在閘極溝槽中暴露；選擇性地從閘極溝槽移除第二半導體層，使得各第一半導體層的第二側壁、頂面、以及底面在閘極溝槽暴露。在一些實施例中，其中形成金屬閘極結構包含：在各第一半導體層的第二側壁、頂面、以及底面的周圍沉積閘極介電層；在閘極介電層上沉積功函數金屬；以及在功函數金屬上形成塊材金屬。在一些實施例中，製造方法進一步包含：在形成金屬閘極結構之前移除在通道區的虛設間隔物的頂部，使得虛設間隔物的頂面為實質上與第一半導體層的頂面共面。
在一些實施例中，製造方法進一步包含：移除在第一半導體堆疊與第二半導體堆疊的複數源極/汲極區的第一半導體層與第二半導體層，以形成源極/汲極溝槽；以及在源極/汲極溝槽中磊晶成長複數源極/汲極特徵，其中源極/汲極特徵由虛設間隔物分開。在一些實施例中，製造方法進一步包含：在源極/汲極區的虛設間隔物以及源極/汲極特徵之上，形成一層間介電質層。在一些實施例中，製造方法進一步包含：形成複數源極/汲極接點，接觸在源極/汲極區的虛設間隔物的側壁。
前述內容概述了幾個實施例的特徵使得本領域技術人員可更容易了解本揭露的各面向。 本領域技術人員應該理解，他們可以容易地將揭露用作設計或修改其他製程和結構的基礎，以實現與本文介紹的實施例相同的目的和/或實現相同的優點。 本領域技術人員還應該認知到，等效的構造不脫離本揭露的精神和範圍，並且在不脫離本揭露的精神和範圍的情況下，它們可以進行各種改變，替換和變更。
100:方法 102-116:步驟 200:半導體裝置(裝置) 202:基板 202N:NFET區 202P:PFET區 204:隔離結構 210N、210P:堆疊 210A、210B:半導體層 210N、210P:堆疊 212、212N、212P:虛設間隔物 212’:虛設間隔層 214:溝槽 216:虛設介電層 220:虛設閘極結構 224:源極/汲極溝槽 230N:N型磊晶源極/汲極特徵 230P:P型磊晶源極/汲極特徵 232、260:層間介電層 234:閘極溝槽 236:光阻遮罩 240N、240P:閘極介電層 242N、242P:函數金屬(WFM) 244:塊材金屬 246N、246P:金屬閘極結構 250:源極/汲極接點 270:金屬線/接點/導孔 D1,D2,D3:距離 T1,T2:厚度 A- A’:剖面線 B- B’:剖面線
本揭露的各項層面在以下的實施方式搭配附帶的圖示一同閱讀會有最好的理解。需要強調的是，按照行業標準慣例，諸多特徵並沒有按比例繪製。事實上，諸多特徵的尺寸可能為任意地增大或縮小以便做描述。 第1圖描繪依據本揭露的一些實施例之用以製作一半導體裝置的一實例方法的流程圖 第2圖描繪六電晶體(six-transistor；6T)靜態隨機存取記憶體(static random-access memory；SRAM)位元單元的一實例的一示意圖。 第3圖描繪該六電晶體SRAM位元單元的實例的一俯視佈置圖。 第4圖描繪對應於本揭露的一些實施例的最初的半導體裝置實例的三維透視圖。 第5A圖、第6A圖、第7A圖、第8A圖、第9A圖、第10A圖、第11A圖、第12A圖、第13A圖、第14A圖、第15A圖、第16A圖、第17A圖、第18A圖、以及第19A圖描繪對應於本揭露的一些實施例在第1圖所示的方法在中間階段的示意圖和三維透視圖且沿著A-A’線的該半導體裝置的剖面圖。 第9B圖、第10B圖、第11B圖、第12B圖、第13B圖、第14B圖、第15B圖、第16B圖、第17B圖、第18B圖、以及第19B圖描繪對應於本揭露的一些實施例在第1圖所示的方法在中間階段的示意圖和三維透視圖且沿著B-B’線的該半導體裝置的剖面圖。
無
200:裝置
202:基板
202N:NFET區
202P:PFET區
204:隔離結構
210N、210P:堆疊
212N、212P:虛設間隔物
240N、240P:閘極介電層
234:閘極溝槽

Claims (1)

  1. 一種半導體裝置，包含： 一第一半導體堆疊以及一第二半導體堆疊，設置於一基板上方，其中各該第一半導體堆疊與該第二半導體堆疊包含層疊的且相互分開的半導體層； 一虛設間隔物，位於該第一半導體堆疊以及該第二半導體堆疊之間，其中該虛設間隔物接觸該第一半導體堆疊與該第二半導體堆疊的各半導體層的一第一側壁；以及 一閘極結構，該閘極結構環繞該第一半導體堆疊與該第二半導體堆疊的各半導體層的一第二側壁、一頂面、以及一底面。
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