CN113764413A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113764413A
CN113764413A CN202110570493.2A CN202110570493A CN113764413A CN 113764413 A CN113764413 A CN 113764413A CN 202110570493 A CN202110570493 A CN 202110570493A CN 113764413 A CN113764413 A CN 113764413A
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semiconductor
dummy
stack
layer
gate
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杨智铨
徐国修
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开提供一种半导体装置以及半导体装置的制造方法。一种半导体装置的范例包含第一半导体堆叠以及第二半导体堆叠、虚设间隔物和栅极结构，这些堆叠位于基板上方，其中各第一半导体堆叠与第二半导体堆叠包含层叠的且相互分开的半导体层；虚设间隔物位于第一半导体堆叠以及第二半导体堆叠之间，其中虚设间隔物接触第一半导体堆叠与第二半导体堆叠的各半导体层的第一侧壁；栅极结构环绕第一半导体堆叠与第二半导体堆叠的各半导体层的第二侧壁、顶面以及底面。

Description

半导体装置
技术领域
本公开涉及半导体装置及其制造方法，且特别涉及具有鱼骨结构的半导体装置及其制造方法。
背景技术
集成电路(IC)产业经历了指数成长。引入了多栅极装置以提高装置性能。其中多栅极装置的一种实例为鳍式场效晶体管(fin-like field effect transistor；FinFET)装置。多栅极装置的另一种实例为纳米片装置(亦称为纳米线装置、纳米环装置、栅极环绕装置、栅极全环(gate-all-around；GAA)装置；或多桥通道(multi-bridge channel)装置。多栅极装置与现有互补式金属氧化物半导体(CMOS)工艺相容，且能使晶体管的尺寸更大幅度地(aggressive)缩小。
缩小尺寸(例如，较小的间距和临界尺寸)一直是集成电路(IC)工艺中的趋势。与FinFET装置相比，虽然纳米片装置可提供较好的栅极控制效能，但纳米片装置的最小通道尺寸(minimum channel dimension)比FinFET装置的最小通道尺寸大许多。除此之外，更大幅度地(aggressively)缩小尺寸对半导体装置工艺引入了更高的复杂度，且为半导体装置带来了一些问题。例如，一些工艺的图案形成窗口可能会受相邻的纳米片堆叠之间有限的距离所拘束。因此，需要对纳米片装置进行改善，以降低装置尺寸以及减缓工艺的一些问题。
发明内容
本公开提供许多不同的实施例。具有鱼骨结构的半导体装置以及其制造方法在此公开。一种半导体装置的范例包含：第一半导体堆叠以及第二半导体堆叠、虚设间隔物、以及栅极结构。第一半导体堆叠以及第二半导体堆叠设置于基板上方，其中各第一半导体堆叠与第二半导体堆叠包含层叠的且相互分开的半导体层。虚设间隔物位于第一半导体堆叠以及第二半导体堆叠之间，其中虚设间隔物接触第一半导体堆叠与第二半导体堆叠的各半导体层的第一侧壁。栅极结构环绕第一半导体堆叠与第二半导体堆叠的各半导体层的第二侧壁、顶面以及底面。
另一范例的半导体装置包含：多个第一半导体堆叠、多个第二半导体堆叠、第一虚设间隔物、第二虚设间隔物、第一栅极结构、以及第二栅极结构。第一半导体堆叠位于基板的第一区之上，第二半导体堆叠位于基板的第二区之上，其中各第一导体堆叠与第二半导体堆叠包含层叠的且相互分开的半导体层。第一虚设间隔物位于第一半导体堆叠之间，第二虚设间隔物位于第二半导体堆叠之间，其中第一虚设间隔物与第一半导体堆叠的半导体层的侧壁接触，且第二虚设间隔物与第二半导体堆叠的半导体层的侧壁接触。第一栅极结构环绕第一半导体堆叠的各半导体层，以及第二栅极结构环绕第二半导体堆叠的各半导体层，其中第一栅极结构的顶部由第一虚设间隔物分开，且第二栅极结构的顶部在第二虚设间隔物的顶面上连续地延伸。
一种半导体装置的制造方法包含：在基板上形成第一半导体堆叠以及第二半导体堆叠，其中各第一半导体堆叠与该第二半导体堆叠包含多个第一半导体层与多个第二半导体层，第一半导体层与第二半导体层包含不同材料且为交叉堆叠。在第一半导体堆叠以及第二半导体堆叠之间形成虚设间隔物，其中虚设间隔物与第一半导体堆叠的第一半导体层与第二半导体层的第一侧壁接触，且虚设间隔物与第二半导体堆叠的第一半导体层与第二半导体层的第一侧壁接触。选择性地移除第一半导体堆叠与第二半导体堆叠的第二半导体层。形成金属栅极结构，金属栅极结构环绕第一半导体堆叠与第二半导体堆叠的第一半导体层的第二侧壁、顶面、以及底面。
附图说明
本公开的各项层面在以下的实施方式搭配附带的图示一同阅读会有最好的理解。需要强调的是，按照行业标准惯例，诸多特征并没有按比例绘制。事实上，诸多特征的尺寸可能为任意地增大或缩小以便做描述。
图1描绘依据本公开的一些实施例之用以制作一半导体装置的一实例方法的流程图
图2描绘六晶体管(six-transistor；6T)静态随机存取存储器(static random-access memory；SRAM)位元单元的一实例的一示意图。
图3描绘该六晶体管SRAM位元单元的实例的一俯视布置图。
图4描绘对应于本公开的一些实施例的最初的半导体装置实例的三维透视图。
图5、图6、图7、图8、图9A、图10A、图11A、图12A、图13A、图14A、图15A、图16A、图17A、图18A、以及图19A描绘对应于本公开的一些实施例在图1所示的方法在中间阶段的示意图和三维透视图且沿着A-A’线的该半导体装置的剖面图。
图9B、图10B、图11B、图12B、图13B、图14B、图15B、图16B、图17B、图18B、以及图19B描绘对应于本公开的一些实施例在图1所示的方法在中间阶段的示意图和三维透视图且沿着B-B’线的该半导体装置的剖面图。
附图标记说明如下：
100:方法
102-116:步骤
200:半导体装置(装置)
202:基板
202N:NFET区
202P:PFET区
204:隔离结构
210N、210P:堆叠
210A、210B:半导体层
210N、210P:堆叠
212、212N、212P:虚设间隔物
212’:虚设间隔层
214:沟槽
216:虚设介电层
220:虚设栅极结构
224:源极/漏极沟槽
230N:N型外延源极/漏极特征
230P:P型外延源极/漏极特征
232、260:层间介电层
234:栅极沟槽
236:光阻掩膜
240N、240P:栅极介电层
242N、242P:函数金属(WFM)
244:块材金属
246N、246P:金属栅极结构
250:源极/漏极接点
270:金属线/接点/导孔
D1,D2,D3:距离
T1,T2:厚度
A-A’：剖面线
B-B’：剖面线
具体实施方式
以下公开内容提供了用于实施所提供标的的不同特征的许多不同实施例或实例。以下描述了部件以及布置等的特定实例以简化本公开内容。当然，该等仅仅是实例，而并不旨在为限制性的。例如，在以下描述中在第二特征上方或之上形成第一特征可以包括第一特征和第二特征形成为直接接触的实施例，并且亦可以包括可以在第一特征与第二特征之间形成额外特征，使得第一特征和第二特征可以不直接接触的实施例。
另外，本公开可以在各种实例中重复参考数字及/或字母。该重复是为了简单和清楚的目的，并且本身并不代表所论述的各种实施例及/或配置之间的关系。除此之外，在本公开当中的一特征在另一特征之上、与之连接和/或耦合的形成可以包括其中特征形成为直接接触的实施方式，并且还可以包括其中可以夹设额外的特征的形成实施方式，以使得特征可能不直接接触。另外，在空间上相对的用语，例如“下部”，“上部”，“水平”，“垂直”，“上方”，“之上”，“下方”，“之下”，“上”，“下”，“顶部”、“底部”等及其派生词(例如，“水平的”，“向下的”，“向上的”等)皆用以使本公开更容易地描述一个特征与另一特征之间的关系。空间相对术语意在涵盖装备以及装备之特征的不同取向。更进一步，当一数字或一范围的数字是用“大约”、“近似”以及类似方式形容时，该字汇的目的是涵盖包括所述的数字的一定合理范围内的其他数字，例如在所述的数字+/-10％的范围或者对于所属领域的技术人员所能够理解的其他数值。举例来说，“大约5nm”这词汇涵盖从4.5纳米至5.5纳米的尺寸范围。
在纳米片装置中，单一装置的通道区可包含相互分离的多个层半导体材料(亦可称为通道半导体层)。在一些实例中，此装置的栅极设置在装置的半导体层上方、并排、或是之间。然而，相比于FinFET，纳米片装置的通道的最小尺寸(minimum dimension)大约为FinFET的鳍片厚度的三倍大。除此之外，由于半导体装置的大幅度(aggressive)缩小，用以分离相邻的栅极和外延源极/漏极(source/drain)结构的光刻工艺可能受限于最小相片尺寸(minimum photo size constraints)。
在本公开中，揭示一种具有鱼骨结构的纳米片装置，以缩小半导体装置(例如SRAM)的尺寸。虚设间隔物(dummy spacer)设置在邻近相同类型(N型或P型)的半导体堆叠之间。虚设间隔物可以将相邻的N型或P型金属栅极及/或相邻的N型或P型外延源极/漏极(S/D)分离，以减缓工艺当中的叠对偏移(overlay shifting)问题。更进一步，相同类型的半导体装置堆叠之间的距离将被缩小，且半导体装置(例如，SRAM的单元区域(cell area))的尺寸亦可有效地缩小。
图1描绘根据本公开的一些实施例的方法100的流程图，而此方法100为制作实例半导体装置(以下称为装置200)。方法100仅为一实例，而非意图在权利要求所明确地叙述的范围外限制本公开。为了执行该方法的不同的实施例，额外的操作可在方法100之前、之中、或之后执行，且部分描述的操作可被取代、移除、或移动。方法100在下面做描述，并且结合其他图式。其他图式描述装置200在方法100的中间步骤的一些三维视图和剖视图。特别而言，图2描绘实例6T SRAM位元单元的示意图。图3描绘包含单元区域201的实例6T SRAM的俯视布局图。图4是根据本公开的一些实施例的单元区域201的初始结构(在此之后称为装置200)的三维图。图5-18A描绘在图3与图4所示的方法100在中间步骤，沿着A-A’平面(亦即，切在X-Z平面的栅极)拍摄的装置200的剖面图。图9B-18B描绘在图3与图4所示的方法100在中间步骤，沿着B-B’平面(亦即，切在X-Z平面的源极/漏极)拍摄的装置200的剖面图。需了解的是，在形成虚设栅极结构之前(亦极，图9A与图9B之前)，沿着A-A’和B-B’平面的剖面图会是一样的。
如图2所描绘，6T SRAM单元通常包含两个P型上拉(pull-up；PU)晶体管、两个N型下拉(pull-down；PD)晶体管、以及两个N型通道栅(pass-gate；PG)晶体管。PD晶体管与PU晶体管形成交叉偶接的反向器。参考图3，6TSRAM布局包含装置200，而装置200包含相邻的N型FET(亦即NFET，在装置200的左手方)以及相邻的P型FET(亦即PFET，在装置200的右手方)。本公开揭示了装置200的结构与制作方法。虽然本公开以6T SRAM的单元区(亦即，装置200)为实例，可以了解装置200可为在集成电路(IC)工艺中制造的另一中间装置，或者集成电路的一部分，而该IC或IC的一部分可包含逻辑电路(例如，8晶体管SRAM、10晶体管SRAM、以及/或其他逻辑电路)、静态部件(如电阻、电容以及电感)，动态部件(如P型FET(PFET)、N型FET(NFET)、金属氧化物半导体场效晶体管(MOSFET)、互补式金属氧化物半导体(CMOS)晶体管、双极晶体管、高电压晶体管；高频率晶体管、以及/或其他存储单元)。装置200可为集成电路(IC)的一部分或核心区域(常称为逻辑区域)、周边区域(常称为输入/输出(I/O)区域)、虚设(dummy)区域、其他合适的区域、或者前述的组合。在一些实施例中，装置200可为IC芯片、系统上芯片(SoC)、或其中一部分。本公开不只限于任何数量的装置或装置区域，或是任何装置配置。
参考图1、图4与图5，在步骤102中，形成装置200的初步半导体结构。如图4与图5所描述，装置200包含基板202。在描述的实施例中，基板202为块材(bulk)硅基板。替代地或附加地，基板202包含另一单晶半导体，例如锗、化合物半导体(compound semiconductor)、合金半导体、或者前述的组合。或者，基板202可为绝缘层上半导体(semiconductor-on-insulator；SGOI)基板，例如绝缘层上硅(silicon-on-insulator；SOI)基板、绝缘层上硅锗(silicon germanium-on-insulator；SGOI)基板、或者绝缘层上锗(germanium-on-insulator；GOI)基板。基板202可为不同的掺杂物所掺杂，而形成不同的掺杂区。在所描述的实施例中，基板202包含NFET区202N，NFET区202N包含被P型掺杂物所掺杂的P型掺杂基板区(例如p井)，而P型掺杂物例如硼(如11B，BF2)、铟、其他P型掺杂物、或前述的组合。基板202亦包含PFET区202P，PFET区202P包含被N型掺杂物所掺杂的N型掺杂基板区(例如n井)，而N型掺杂物例如磷(如31P)、砷、其他N型掺杂物、或前述的组合。在一些实施例中，基板202包含P型掺杂物与N型掺杂物的组合所形成的掺杂区。电子注入工艺、扩散工艺、以及/或其他合适的掺杂工艺皆可用以形成不同的掺杂区。
装置200包含在基板202上形成的交替的半导体层，例如半导体层210A以及半导体层210B。半导体层210A包含第一半导体材料，而半导体层210B包含与第一半导体材料不同的第二半导体材料。前述半导体层210A与210B的不同的半导体材料具有不同的氧化速率以及/或蚀刻选择性。在一些实施例中，半导体层210A的第一半导体材料与基板202的材料相同。例如，半导体层210A包含硅(Si，如基板202)，以及半导体210B包含硅锗(silicongermanium；SiGe)。因此，交替的SiGe层/Si层/SiGe层/Si层/…从底至顶设置。在一些实施例中，最顶层的半导体层的材料可以与或是不与最底层的半导体层的材料相同。在所描述的实施例中，最顶层的半导体层为包含硅锗的半导体层210B。最顶层的半导体层210B可当作硬掩膜层，使得下层的半导体层210A与210B能在后续的蚀刻工艺受顶层的保护。在一些实施例中，半导体层210A的形成并没有执行有意的掺杂。在其他的实施例中，半导体层210A可被P型掺杂物或N型掺杂物所掺杂。半导体层210A与210B的数量取决于装置200的设计要求。例如，装置200可包含半导体层210A与210B的各1至10层。在一些实施例中，半导体层210A与210B的不同层在Z方向具有相同的厚度。在一些实施例中，半导体层210A与210B的不同层在Z方向具有不同的厚度。在一些实施例中，半导体层210A及/或半导体层210B由合适的外延工艺所形成。例如，包含硅锗与硅的半导体层交替地在基板202上形成，而形成方式为分子束外延(molecular beam epitaxy；MBE)工艺、化学气相沉积(chemical vapordeposition；CVD)工艺，例如金属有机化学气相沉积(metal organic CVD；MOCVD)工艺、以及/或其他合适的外延成长工艺。
在此之后，交替的半导体层210A与210B被图案化以形成堆叠210(亦可称为半导体堆叠)。在所描述的实施例中，堆叠210包含在NFET区202N形成的堆叠210N以及在PFET区202P形成的堆叠210P。在一些实施例中，为了形成图4与图5中鳍片状的堆叠210，不同光致抗蚀剂光刻工艺以及蚀刻工艺可被使用。例如，首先，在装置200上形成图案化的光阻掩膜。根据装置200的设计要求，图案化的光致抗蚀剂掩膜会覆盖鳍片的位置。其次，利用图案化的光致抗蚀剂掩膜执行一或多个蚀刻工艺以移除半导体层210A及210B的暴露部分。半导体层210A及210B的剩余部分形成鳍片形状堆叠210。在一些实施例中，基板202的顶部部分也遭移除。蚀刻工艺包含干蚀刻、湿蚀刻、其他合适的蚀刻工艺、或前述的组合。接下来利用任何妥当的方法(例如，电浆灰化(plasma ashing)工艺)移除光致抗蚀剂掩膜。
参考图4与图5，在NFET区202N中的相邻堆叠210N之间的距离为D1，在PFET区202P中的相邻堆叠210P之间的距离为D2，以及堆叠210N与210P之间的最近距离为D3。在一些实施例中，距离D1为大约8纳米至大约10纳米；距离D2为大约8纳米至大约10纳米；以及距离D3为大约39纳米至大约42纳米。在一些实施例中，距离D3为距离D1或D2的大约4倍至大约7倍大。距离D1、D2及/或D3不能太大，否则装置200的尺寸将无法有效地缩小。距离D1、D2以及/或D3不能太小，不然将很难在PFET区中的相邻堆叠210P或NFET区中的相邻堆叠210N之间的虚设间隔物212填满，而使在一些情形下的寄生电容增加。
装置200也包含在堆叠210之间的沟槽形成的隔离结构204，以分离与隔开装置200的有源区。在一些实施例中，一或多个介电材料，例如二氧化硅(silicon dioxide；SiO)及/或氮化硅(silicon nitride；SiN)，在基板202上沿着堆叠210的侧壁设置。介电材料亦可由CVD(例如，电浆增强化学气相沉积法(plasma enhanced CVD；PECVD))、物理气相沉积(physical vapor deposition；PVD)、热氧化、或其他技术。接者，介电材料被凹陷(recessed)/回蚀(例如，被蚀刻以及/或化学机械研磨(chemical mechanical polishing；CMP))以形成隔离结构204。
参考图1、图6与图7，在步骤104中，虚设间隔物212N与212P(两者皆称为虚设间隔物212)在NFET区202N的相邻堆叠210N之间形成，或者在PFET区202P的相邻堆叠210P之间形成。换句话说，虚设间隔物212在同类型(N型或P型)FET的堆叠210之间形成。参考图6，虚设间隔层212’在堆叠210与隔离结构204上设置。在一些实施例中，虚设间隔层包含基于氮化物的介电材料(例如，氮化硅(silicon nitride；SiN)、氮碳化硅(silicon carbonitride、SiCN)、其他基于氮化物的介电材料、或前述的组合)，或者是基于氧化物的介电材料(例如，氧化硅(silicon oxide；SiO)、碳氧化硅(silicon oxycarbide；SiOC)、其他基于氧化物的介电材料、或前述的组合)。在一些实施例中，虚设间隔层212’为沉积工艺所形成，例如原子层沉积(atomic layer deposition；ALD)、CVD、PVD、其他沉积工艺，或前述的组合)。沉积过程受控制，使得在NFET区202N中的堆叠210N之间的间隙与在PFET区202P中的堆叠210P之间的间隙被填补，而不同FET(意即相邻堆叠210N及210P)的相邻堆叠210之间的间隙没有填补，因而于其间形成沟槽214。参考图6，虚设间隔层212’的厚度T1本质上相等或大于堆叠210N之间的距离D1的一半(50％)及/或虚设间隔层212’的厚度T1本质上相等或大于堆叠210P之间的距离D2的一半(50％)。距离D1或D2本质上等于或小于两倍(200％)的厚度T1。在所描述距离D1或D2为大约8纳米至大约10纳米的实施例中，厚度T1为大约4纳米至大约6纳米，使得虚设间隔层的介电材料能填充堆叠210N之间的间隙或堆叠210P之间的间隙。
在此之后，参考图7，虚设间隔层212’的外层部分被移除，而保留了相邻堆叠210N之间或相邻堆叠210P之间的内层部分。在一些实施例中，虚设间隔层212’的外层部分由等向性蚀刻(isotropic etching)工艺(例如干蚀刻、湿蚀刻、或前述的组合)所移除。虚设间隔层212’所剩余的内层部分在堆叠210N之间形成虚设间隔物212N，以及在堆叠210P之间形成虚设间隔物212P。在一些实施例中，虚设栅极间隔物212的顶层部分可由蚀刻工艺的过程当中移除。虚设间隔物212的顶部表面位于半导体层210B的顶层之下，且位于半导体层210A的顶层之上，或实质上与半导体层210A的顶层共面。意即，蚀刻工艺可被控制，使得虚设栅极间隔物212的最顶部所遭移除的部分比半导体层210B(当作蚀刻工艺的硬掩膜)的最顶部的厚度还要少，而虚设间隔层212’的外层部分为实质上完全移除。如图7所描述，同类型FET中的堆叠210(例如相邻的堆叠210N或相邻的堆叠210P)为分别由虚设间隔物212N或212P所分开。接触堆叠210N的半导体层210A与210B之侧壁的虚设间隔物212N在X方向具有宽度D1，且接触堆叠210P的半导体层210A与210B的侧壁的虚设间隔物212P在X方向具有宽度D2。
参考图1与图8，在步骤106中，虚设介电层216在基板202上形成。在形成虚设介电层216之前，从堆叠210的顶部移除最顶层的半导体层210B。在一些实施例中，可用选择性的蚀刻工艺来移除最顶层的半导体层210B，因为最顶层的半导体层210B的材料提供不同于下层的半导体层210A的氧化速率以及/或蚀刻选择性。选择性的蚀刻工艺可以是干蚀刻、湿蚀刻、或前述的组合。
在此之后，虚设介电层216设置在堆叠210、虚设间隔物212、以及隔离结构204之上。在以下的所叙述的栅极取代工艺中，虚设介电层216可保护虚设间隔物以及或半导体层210A与210B。虚设介电层216的材料应提供虚设间隔物212的蚀刻选择性。例如，若是虚设间隔物212包含基于氮化物的介电材料，虚设介电层216包含基于氧化物的介电材料；或者是虚设间隔物212包含基于氧化物的介电材料，虚设介电层216包含基于氮化物的介电材料。在一些实施例中，介电材料可包含氮化硅(SiN)、氮碳化硅(SiCN)、氧化硅(SiO)、碳氧化硅(SiOC)、其他合适的介电材料、或前述的组合。在一些实施例中，虚设介电层216由ALD、CVD、PVD、其他沉积工艺、或前述的组合所形成。如图8所描述，虚设介电层216具有厚度T2。在一些实施例中，厚度T2为大约3纳米至大约10纳米，使得虚设介电层216的厚度够厚，足以保护虚设间隔物212以及堆叠210，且够薄，使得虚设介电层的形成与后续移除的时间及成本不会增加。
参考图1、图9A以及图9B，在步骤108中，虚设栅极结构220在堆叠210上形成。每个虚设栅极结构220作为后续形成金属栅极结构的一个预留空间。在一些实施例中，虚设栅极结构220沿着X方向延伸且横跨各个堆叠210。虚设栅极结构220覆盖堆叠210的通道区，堆叠210的通道区夹设在源极区以及漏极区(两者合称为源极/漏极区)之间。每个虚设栅极结构220可包含许多虚设栅极层，例如，在堆叠210上的界面层、在界面层上的虚设栅极电极(例如，包含多晶硅)、在虚设栅极电极上的一或多个硬掩膜层、或其他合适的层。虚设栅极结构220由沉积工艺、光刻工艺、蚀刻工艺、其他合适工艺、或前述的组合所形成。例如，不同的虚设栅极层沉积在堆叠210上。之后，执行光刻工艺以形成覆盖在堆叠210上的掩膜。在此之后，利用光刻掩膜蚀刻不同的虚设栅极层，以形成虚设栅极结构220。之后，光刻掩膜用任何适当的方法进行移除。在一些实施例中，包含介电材料的栅极间隔物(未图示)可沿着虚设栅极结构220的侧壁形成，并且前述的栅极间隔物被认为是虚设栅极结构220的一部分。
参考图1、图10A、图10B、图11A以及图11B，在步骤110中，外延源极/漏极特征230N与230P(两者称为外延源极/漏极特征230)在堆叠210的源极/漏极区上形成。参考图10A与图10B，首先，在源极/漏极区中的虚设介电层216以及堆叠210被蚀刻工艺移除。在一些实施例中，沿着虚设栅极结构220的侧壁移除虚设介电层216以及堆叠210以形成在图10B的源极/漏极沟槽224。在一些实施例中，在移除堆叠210之前先移除虚设介电层216。由于虚设介电层216以及虚设间隔物212的材料提供不同的蚀刻选择性，移除虚设介电层216时，虚设间隔物212实质上不受影响。接着进行源极/漏极蚀刻工艺以移除源极/漏极区上的堆叠210的部分。蚀刻工艺可以为干蚀刻(例如，反应离子蚀刻(reactive ion etching；RIE))、湿蚀刻、或前述的组合。蚀刻工艺的持续时间受控制，使得在源极/漏极区的各半导体层210A与210B的部分遭移除，意即，在源极/漏极沟槽224中的各半导体层210A与210B的侧壁为暴露的。在一些实施例中，内部间隔物(未图示)可在此后沿着半导体层210B的边缘部分形成。
之后，参考图11A及图11B，分别地在NFET区202N以及PFET区202P上方的源极/漏极沟槽224中外延成长源极/漏极特征230N与230P。外延源极/漏极特征可包含不同类型(N型或P型)源极/漏极特征的不同半导体材料。例如，在NFET区202N中，N型外延源极/漏极特征230N可包含例如硅以及/或碳的材料，其中包含硅的外延层或者包含硅-碳的外延层经由磷、砷、其他N型掺杂物、或前述的组合所掺杂(例如，形成Si:P外延层、Si:C外延层、或Si:C:P外延层)。在PFET区202P中，P型外延源极/漏极特征230P可包含例如硅以及/或锗的材料，其中包含硅-锗的外延层经由硼、碳、其他P型掺杂物、或前述的组合所掺杂(例如，形成Si:Ge:B外延层、或Si:Ge:C外延层)。在一些实施例中，源极/漏极特征230包含相互堆叠的多层结晶层。在一些实施例中，外延源极/漏极特征230包含可在通道区达到理想拉张应力以及/或压缩应力的材料以及/或掺杂物。在许多实施例中，外延源极/漏极特征230的不同外延层可包含相同或不同的半导体材料。
在源极/漏极沟槽224中实施外延工艺以长出源极/漏极特征230。外延工艺包含CVD沉积(例如，气相外延(vapor-phase epitaxy；VPE)、超高真空CVD(ultra-high vacuumCVD；UHV-VCD)、LPCVD、以及/或PECVD)、分子束外延(molecular beam epitaxy)、其他合适的选择性外延成长(SEG)工艺、或前述的组合。参考图11B，基于虚设间隔物212，同类型FET的相邻的源极/漏极特征230，意即NFET区202N中的相邻N型源极/漏极特征或PFET区202P中的相邻P型源极/漏极特征，在X方向并没有结合在一起。意即，虚设间隔物212将同类型FET的相邻源极/漏极特征230隔开。
在现有的纳米片半导体装置中，为了隔开相邻同类型的源极/漏极特征，半导体堆叠需要特定的距离。然而，在本公开中，同类型源极/漏极特征由虚设间隔物隔开。因此，相同半导体堆叠之间的距离缩短至距离D1或D2，意即，虚设间隔物212N或212P的宽度。在一些实施例中，本公开的同类型的半导体堆叠之间的距离可缩小为现有纳米片半导体装置的的同类型的半导体堆叠之间的距离大约20％至大约40％。因此，装置尺寸更大幅度地(aggressively)缩小了。此外，同类型源极/漏极特征之间的虚设间隔物可用来隔开源极/漏极接点(参照图18B与图19B)，因此形成源极/漏极接点时可缓解叠对偏移问题。
在此之后，参考图1、12A-17A、以及12B-17B，在步骤112中，执行栅极取代工艺将虚设栅极结构220取代成金属栅极结构244。参考图12A与图12B，在源极/漏极区中的在外延源极/漏极特征230、虚设间隔物212、以及隔离结构204上方形成层间介电(interlayerdielectric；ILD)层232。在一些实施例中，层间介电层232包含有别于虚设间隔物212的介电材料。在一些实施例中，层间介电质层232包含低介电系数(low-k)(K<3.9)介电材料，例如，四乙氧基硅烷(tetraethylorthosilicate；TEOS)氧化物、未掺杂的硅酸盐(silicate)玻璃、或掺杂过的氧化硅例如硼磷硅玻璃(borophosphosilicate glass；BPSG)、氟硅玻璃(FSG)、磷硅酸盐玻璃(phosphosilicate glass；PSG)、硼掺杂硅玻璃(boron dopedsilicon glass；BSG)、其他合适的介电材料、或前述的组合。层间介电层232可由沉积工艺如CVD、流动式CVD(flowable CVD；FCVD)、旋涂式玻璃(spin-on-glass；SOG)、其他合适的方法、或前述的组合。在此之后，可执行平坦化工艺(例如，CMP)以移除装置200的顶部(例如，层间介电层232以及虚设栅极结构220的硬掩膜层的顶部)以暴露虚设栅极电极。参考图12B，剩余的层间介电层232覆盖在源极/漏极区中的虚设间隔物212，使得在源极/漏极区的虚设间隔物212在后续的虚设间隔物回蚀工艺中受保护。
参考图13A与图13B，移除虚设栅极结构220以形成栅极沟槽234，并暴露堆叠210的通道区。在一些实施例中，移除虚设栅极结构220包含一或多道蚀刻工艺，例如湿蚀刻、干蚀刻、或前述的组合。背向虚设间隔物212的半导体层210A与210B的侧壁在栅极沟槽234为暴露状态。
在此之后，参考图14A与图14B，半导体层210B从栅极沟槽234选择性地移除。基于半导体层210A的材料(例如，SiGe)以及半导体层210B的材料(例如，硅)的不同的氧化速率以及/或蚀刻选择性，只有半导体层210B遭移除，而半导体层210A实质上维持不变。在一些实施例中，半导体层210B的选择性移除可包含氧化工艺，接着选择性蚀刻工艺。例如，先选择性氧化半导体层210B以包含硅锗氧化物(SiGeOx)材料。接着，执行选择性蚀刻工艺以利用合适的蚀刻剂例如氢氧化铵(ammonium hydroxide；NH4OH)或氟化氢(hydro fluoride；HF)以移除硅锗氧化物。在一些实施例中，半导体层210A在选择性蚀刻工艺中仅些微地蚀刻或不蚀刻。经此，半导体层210A在通道区为悬空且沿着方向(Z方向)堆叠，该方向实质上与基板202(X-Y平面)的顶面垂直。悬空的半导体层210A亦称为通道半导体层。参考图14A，同类型FET的半导体层210A以及在半导体层210A之间的虚设间隔物212在X-Z平面形成鱼骨结构。意即，堆叠210N的半导体层210A以及虚设间隔物212N在NFET区202N形成鱼骨结构，以及堆叠210P的半导体层210A以及虚设间隔物212P在PFET区202P形成鱼骨结构。半导体层210A的侧壁接触虚设间隔物212N或212P，而半导体层210A的其他侧(包含顶面、底面以及另外一侧壁)在栅极沟槽234中暴露。
参考图3、15A、15B，沿着A-A’线上，装置200的栅极结构在NFET区为不连接的，而在PFET区为连续的，并且在通道区的虚设间隔物212P的顶层部分会被回蚀(意即，虚设间隔物回蚀)。例如，可形成光阻掩膜236以覆盖NFET区202N。在堆叠210P(在通道区)之间的虚设间隔物212P的顶层部分会被蚀刻工艺(例如湿蚀刻、干蚀刻、或前述的组合)所移除。由于层间介电层232的保护，外延源极/漏极特征230P(在源极/漏极区)之间的虚设间隔物212P不受影响。如图15A、15B所描述，堆叠210P的顶面实质上与半导体层210A的顶部的顶面共面。如所描述的实施例中，通道区的虚设间隔物212P的顶面在源极/漏极区的虚设间隔物212P的顶面之下，而通道区的虚设间隔物212N的顶面实质上与源极/漏极区的虚设间隔物212N的顶面共面。
在此之后，参考图16A、16B、17A、17B，在堆叠210的通道区形成金属栅极结构246N与246P(两者称为金属栅极结构246)。金属栅极结构246环绕着各悬空半导体层210A的暴露的侧边。在一些实施例中，各金属栅极结构246N与246P包含栅极介电层、金属栅极电极、以及其他合适的层。参考图16A与16B，沉积栅极介电层240N与240P(两者称为栅极介电层240)以环绕栅极沟槽234中的半导体层210A的暴露的侧边。具体而言，暴露的侧边包含半导体层210A的背向虚设间隔物212的侧壁、顶面、以及底面。在一些实施例中，栅极介电层240包含高介电系数(high-k)(K>3.9)介电材料，例如，二氧化铪(HfO2)、硅酸铪(HfSiO)、氮氧化硅铪(HfSiON)、镧酸铪(HfLaO)、钽酸铪(HfTaO)、钛酸铪(HfTiO)、锆酸铪(HfZrO)、铪铝氧化物(HfAlOx)、氧化锆(ZrO)、二氧化锆(ZrO2)、硅酸锆(ZrSiO2)、一氧化铝(AlO)、硅酸铝(AlSiO)、氧化铝(Al2O3)、氧化钛(TiO)、二氧化钛(TiO2)、氧化镧(LaO)、LaSiO、三氧化二钽(Ta2O3)、五氧化二钽(Ta2O5)、氧化钇(Y2O3)、钛酸锶(SrTiO3)、锆酸钡(BaZrO)、钛酸钡(BaTiO3；BTO)、钛酸锶钡((Ba,Sr)TiO3；BST)、氮化硅(Si3N4)、二氧化铪-氧化铝(hafniumdioxide-alumina；HfO2-Al2O3)合金、其他合适的high-k介电材料、或前述的组合。栅极介电层240可由CVD、PVD、ALD、以及/或其他合适的方法沉积。参考图16A，栅极介电层240N的顶面在虚设间隔物212N的顶面之下，以及栅极介电层240P的顶面在虚设间隔物212P的顶面之上。意即，栅极介电层240N的顶层部分被虚设间隔物212N隔开，以及栅极介电层240P的顶层部分持续性地在虚设间隔物212P的顶面上延伸。
参考图17A与17B，在栅极介电层240N与240P上形成栅极电极。各栅极电极包含一个或多个功函数金属(work function metal；WFM)层以及块材金属。WFM层被配置以调适晶体管的相应的功函数以达到理想的临界电压Vt。并且块材金属被配置以作为函数栅极结构的主要导电部分。参考图17A，功函数金属(WFM)242N与WFM 242P(两者称为WFM 242)各别在栅极介电层240N与240P上形成。在一些实施例中，WFM层的材料可包含铝化钛(TiAl)、碳化铝钛(TiAlC)、碳化铝钽(TaAlC)、氮化铝钛(TiAlN)、氮化钛(TiN)、钛硅氮化物(TSN)、氮化钽(TaN)、氮化碳钨(WCN)、钼(Mo)、其他材料、或前述的组合。WFM 240可由任何合适的方法形成，例如CVD、ALD、PVD、电镀(plating)、化学氧化、热氧化、其他合适的方法、或前述的组合。如图17A所描述，WFM 240环绕半导体层210A所暴露的侧边。WFM 240N的顶面为虚设间隔物212N的顶面之下，而WFM 240P的顶面为虚设间隔物212P的顶面之上。意即，WFM 242N的顶部为虚设间隔物212N所分开，而WFM240P的顶部持续性地在虚设间隔物212P的顶面上延伸。
在此之后，块材金属244(例如包含铝、钨、铜、或前述的组合)在WFM242的上方的栅极沟槽234中形成。在一些实施例中，块材金属244由任何合适的方法形成，例如CVD、ALD、PVD、电镀、化学氧化、热氧化、其他合适的方法、或前述的组合。在所描述的实施例中，栅极介电层240N、WFM 242N、以及块材金属244形成金属栅极结构246N，以及栅极介电层240P、WFM 242P、以及块材金属244形成金属栅极结构246P。接着执行平坦化工艺(例如CMP)以移除多于块材金属材料，使得虚设间隔物212N的顶面为暴露的。由此，金属栅极结构246N的顶部由虚设间隔物212N所分开，而金属栅极结构246P的顶部持续性地在虚设间隔物212P上延伸。参考图17B，层间介电层232的顶部亦由平坦化工艺移除，且在源极/漏极区的虚设间隔物212N与212P的顶面亦为暴露的。
请参考图1、18A以及18B，在步骤114中，在外延源极/漏极特征230上形成源极/漏极接点250。在一些实施例中，源极/漏极接点250包含导电材料，例如铝、钨、铜、或前述的组合。源极/漏极接点250可由许多工艺，包含光刻工艺、蚀刻工艺、以及/或沉积工艺所形成。例如，形成光阻掩膜以暴露源极/漏极接点位置上的层间介电层232的部分。接着，执行蚀刻工艺以移除层间介电层232的暴露部分。由于层间介电层232的材料有别于虚设间隔物212，在蚀刻工艺中虚设间隔物212实质上不受影响。接下来，形成源极/漏极接点250的导电材料以取代层间介电层232的移除部分。虚设间隔物212系用以分开源极/漏极接点250。
请参考图1、19A以及19B，在步骤116中，进一步执行工艺以完成装置200的工艺。例如，在装置200上形成其他多层相互连接特征(例如金属线/接点/导孔270、以及层间介电层260以及/或蚀刻停止层，相互连接特征被配置以连接许多特征以便形成包含不同半导体装置的功能电路。
与现有的纳米片半导体装置相比，现有的纳米片半导体装置并没有用以隔开同类型FET的虚设间隔物，而本公开的半导体装置具有较小的尺寸，因为虚设间隔物能分开以及缩小同类型半导体堆叠之间的距离。进一步而言，对应于半导体装置的设计需求，虚设间隔物亦可以有效地分开同类型的外延源极/漏极特征，且可用以分开金属栅极结构。因此，可减缓光刻工艺中的迭对偏移问题同时能有效地缩小装置尺寸。
虽然不意图为限制性，但本公开的一或多个实施例对半导体装置以及半导体装置的形成工艺提供许多优点。例如，本公开的实施例提供的半导体装置具有在同类型FET的通道半导体层之间形成的虚设间隔物。通道半导体层与虚设间隔物形成鱼骨结构，以缩小装置尺寸，分隔外延源极/漏极特征及/或金属栅极结构，以及减缓工艺当中的叠对偏移问题。
本公开提供许多不同的实施例。具有鱼骨结构的半导体装置以及其制造方法在此公开。一种半导体装置的范例包含：第一半导体堆叠以及第二半导体堆叠、虚设间隔物、以及栅极结构。第一半导体堆叠以及第二半导体堆叠设置于基板上方，其中各第一半导体堆叠与第二半导体堆叠包含层叠的且相互分开的半导体层。虚设间隔物位于第一半导体堆叠以及第二半导体堆叠之间，其中虚设间隔物接触第一半导体堆叠与第二半导体堆叠的各半导体层的第一侧壁。栅极结构环绕第一半导体堆叠与第二半导体堆叠的各半导体层的第二侧壁、顶面、以及底面。
在一些实施例中，半导体装置的范例进一步包含：多个外延源极/漏极特征，接触虚设间隔物的侧壁。在一些实施例中，半导体装置的范例进一步包含多个源极/漏极接点，位于外延源极/漏极特征之上且接触虚设间隔物的侧壁。在一些实施例中，半导体装置的范例进一步包含隔离结构，隔开半导体装置的多个有源区，并且接触虚设间隔物的底面。在一些实施例中，虚设间隔物的顶面位于第一半导体堆叠与第二半导体堆叠的最顶层的半导体层的顶面之上，以及虚设间隔物将栅极结构分开，栅极结构包含栅极介电层以及在栅极介电层上的栅极电极。在一些实施例中，栅极结构包含栅极介电层以及在栅极介电层上的栅极电极，栅极介电层与栅极电极在虚设间隔物的顶面上连续地延伸。在一些实施例中，虚设间隔物的宽度为大约8纳米至大约10纳米。
另一范例半导体装置包含：多个第一半导体堆叠、多个第二半导体堆叠、第一虚设间隔物、第二虚设间隔物、第一栅极结构、以及第二栅极结构。第一半导体堆叠位于基板的第一区之上，第二半导体堆叠位于基板的第二区之上，其中各第一导体堆叠与第二半导体堆叠包含层叠的且相互分开的半导体层。第一虚设间隔物位于第一半导体堆叠之间，第二虚设间隔物位于第二半导体堆叠之间，其中第一虚设间隔物与第一半导体堆叠的半导体层的侧壁接触，且第二虚设间隔物与第二半导体堆叠的半导体层的侧壁接触。第一栅极结构环绕第一半导体堆叠的各半导体层，以及第二栅极结构环绕第二半导体堆叠的各半导体层，其中第一栅极结构的顶部由第一虚设间隔物分开，且第二栅极结构的顶部在第二虚设间隔物的顶面上连续地延伸。
在一些实施例中，在通道区中的第二虚设间隔物的顶面位于在源极/漏极区中的第二虚设间隔物的顶面之下。在一些实施例中，第一半导体堆叠与第二半导体堆叠之间的最短距离为第一虚设间隔物的宽度或第二虚设间隔物的宽度的大约4倍至大约7倍大。
一种半导体装置的制造方法包含：在基板上形成第一半导体堆叠以及第二半导体堆叠，其中各第一半导体堆叠与该第二半导体堆叠包含多个第一半导体层与多个第二半导体层，第一半导体层与第二半导体层包含不同材料且为交叉堆叠。在第一半导体堆叠以及第二半导体堆叠之间形成虚设间隔物，其中虚设间隔物与第一半导体堆叠的第一半导体层与第二半导体层的第一侧壁接触，且虚设间隔物与第二半导体堆叠的第一半导体层与第二半导体层的第一侧壁接触。选择性地移除第一半导体堆叠与第二半导体堆叠的第二半导体层。形成金属栅极结构，金属栅极结构环绕第一半导体堆叠与第二半导体堆叠的第一半导体层的第二侧壁、顶面、以及底面。
在一些实施例中，范例的制造方法进一步包含：在第一半导体堆叠与第二半导体堆叠之上沉积虚设间隔物层，虚设间隔物层的部分填满第一半导体堆叠与第二半导体堆叠之间的空间。等向性地移除(isotropically remove)第一半导体堆叠与第二半导体堆叠外面的虚设间隔物层，且保留填满第一半导体堆叠与第二半导体堆叠之间的空间的虚设间隔物层的部分以形成该虚设间隔物，其中虚设间隔物的顶面位于第一半导体堆叠与第二半导体堆叠的最顶层的第一半导体层的顶面之上。在一些实施例中，制造方法进一步包含：在第一半导体堆叠、第二半导体堆叠以及虚设间隔物之上沉积虚设介电层。在一些实施例中，制造方法进一步包含：在虚设间隔物、虚设介电层、第一半导体堆叠与第二半导体堆叠之上沉积虚设栅极结构。在一些实施例中，选择性地移除第二半导体层包含：移除虚设栅极结构以形成一栅极沟槽，其中第一半导体层与第二半导体层的第二侧壁在栅极沟槽中暴露；选择性地从栅极沟槽移除第二半导体层，使得各第一半导体层的第二侧壁、顶面、以及底面在栅极沟槽暴露。在一些实施例中，其中形成金属栅极结构包含：在各第一半导体层的第二侧壁、顶面、以及底面的周围沉积栅极介电层；在栅极介电层上沉积功函数金属；以及在功函数金属上形成块材金属。在一些实施例中，制造方法进一步包含：在形成金属栅极结构之前移除在通道区的虚设间隔物的顶部，使得虚设间隔物的顶面为实质上与第一半导体层的顶面共面。
在一些实施例中，制造方法进一步包含：移除在第一半导体堆叠与第二半导体堆叠的多个源极/漏极区的第一半导体层与第二半导体层，以形成源极/漏极沟槽；以及在源极/漏极沟槽中外延成长多个源极/漏极特征，其中源极/漏极特征由虚设间隔物分开。在一些实施例中，制造方法进一步包含：在源极/漏极区的虚设间隔物以及源极/漏极特征之上，形成一层间介电质层。在一些实施例中，制造方法进一步包含：形成多个源极/漏极接点，接触在源极/漏极区的虚设间隔物的侧壁。
前述内容概述了几个实施例的特征使得本领域技术人员可更容易了解本公开的各面向。本领域技术人员应该理解，他们可以容易地将公开用作设计或修改其他工艺和结构的基础，以实现与本文介绍的实施例相同的目的和/或实现相同的优点。本领域技术人员还应该认知到，等效的构造不脱离本公开的精神和范围，并且在不脱离本公开的精神和范围的情况下，它们可以进行各种改变，替换和变更。

Claims (1)

1.一种半导体装置，其特征在于，包含：
一第一半导体堆叠以及一第二半导体堆叠，设置于一基板上方，其中各该第一半导体堆叠与该第二半导体堆叠包含层叠的且相互分开的半导体层；
一虚设间隔物，位于该第一半导体堆叠以及该第二半导体堆叠之间，其中该虚设间隔物接触该第一半导体堆叠与该第二半导体堆叠的各半导体层的一第一侧壁；以及
一栅极结构，该栅极结构环绕该第一半导体堆叠与该第二半导体堆叠的各半导体层的一第二侧壁、一顶面以及一底面。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4199113A1 (en) * 2021-12-20 2023-06-21 IMEC vzw A method for forming a semiconductor device structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11329168B2 (en) * 2020-07-31 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with fish bone structure and methods of forming the same
US11908910B2 (en) * 2020-10-27 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having embedded conductive line and method of fabricating thereof

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199502B2 (en) 2014-08-15 2019-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of S/D contact and method of making same
US9818872B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9754840B2 (en) 2015-11-16 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Horizontal gate-all-around device having wrapped-around source and drain
US10032627B2 (en) 2015-11-16 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming stacked nanowire transistors
US9899387B2 (en) 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9887269B2 (en) 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9899269B2 (en) 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
US9899398B1 (en) 2016-07-26 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory device having nanocrystal floating gate and method of fabricating same
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US10475902B2 (en) 2017-05-26 2019-11-12 Taiwan Semiconductor Manufacturing Co. Ltd. Spacers for nanowire-based integrated circuit device and method of fabricating same
US10522546B2 (en) * 2018-04-20 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd FinFET devices with dummy fins having multiple dielectric layers
US11101348B2 (en) * 2018-07-25 2021-08-24 Globalfoundries U.S. Inc. Nanosheet field effect transistor with spacers between sheets
US10825918B2 (en) * 2019-01-29 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US12094781B2 (en) * 2019-09-13 2024-09-17 Hitachi High-Tech Corporation Manufacturing method of three-dimensional semiconductor device
US11139379B2 (en) * 2020-01-16 2021-10-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for forming the same
US11329168B2 (en) * 2020-07-31 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with fish bone structure and methods of forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4199113A1 (en) * 2021-12-20 2023-06-21 IMEC vzw A method for forming a semiconductor device structure

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