JP6678506B2 - 半導体パッケージ及び半導体パッケージの製造方法 - Google Patents

半導体パッケージ及び半導体パッケージの製造方法 Download PDF

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JP6678506B2
JP6678506B2 JP2016090189A JP2016090189A JP6678506B2 JP 6678506 B2 JP6678506 B2 JP 6678506B2 JP 2016090189 A JP2016090189 A JP 2016090189A JP 2016090189 A JP2016090189 A JP 2016090189A JP 6678506 B2 JP6678506 B2 JP 6678506B2
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semiconductor device
insulating layer
resin insulating
opening
recess
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JP2017199823A (ja
JP2017199823A5 (enExample
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靖之 竹原
靖之 竹原
一彦 北野
一彦 北野
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株式会社アムコー・テクノロジー・ジャパン
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Priority to JP2016090189A priority Critical patent/JP6678506B2/ja
Priority to TW110137066A priority patent/TWI784738B/zh
Priority to TW106107950A priority patent/TWI745359B/zh
Priority to US15/472,387 priority patent/US10553456B2/en
Priority to CN201710227962.4A priority patent/CN107424980B/zh
Priority to CN202210347036.1A priority patent/CN114823629A/zh
Priority to KR1020170047733A priority patent/KR20170123238A/ko
Publication of JP2017199823A publication Critical patent/JP2017199823A/ja
Publication of JP2017199823A5 publication Critical patent/JP2017199823A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
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    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
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    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
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    • H10W70/68—Shapes or dispositions thereof
    • H10W70/6875—Shapes or dispositions thereof being on a metallic substrate, e.g. insulated metal substrates [IMS]
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    • H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
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    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/134—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being in grooves in the semiconductor body
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    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H10W74/473—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins containing a filler
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    • H10W70/24—Conductive package substrates serving as an interconnection, e.g. metal plates characterised by materials
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    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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JP2016090189A 2016-04-28 2016-04-28 半導体パッケージ及び半導体パッケージの製造方法 Active JP6678506B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2016090189A JP6678506B2 (ja) 2016-04-28 2016-04-28 半導体パッケージ及び半導体パッケージの製造方法
TW110137066A TWI784738B (zh) 2016-04-28 2017-03-10 半導體封裝件及半導體封裝件之製造方法
TW106107950A TWI745359B (zh) 2016-04-28 2017-03-10 半導體封裝件及半導體封裝件之製造方法
US15/472,387 US10553456B2 (en) 2016-04-28 2017-03-29 Semiconductor package and manufacturing method of semiconductor package
CN201710227962.4A CN107424980B (zh) 2016-04-28 2017-04-10 半导体封装件及半导体封装件的制造方法
CN202210347036.1A CN114823629A (zh) 2016-04-28 2017-04-10 半导体封装件及半导体封装件的制造方法
KR1020170047733A KR20170123238A (ko) 2016-04-28 2017-04-13 반도체 패키지 및 반도체 패키지의 제조 방법

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JP2016090189A JP6678506B2 (ja) 2016-04-28 2016-04-28 半導体パッケージ及び半導体パッケージの製造方法

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JP2017199823A JP2017199823A (ja) 2017-11-02
JP2017199823A5 JP2017199823A5 (enExample) 2018-12-27
JP6678506B2 true JP6678506B2 (ja) 2020-04-08

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US (1) US10553456B2 (enExample)
JP (1) JP6678506B2 (enExample)
KR (1) KR20170123238A (enExample)
CN (2) CN107424980B (enExample)
TW (2) TWI745359B (enExample)

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JP6691835B2 (ja) * 2016-06-17 2020-05-13 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージの製造方法
KR102138012B1 (ko) * 2018-08-28 2020-07-27 삼성전자주식회사 팬-아웃 반도체 패키지
CN111415908B (zh) 2019-01-07 2022-02-22 台达电子企业管理（上海）有限公司 电源模块、芯片嵌入式封装模块及制备方法
WO2021111517A1 (ja) * 2019-12-03 2021-06-10 太陽誘電株式会社 部品モジュールおよびその製造方法
US12266581B2 (en) * 2020-10-30 2025-04-01 Intel Corporation Electronic substrates having heterogeneous dielectric layers
US20220238473A1 (en) * 2021-01-25 2022-07-28 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device

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JPS62163962A (ja) 1986-01-14 1987-07-20 Nec Corp 超音波顕微鏡
JPS62163962U (enExample) * 1986-04-08 1987-10-17
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TW202207380A (zh) 2022-02-16
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US20170316996A1 (en) 2017-11-02
TWI784738B (zh) 2022-11-21
TW201803036A (zh) 2018-01-16
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CN107424980A (zh) 2017-12-01
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