JP6604833B2 - プラズマエッチング方法 - Google Patents

プラズマエッチング方法 Download PDF

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Publication number
JP6604833B2
JP6604833B2 JP2015236624A JP2015236624A JP6604833B2 JP 6604833 B2 JP6604833 B2 JP 6604833B2 JP 2015236624 A JP2015236624 A JP 2015236624A JP 2015236624 A JP2015236624 A JP 2015236624A JP 6604833 B2 JP6604833 B2 JP 6604833B2
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Prior art keywords
plasma
frequency power
film
gas
plasma etching
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Japanese (ja)
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JP2017103388A (ja
JP2017103388A5 (enExample
Inventor
航 ▲高▼山
翔 冨永
義樹 五十嵐
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to JP2015236624A priority Critical patent/JP6604833B2/ja
Priority to TW105138041A priority patent/TWI706460B/zh
Priority to US15/361,675 priority patent/US9966273B2/en
Priority to KR1020160160127A priority patent/KR102363783B1/ko
Priority to SG10201610044VA priority patent/SG10201610044VA/en
Priority to CN201611078504.0A priority patent/CN106992121B/zh
Publication of JP2017103388A publication Critical patent/JP2017103388A/ja
Priority to US15/949,185 priority patent/US10707090B2/en
Publication of JP2017103388A5 publication Critical patent/JP2017103388A5/ja
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    • H10P50/283—
    • H10P50/242—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00—Generating plasma; Handling plasma
    • H05H1/24—Generating plasma
    • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10P14/6514—
    • H10P50/267—
    • H10P50/73—
    • H10P95/90—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Electromagnetism (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Drying Of Semiconductors (AREA)
JP2015236624A 2015-12-03 2015-12-03 プラズマエッチング方法 Active JP6604833B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2015236624A JP6604833B2 (ja) 2015-12-03 2015-12-03 プラズマエッチング方法
TW105138041A TWI706460B (zh) 2015-12-03 2016-11-21 電漿蝕刻方法
US15/361,675 US9966273B2 (en) 2015-12-03 2016-11-28 Plasma etching method
KR1020160160127A KR102363783B1 (ko) 2015-12-03 2016-11-29 플라즈마 에칭 방법
SG10201610044VA SG10201610044VA (en) 2015-12-03 2016-11-30 Plasma etching method
CN201611078504.0A CN106992121B (zh) 2015-12-03 2016-11-30 等离子体蚀刻方法
US15/949,185 US10707090B2 (en) 2015-12-03 2018-04-10 Plasma etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015236624A JP6604833B2 (ja) 2015-12-03 2015-12-03 プラズマエッチング方法

Publications (3)

Publication Number Publication Date
JP2017103388A JP2017103388A (ja) 2017-06-08
JP2017103388A5 JP2017103388A5 (enExample) 2018-07-19
JP6604833B2 true JP6604833B2 (ja) 2019-11-13

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Family Applications (1)

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JP2015236624A Active JP6604833B2 (ja) 2015-12-03 2015-12-03 プラズマエッチング方法

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US (2) US9966273B2 (enExample)
JP (1) JP6604833B2 (enExample)
KR (1) KR102363783B1 (enExample)
CN (1) CN106992121B (enExample)
SG (1) SG10201610044VA (enExample)
TW (1) TWI706460B (enExample)

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JP7018801B2 (ja) 2018-03-29 2022-02-14 東京エレクトロン株式会社 プラズマ処理装置、及び被処理体の搬送方法
JP6920245B2 (ja) * 2018-04-23 2021-08-18 東京エレクトロン株式会社 温度制御方法
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JP7175239B2 (ja) * 2018-06-22 2022-11-18 東京エレクトロン株式会社 制御方法、プラズマ処理装置、プログラム及び記憶媒体
JP6778822B2 (ja) 2018-10-26 2020-11-04 株式会社日立ハイテク プラズマ処理方法
US11476145B2 (en) 2018-11-20 2022-10-18 Applied Materials, Inc. Automatic ESC bias compensation when using pulsed DC bias
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US11508554B2 (en) 2019-01-24 2022-11-22 Applied Materials, Inc. High voltage filter assembly
KR102904251B1 (ko) * 2019-02-18 2025-12-24 도쿄엘렉트론가부시키가이샤 에칭 방법
WO2020195559A1 (ja) * 2019-03-22 2020-10-01 セントラル硝子株式会社 ドライエッチング方法及び半導体デバイスの製造方法
US11361976B2 (en) * 2019-11-25 2022-06-14 Tokyo Electron Limited Substrate processing method and plasma processing apparatus
WO2021171458A1 (ja) 2020-02-27 2021-09-02 株式会社日立ハイテク プラズマ処理方法
US11087989B1 (en) 2020-06-18 2021-08-10 Applied Materials, Inc. Cryogenic atomic layer etch with noble gases
JP7595431B2 (ja) 2020-07-21 2024-12-06 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
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US11495470B1 (en) 2021-04-16 2022-11-08 Applied Materials, Inc. Method of enhancing etching selectivity using a pulsed plasma
US11791138B2 (en) 2021-05-12 2023-10-17 Applied Materials, Inc. Automatic electrostatic chuck bias compensation during plasma processing
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US12525441B2 (en) 2021-06-09 2026-01-13 Applied Materials, Inc. Plasma chamber and chamber component cleaning methods
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US12106938B2 (en) 2021-09-14 2024-10-01 Applied Materials, Inc. Distortion current mitigation in a radio frequency plasma processing chamber
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Also Published As

Publication number Publication date
KR102363783B1 (ko) 2022-02-15
US9966273B2 (en) 2018-05-08
US20170162399A1 (en) 2017-06-08
JP2017103388A (ja) 2017-06-08
US10707090B2 (en) 2020-07-07
TW201721739A (zh) 2017-06-16
SG10201610044VA (en) 2017-07-28
KR20170065449A (ko) 2017-06-13
TWI706460B (zh) 2020-10-01
CN106992121B (zh) 2020-10-09
CN106992121A (zh) 2017-07-28
US20180226264A1 (en) 2018-08-09

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