JP6478853B2 - 電子部品装置及びその製造方法 - Google Patents

電子部品装置及びその製造方法 Download PDF

Info

Publication number
JP6478853B2
JP6478853B2 JP2015140304A JP2015140304A JP6478853B2 JP 6478853 B2 JP6478853 B2 JP 6478853B2 JP 2015140304 A JP2015140304 A JP 2015140304A JP 2015140304 A JP2015140304 A JP 2015140304A JP 6478853 B2 JP6478853 B2 JP 6478853B2
Authority
JP
Japan
Prior art keywords
electronic component
semiconductor chip
alignment mark
underfill resin
resin material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015140304A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017022300A (ja
JP2017022300A5 (https=
Inventor
翔太 三木
翔太 三木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2015140304A priority Critical patent/JP6478853B2/ja
Priority to US15/206,422 priority patent/US9825006B2/en
Publication of JP2017022300A publication Critical patent/JP2017022300A/ja
Publication of JP2017022300A5 publication Critical patent/JP2017022300A5/ja
Application granted granted Critical
Publication of JP6478853B2 publication Critical patent/JP6478853B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/607—Located on parts of packages, e.g. on encapsulations or on package substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2015140304A 2015-07-14 2015-07-14 電子部品装置及びその製造方法 Active JP6478853B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015140304A JP6478853B2 (ja) 2015-07-14 2015-07-14 電子部品装置及びその製造方法
US15/206,422 US9825006B2 (en) 2015-07-14 2016-07-11 Electronic component device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015140304A JP6478853B2 (ja) 2015-07-14 2015-07-14 電子部品装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2017022300A JP2017022300A (ja) 2017-01-26
JP2017022300A5 JP2017022300A5 (https=) 2018-04-26
JP6478853B2 true JP6478853B2 (ja) 2019-03-06

Family

ID=57775892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015140304A Active JP6478853B2 (ja) 2015-07-14 2015-07-14 電子部品装置及びその製造方法

Country Status (2)

Country Link
US (1) US9825006B2 (https=)
JP (1) JP6478853B2 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6489965B2 (ja) * 2015-07-14 2019-03-27 新光電気工業株式会社 電子部品装置及びその製造方法
JP6871512B2 (ja) * 2017-04-11 2021-05-12 富士通株式会社 半導体装置及びその製造方法
JP2018182213A (ja) 2017-04-19 2018-11-15 富士通株式会社 半導体装置及び半導体装置の製造方法
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10714462B2 (en) * 2018-04-24 2020-07-14 Advanced Micro Devices, Inc. Multi-chip package with offset 3D structure
JP7236269B2 (ja) * 2018-12-26 2023-03-09 新光電気工業株式会社 配線基板、半導体装置、及び配線基板の製造方法
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
KR102741172B1 (ko) * 2019-12-06 2024-12-11 삼성전자주식회사 테스트 범프들을 포함하는 반도체 패키지
KR102848525B1 (ko) 2020-11-25 2025-08-22 에스케이하이닉스 주식회사 관통 전극을 포함하는 반도체 칩, 및 이를 포함하는 반도체 패키지
US20220230986A1 (en) * 2021-01-18 2022-07-21 Yibu Semiconductor Co., Ltd. Semiconductor Assembly Packaging Method, Semiconductor Assembly and Electronic Device
JP2023121355A (ja) * 2022-02-21 2023-08-31 キオクシア株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002184936A (ja) * 2000-12-11 2002-06-28 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2002222914A (ja) * 2001-01-26 2002-08-09 Sony Corp 半導体装置及びその製造方法
JP3668686B2 (ja) * 2001-01-30 2005-07-06 アルプス電気株式会社 チップ部品の実装構造
JP4074862B2 (ja) * 2004-03-24 2008-04-16 ローム株式会社 半導体装置の製造方法、半導体装置、および半導体チップ
US20110089438A1 (en) * 2009-10-19 2011-04-21 Zarlink Semiconductor Ab Opto-electrical assemblies and associated apparatus and methods
KR101852601B1 (ko) * 2011-05-31 2018-04-27 삼성전자주식회사 반도체 패키지 장치
JP2012256679A (ja) * 2011-06-08 2012-12-27 Elpida Memory Inc 半導体装置及びその製造方法
JP5357241B2 (ja) 2011-08-10 2013-12-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
JP2013138177A (ja) * 2011-11-28 2013-07-11 Elpida Memory Inc 半導体装置の製造方法
JP2013168503A (ja) * 2012-02-15 2013-08-29 Sumitomo Bakelite Co Ltd 半導体装置の製造方法
JP2013197387A (ja) * 2012-03-21 2013-09-30 Elpida Memory Inc 半導体装置
US9349663B2 (en) * 2012-06-29 2016-05-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package-on-package structure having polymer-based material for warpage control
US9627325B2 (en) * 2013-03-06 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package alignment structure and method of forming same
KR20160006702A (ko) * 2013-05-07 2016-01-19 피에스4 뤽스코 에스.에이.알.엘. 반도체 장치 및 반도체 장치의 제조 방법
JP2015005637A (ja) * 2013-06-21 2015-01-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
JP2015056563A (ja) * 2013-09-12 2015-03-23 株式会社東芝 半導体装置およびその製造方法
KR102107961B1 (ko) * 2013-11-14 2020-05-28 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
JP6242231B2 (ja) * 2014-02-12 2017-12-06 新光電気工業株式会社 半導体装置及びその製造方法
KR102245003B1 (ko) * 2014-06-27 2021-04-28 삼성전자주식회사 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법
JP6276151B2 (ja) * 2014-09-17 2018-02-07 東芝メモリ株式会社 半導体装置
JP6489965B2 (ja) * 2015-07-14 2019-03-27 新光電気工業株式会社 電子部品装置及びその製造方法

Also Published As

Publication number Publication date
US20170018534A1 (en) 2017-01-19
JP2017022300A (ja) 2017-01-26
US9825006B2 (en) 2017-11-21

Similar Documents

Publication Publication Date Title
JP6478853B2 (ja) 電子部品装置及びその製造方法
US12406934B2 (en) Semiconductor package
JP6489965B2 (ja) 電子部品装置及びその製造方法
US11476204B2 (en) Flip-chip packaging substrate and method for fabricating the same
TWI506738B (zh) 封裝結構及其製法
JP6816964B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
US9583367B2 (en) Methods and apparatus for bump-on-trace chip packaging
TWI548043B (zh) 封裝結構及其製法
CN103262236B (zh) 半导体元件中的无铅结构
JP6242231B2 (ja) 半導体装置及びその製造方法
TWI715970B (zh) 低翹曲扇出型封裝結構
TWI571185B (zh) 電子封裝件及其製法
US20100007015A1 (en) Integrated circuit device with improved underfill coverage
TW201325343A (zh) 用於嵌入式晶粒封裝的高精密度自我對準晶粒
TW201448139A (zh) 嵌埋式基板封裝構造及其製造方法
US20180337143A1 (en) Semiconductor chip, and fabrication and packaging methods thereof
TWI591739B (zh) 封裝堆疊結構之製法
TW201507098A (zh) 半導體裝置及其製造方法
TWI628773B (zh) 半導體結構、半導體元件及其形成方法
CN103378041A (zh) 迹线上凸块芯片封装的方法和装置
TW201725669A (zh) 封裝基板
JP6495130B2 (ja) 半導体装置及びその製造方法
TWI565008B (zh) 半導體元件封裝結構及其形成方法
JP2009266972A (ja) 積層型半導体モジュール及びその製造方法
TW201507097A (zh) 半導體晶片及具有半導體晶片之半導體裝置

Legal Events

Date Code Title Description
RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20180207

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20180215

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180315

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180315

TRDD Decision of grant or rejection written
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190117

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190122

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190205

R150 Certificate of patent or registration of utility model

Ref document number: 6478853

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150