TW201725669A - 封裝基板 - Google Patents

封裝基板 Download PDF

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Publication number
TW201725669A
TW201725669A TW105101273A TW105101273A TW201725669A TW 201725669 A TW201725669 A TW 201725669A TW 105101273 A TW105101273 A TW 105101273A TW 105101273 A TW105101273 A TW 105101273A TW 201725669 A TW201725669 A TW 201725669A
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Taiwan
Prior art keywords
conductive
layer
package
circuit component
package substrate
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TW105101273A
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English (en)
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TWI672768B (zh
Inventor
許詩濱
楊智貴
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恆勁科技股份有限公司
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Priority to TW105101273A priority Critical patent/TWI672768B/zh
Priority to US15/386,456 priority patent/US10062649B2/en
Publication of TW201725669A publication Critical patent/TW201725669A/zh
Application granted granted Critical
Publication of TWI672768B publication Critical patent/TWI672768B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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Abstract

本發明揭示一種封裝基板，其包括：一第一導電層，包含一第一導電區及一第二導電區；一封裝單元層，設置於該第一導電層上，並包含一第一電路元件、一第一導電柱、及一封膠材料，該第一電路元件具有一連接該第一導電區的第一連接端及一連接該第二導電區的第二連接端，且該第一導電柱連接該第一導電區；以及一第二導電層，設置於該封裝單元層上，並包含一連接該第一導電柱的第一金屬走線。

Description

封裝基板
本發明係關於一種封裝基板技術。
新一代的電子產品不僅追求輕薄短小，更朝多功能與高性能的方向發展，因此，積體電路(Integrated Circuit，簡稱IC)技術不斷地高密度化與微型化，以期在有限的晶片空間容納更多的電子元件，而其後端的封裝基板及其構裝技術亦隨之進展，以符合此新一代的電子產品趨勢。
傳統技術常以核心板(Core substrate)為基礎來構裝封裝基板，例如，第1A~1D圖為習知封裝基板在不同製程步驟的剖面示意圖。在電路元件14a、14b置入核心板11之前，習知技術會在核心板11的上下表面上先製作上層金屬線路12及下層金屬線路13，如第1A圖所示。接著在電路元件14a、14b的預定位置開設開口窗，並黏貼暫用載膜15於下層金屬線路13的下方，藉以將電路元件14a、14b置入核心板11的開口窗，如第1B圖所示。接著形成絕緣層16，將核心板11、上層金屬線路12、下層金屬線路13、及電路元件14a、14b全部包覆，並製作上層金屬線路12、下層金屬線路13、及電路元件14a、14b藉以向外連接的導通孔17，如第1C圖所示。最後形成填滿導通孔17的導電金屬層18，使得金屬線路12、下層金屬線路13、及電路元件14a、14b得以向外連接至外部電路。然而，開設上述開口窗於核心板11內需要昂貴的加工技術，製作上述導通孔17於絕緣層16內會有上下層布局圖對位(alignment)的問題，且可能會選用雷射開孔技術而致加工時間冗長。因此，有必要發展新的封裝基板技術，以解決上述問題。
為達成此目的，根據本發明的一方面，一實施例提供一種封裝基板，其包括：一第一導電層，包含一第一導電區及一第二導電區；一封裝單元層，設置於該第一導電層上，並包含一第一電路元件、一第一導電柱、及一封膠材料，該第一電路元件具有一連接該第一導電區的第一連接端及一連接該第二導電區的第二連接端，且該第一導電柱連接該第一導電區；以及一第二導電層，設置於該封裝單元層上，並包含一連接該第一導電柱的第一金屬走線。
在一實施例中，該第一電路元件為積體電路晶片或積層陶瓷電容器。
在一實施例中，該封膠材料充填於該封裝單元層內該第一電路元件及該第一導電柱之外的其餘部分。
在一實施例中，該封裝單元層進一步包含一第二導電柱，該第二導電層進一步包含一第二金屬走線，且該第二導電柱連接該第二導電區與該第二金屬走線。
在一實施例中，該封裝單元層進一步包含一第二電路元件，其具有一連接該第一導電區的第三連接端。
在一實施例中，該封裝單元層進一步包含一第二電路元件、一第二導電柱、及一第三導電柱，該第一導電層進一步包含一第三導電區，該第二電路元件具有一連接該第一導電區的第三連接端及一連接該第三導電區的第四連接端，該第二導電柱連接該第二導電區，且該第三導電柱連接該第三導電區。
在一實施例中，該封裝單元層進一步包含一連接單元，該第二導電層進一步包含一第二金屬走線，且該第一電路元件的第二連接端透過該連接單元連接該第二金屬走線。
在一實施例中，該封裝單元層進一步包含一第一連接單元、一第二連接單元、及一第三連接單元，該第二導電層進一步包含一第二金屬走線及一第三金屬走線，該第一電路元件的第二連接端透過該第一連接單元連接該第二金屬走線，該第一電路元件的 第一連接端透過該第二連接單元連接該第三金屬走線，且該第二電路元件的第三連接端透過該第三連接單元連接該第一金屬走線。
11‧‧‧核心板
12‧‧‧上層金屬線路
13‧‧‧下層金屬線路
14a、14b‧‧‧電路元件
15‧‧‧暫用載膜
16‧‧‧絕緣層
17‧‧‧導通孔
18‧‧‧導電金屬層
100、200‧‧‧封裝基板
120‧‧‧第一導電層
121‧‧‧第一導電區
122‧‧‧第二導電區
123‧‧‧第三導電區
130‧‧‧封裝單元層
131‧‧‧第一電路元件
131a、131b‧‧‧連接端
132‧‧‧第一導電柱
133‧‧‧封膠材料
134‧‧‧第二電路元件
134a、134b‧‧‧連接端
135‧‧‧第二導電柱
137‧‧‧第三導電柱
138‧‧‧第一連接單元
139‧‧‧第二連接單元
239‧‧‧第三連接單元
140‧‧‧第二導電層
141‧‧‧第一金屬走線
142‧‧‧第二金屬走線
143‧‧‧第三金屬走線
145‧‧‧保護層
150‧‧‧連接墊
第1A~1D圖為對應以核心板為基礎的封裝基板之不同製程步驟的剖面示意圖。
第2圖為根據本發明第一實施例的封裝基板之上視平面圖。
第3圖則為沿第2圖之直線AA’切割而得該封裝基板的結構剖面圖。
第4A~4E圖為對應本實施例封裝基板的各製程步驟之結構剖面圖。
第5圖為根據本發明第二實施例的封裝基板之結構剖面圖。
為對本發明之特徵、目的及功能有更進一步的認知與瞭解，茲配合圖式詳細說明本發明的實施例如後。在所有的說明書及圖示中，將採用相同的元件編號以指定相同或類似的元件。
在各個實施例的說明中，當一元素被描述是在另一元素之「上方/上」或「下方/下」，係指直接地或間接地在該另一元素之上或之下的情況，其可能包含設置於其間的其他元素；所謂的「直接地」係指其間並未設置其他中介元素。「上方/上」或「下方/下」等的描述係以圖式為基準進行說明，但亦包含其他可能的方向轉變。所謂的「第一」、「第二」、及「第三」係用以描述不同的元素，這些元素並不因為此類謂辭而受到限制。為了說明上的便利和明確，圖式中各元素的厚度或尺寸，係以誇張或省略或概略的方式表示，且各元素的尺寸並未完全為其實際的尺寸。
第2圖為根據本發明第一實施例的封裝基板100之上視平面圖，其為該封裝基板100的封裝單元層130之布局圖，而第3圖則為沿第2圖之直線AA’切割而得該封裝基板100的結構剖面圖。該封裝基板100包含：一第一導電層120、一封裝單元層130、 以及一第二導電層140。該第一導電層120包含至少一金屬走線或導電區，藉以形成該封裝基板100的下層電路，如圖所示，該第一導電層120包含第一導電區121、第二導電區122、及第三導電區123。該封裝單元層130設置於該第一導電層120上，並包含至少一電路元件及至少一導電柱。該至少一電路元件可以是積體電路晶片或是表面黏貼元件(Surface Mounted Device，簡稱SMD)，例如，積層陶瓷電容器(Multi-Layer Ceramic Capacitor，簡稱MLCC)，如圖所示，該封裝單元層130包含一第一電路元件131及一第二電路元件134。該至少一導電柱可以是金屬材質的柱狀物，例如，銅柱，其穿過該封裝單元層130，藉以連接該第一導電層120(該封裝基板100的下層電路)與該第二導電層140(該封裝基板100的上層電路)，如圖所示，該封裝單元層130包含一第一導電柱132及一第二導電柱135。該封膠材料133充填於該封裝單元層130內該等電路元件131、134及該等導電柱132、135之外的其餘部分，藉以將該等電路元件131、134及該等導電柱132、135封裝及固定於該封裝單元層130內。該第二導電層140設置於該封裝單元層130上，並包含至少一金屬走線或導電區，藉以形成該封裝基板100的上層電路，如圖所示，該第二導電層140包含第一金屬走線141及第二金屬走線142。該封膠材料133可由適合頂端鑄模(Top Molding)、壓縮鑄模(Compression Molding)、轉換鑄模(Transfer Molding)或注射鑄模(Injection Molding)等技術而選擇合適的絕緣封膠材料(Molding Compound)所組成，例如，酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、或矽基樹脂(Silicone-Based Resin)，藉以減小該封裝單元層130的厚度，並可有效防止該封裝基板100發生彎翹或變形。
在本實施例中，該等電路元件131、134藉由導電材質之連接墊(Pad)150而直接黏貼至該第一導電層120，製作上相當簡單而無上下層布局對位的問題，有助於降低封裝基板的製造成本。上述該連接墊150只需透過網板印刷或噴墨印製等簡單方式，即可配發於該第一導電層120上。此外，倘若該第一導電區121或該 第二導電區122作為連接電源或接地之用，則可設計成大面積的金屬層。如第2圖及第3圖所示，該第一電路元件131具有二個連接端：連接該第一導電區121的連接端131a，及連接該第二導電區122的連接端131b；該第二電路元件134亦具有二個連接端：連接該第一導電區121的連接端134a，及連接該第三導電區123的連接端134b。該等連接端131a、131b、134a、134b的組成材質為金屬，例如，銅(Cu)、錫(Sn)、鋁(Al)、錫銅(SnCu)合金、錫鉛(SnPb)合金、或錫銀銅(SnAgCu)合金，倘若該等連接端131a、131b、134a、134b設計為大尺寸，則可使得該等電路元件131、134以大接觸面積黏接於該第一導電層120上，有助於降低二者之間的電阻。
此外，相較於以第1A~1D圖為例的習知技術，該電路元件14a必須經過該導電金屬層18以及二個該導通孔17如此長的路徑才能連接到該封裝基板的上層金屬線路12；反觀本實施例，該第一電路元件131只需直接黏貼至該第一導電層120，就能連接到該封裝基板100的下層金屬線路。如此，有助於降低該第一電路元件131連接至外部電路之路徑及因而所致的電阻，且無元件對位(alignment)上的問題。
此外，該第一導電柱132用以連接該第一導電層120的第一導電區121與該第二導電層140的第一金屬走線141，該第二導電柱135用以連接該第一導電層120的第二導電區122與該第二導電層140的第二金屬走線142，該等導電柱132、135可以是任何適當的形狀(例如，圓形或矩形柱狀物)，亦可設計成具有大的截面積，且其可設置於該第一導電層120的該等導電區121、122、123上的任何位置，例如，倘若該第一導電柱132愈靠近該第一電路元件131，則該第一電路元件131連接至外部電路的路徑愈短，有助於降低其外接線路的路徑及因而所致的電阻。此外，該封裝單元層130可進一步包含一第三導電柱137，如第2圖所示，其連接該第三導電區123。
第4A~4E圖及第3圖為本實施例封裝基板100的各製程步驟 S310~S390所對應之結構剖面圖，並詳述如下。
首先，如第4A圖所示，提供一承載基板110，其上已製作有導線電路111及金屬導柱112。該承載基板110可以是金屬基板或是具有金屬層之玻璃纖維核心板(Core Substrate)，用以承載或支持其上的導電線路及電子元件；例如，如第2或3圖所示之該第一導電層120、該封裝單元層130、以及該第二導電層140。上述的金屬包含鐵(Fe)、鐵/鎳(Fe/Ni)、銅(Cu)、鋁(Al)及其組合或合金，但本發明不以此為限。該等導線電路111及該等金屬導柱112則用以將如第2或3圖所示之該第一導電層120連皆至外部電路。
接著，如第4B圖所示，形成一第一導電層120於該承載基板100上，並圖案化成該封裝基板100所預先設定的下層電路之金屬走線或導電區，例如，第一導電區121、第二導電區122。該第一導電層120可藉由金屬的電鍍(Electrolytic Plating)或蒸鍍(Evaporation)技術來製作，例如，銅、鋁、或鎳，而其導電走線的圖案化可藉由光微影蝕刻(Photolithography)技術來製作。
接著，如第4C圖所示，採用網板印刷或噴墨印製等手段，在該第一導電層120上形成導電材質之連接墊(Pad)150，並將第一電路元件131及第二電路元件134置於該連接墊150上，該等電路元件131、134的連接端131a、131b、134a分別對應該等連接墊150而黏貼至該第一導電層120。藉此，該第一電路元件131及該第二電路元件134可直接就能連接到該封裝基板100的下層金屬線路，例如，該導線電路111。
接著，如第4D圖所示，形成第一導電柱132及第二導電柱135於該第一導電層120上，用以連接該第一導電層120與該第二導電層140。該等導電柱132、135可藉由金屬的電鍍或蒸鍍技術來製作，而該該等導電柱132、135的圖案化可藉由光微影蝕刻技術來製作。
接著，如第4E圖所示，將封膠材料133形成於該第一導電層120上，使得該封膠材料133充填於該封裝單元層130內該等電路元件131、134及該等導電柱132、135之外的其餘部分，藉以將 該等電路元件131、134及封裝及固定於該封裝單元層130內。這可藉由該封膠材料133的頂端鑄模、壓縮鑄模、轉換鑄模、或注射鑄模等技術來製作；其中，該封膠材料133可以是酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、或矽基樹脂(Silicone-Based Resin)等絕緣材料所組成，但不以此為限。此外，可藉由研磨(Polishing)、磨削(Grinding)、噴砂、電漿或化學蝕刻方式，自上而下去除該封膠材料133的上半部，直到該等導電柱132、135的上端面露出，藉以形成該封裝單元層130；也就是該封裝單元層130位於該第一導電層120上，並且包含該等電路元件131、134及該等導電柱132、135。
接著，如第3圖所示，形成一第二導電層140於該封裝單元層130上，並圖案化成該封裝基板100所預先設定的上層電路之金屬走線或導電區，例如，第一金屬走線141、第二金屬走線142。該第二導電層140亦可藉由金屬的電鍍或蒸鍍技術來製作，例如，銅、鋁、或鎳，而其導電走線的圖案化可藉由光微影蝕刻技術來製作。一絕緣材質的保護層145可形成於該第二導電層140內該等金屬走線141、142之外的其餘部分，用以保護該封裝基板100免於受到來自外部環境或後續製程(例如，焊接)的可能傷害。至此，該承載基板110已完成其製程上的階段性任務，因此可將其移除。
第5圖為根據本發明第二實施例的封裝基板200之結構剖面圖。該封裝基板200包含：一第一導電層120、一封裝單元層130、以及一第二導電層140，其類似於上述第一實施例的該封裝基板100，且相同之處在此不再贅述。如第5圖所示，該封裝單元層130進一步包含一第一連接單元138，且該第一電路元件131的連接端131b透過該第一連接單元138而連接該第二金屬走線142。藉此，該第一電路元件131亦可透過其連接端131b而連接該封裝基板200的上層電路(例如，該第二導電層140)。
在另一實施例中，該封裝單元層130可進一步包含一第二連接單元139及一第三連接單元239，且該第二導電層140進一步包 含一第三金屬走線143，亦如第5圖所示，該第一電路元件131的連接端131b可透過該第一連接單元138而連接該第二金屬走線142，其另一連接端131a可透過該第二連接單元139而連接該第三金屬走線143，且該第二電路元件134的連接端134a則可透過該第三連接單元239而連接該第一金屬走線141。藉此，該等電路元件131、134亦可透過其連接端131a、131b、134a而連接該封裝基板200的上層電路(例如，該第二導電層140)。
唯以上所述者，僅為本發明之較佳實施例，當不能以之限制本發明的範圍。即大凡依本發明申請專利範圍所做之均等變化及修飾，仍將不失本發明之要義所在，亦不脫離本發明之精神和範圍，故都應視為本發明的進一步實施狀況。
100‧‧‧封裝基板
120‧‧‧第一導電層
121‧‧‧第一導電區
122‧‧‧第二導電區
130‧‧‧封裝單元層
131‧‧‧第一電路元件
131a、131b‧‧‧連接端
132‧‧‧第一導電柱
133‧‧‧封膠材料
134‧‧‧第二電路元件
134a‧‧‧連接端
135‧‧‧第二導電柱
140‧‧‧第二導電層
141‧‧‧第一金屬走線
142‧‧‧第二金屬走線
145‧‧‧保護層
150‧‧‧連接墊

Claims (8)

  1. 一種封裝基板，其包括：一第一導電層，包含一第一導電區及一第二導電區；一封裝單元層，設置於該第一導電層上，並包含一第一電路元件、一第一導電柱、及一封膠材料，該第一電路元件具有一連接該第一導電區的第一連接端及一連接該第二導電區的第二連接端，且該第一導電柱連接該第一導電區；以及一第二導電層，設置於該封裝單元層上，並包含一連接該第一導電柱的第一金屬走線。
  2. 如申請專利範圍第1項所述之封裝基板，其中，該第一電路元件為積體電路晶片或積層陶瓷電容器。
  3. 如申請專利範圍第1項所述之封裝基板，其中，該封膠材料充填於該封裝單元層內該第一電路元件及該第一導電柱之外的其餘部分。
  4. 如申請專利範圍第1項所述之封裝基板，其中，該封裝單元層進一步包含一第二導電柱，該第二導電層進一步包含一第二金屬走線，且該第二導電柱連接該第二導電區與該第二金屬走線。
  5. 如申請專利範圍第1項所述之封裝基板，其中，該封裝單元層進一步包含一第二電路元件，其具有一連接該第一導電區的第三連接端。
  6. 如申請專利範圍第1項所述之封裝基板，其中，該封裝單元層進一步包含一第二電路元件、一第二導電柱、及一第三導電柱，該第一導電層進一步包含一第三導電區，該第二電路元件具有一連接該第一導電區的第三連接端及一連接該第三導電區的第四連接端，該第二導電柱連接該第二導電區，且該第三導電柱連接該第三導電區。
  7. 如申請專利範圍第1項所述之封裝基板，其中，該封裝單元層進一步包含一連接單元，該第二導電層進一步包含一第二金屬走線，且該第一電路元件的第二連接端透過該連接單元連接該第二金屬走線。
  8. 如申請專利範圍第5項所述之封裝基板，其中，該封裝單元層進一步包含一第一連接單元、一第二連接單元、及一第三連接單元，該第二導電層進一步包含一第二金屬走線及一第三金屬走線，該第一電路元件的第二連接端透過該第一連接單元連接該第二金屬走線，該第一電路元件的第一連接端透過該第二連接單元連接該第三金屬走線，且該第二電路元件的第三連接端透過該第三連接單元連接該第一金屬走線。
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