JP6310224B2 - リセス内のストレッサを有する半導体素子の形成方法 - Google Patents
リセス内のストレッサを有する半導体素子の形成方法 Download PDFInfo
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- JP6310224B2 JP6310224B2 JP2013219213A JP2013219213A JP6310224B2 JP 6310224 B2 JP6310224 B2 JP 6310224B2 JP 2013219213 A JP2013219213 A JP 2013219213A JP 2013219213 A JP2013219213 A JP 2013219213A JP 6310224 B2 JP6310224 B2 JP 6310224B2
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Description
他の実施形態において、第2高速エッチング領域349を省略することができる。
22 ウェル
23 活性領域
23SU 第1表面
23S1 第1側面
23S2 第2側面
23S3 第2表面
E1 第1端
E2 第2端
29 素子分離膜
31 バッファ膜
33 仮設ゲート電極
35、37 マスクパターン
42 第1スペーサ
43 LDD(lightly doped drain)
45 ハロー(halo)
47、47A 第2スペーサ
49 高速エッチング領域(faster etch rate part)
51 第3スペーサ
51T リセス領域
53、55 トレンチ
61、61A、61B 第1半導体膜
62 第2半導体膜
63 第3半導体膜
65、65A、65B 内蔵ストレッサ(embedded stressor)
71 層間絶縁膜
73 第1ゲート誘電膜
75 第2ゲート誘電膜
77 第1ゲート電極
79 第2ゲート電極
100 半導体チップ
101 メモリ領域
102 第1領域
101C 第2領域
101P SRAM−peri
131 ゲート誘電膜
133 第1ゲート電極
134 内側スペーサ
142 第1スペーサ
147 第2スペーサ
151 第3スペーサ
181 第2ゲート電極
183 エッチング停止膜
185 層間絶縁膜
221 基板
222 ウェル
223 活性領域
225 バッファ膜
229 素子分離膜
231 仮設ゲート誘電膜
233 仮設ゲート電極
235 第1マスクパターン
237 第2マスクパターン
242 第1スペーサ
243 LDD(lightly doped drain)
245 ハロー(halo)
247 第2スペーサ
249 高速エッチング領域(faster etch rate part)
251 第3スペーサ
253、255、255A、255B トレンチ
262 第2半導体膜
263 第3半導体膜
265 内蔵ストレッサ(embedded stressor)
271 層間絶縁膜
273 第1ゲート誘電膜
275 第2ゲート誘電膜
279 ゲート電極
322 ウェル
323 活性領域
E31、E32 端
329 素子分離膜
331 バッファ膜
333 仮設ゲート電極
335、337 マスクパターン
342、347、351 スペーサ
343 LDD(lightly doped drain)
345 ハロー(halo)
349 高速エッチング領域(faster etch rate part)
353、355 トレンチ
361、362、363 半導体膜
365 内蔵ストレッサ(embedded stressor)
371 層間絶縁膜
373、375 ゲート誘電膜
377、379 ゲート電極
1900 スマートフォン
2100 電子システム
2110 ボディ
2120 マイクロプロセッサユニット
2130 パワーユニット
2140 機能ユニット
2150 ディスプレイコントローラユニット
2160 ディスプレイユニット
2170 外部装置
2180 通信ユニット
2400 電子システム
2412 メモリシステム
2414 マイクロプロセッサ
2416 RAM
2418 ユーザインターフェース
2420 バス
Claims (29)
- 活性領域を有する基板を準備する段階と、
前記活性領域にLDD(lightly doped drain)を形成する段階と、
前記LDD内にリン(P)を含む高速エッチング領域を形成する段階と、
前記高速エッチング領域の少なくとも一部を除去して前記活性領域内に第1トレンチを形成する段階と、
方向性エッチング工程を用いて前記第1トレンチを拡張して前記活性領域内にノッチ部分(notched portion)を有する第2トレンチを形成する段階と、
前記第2トレンチ内にストレッサ(stressor)を形成する段階と、
前記活性領域上にゲート電極を形成する段階と、を含み、
前記活性領域内の前記ノッチ部分は、前記第2トレンチに露出された前記LDDの表面に位置することを特徴とする半導体素子の形成方法。 - 前記LDDは、ボロン(B)を含むことを特徴とする請求項1に記載の半導体素子の形成方法。
- 前記第1トレンチを形成する段階は、等方性エッチング工程を含み、
前記第1トレンチは、前記高速エッチング領域に整列された上部トレンチ、及び前記LDDを貫通して前記上部トレンチの底面に連通されて前記上部トレンチよりも狭い幅を有する下部トレンチを含み、
前記第1トレンチの側壁は段差(step)を有することを特徴とする請求項1に記載の半導体素子の形成方法。 - 前記第1トレンチを形成する段階は、異方性エッチング工程をさらに含み、
前記異方性エッチング工程は前記等方性エッチング工程よりも先に実行されることを特徴とする請求項3に記載の半導体素子の形成方法。 - 前記活性領域の前記ノッチ部分は、上部側壁及び前記上部側壁に接触した下部側壁を含み、
前記活性領域の上部表面(uppermost surface)と前記上部側壁との間の角度は鋭角であって、
前記上部側壁は前記下部側壁と異なる傾斜を有することを特徴とする請求項1に記載の半導体素子の形成方法。 - 前記上部側壁は、前記第2トレンチに露出された前記LDDの表面に位置する融合インターフェース(convergence interface)で前記下部側壁に接触することを特徴とする請求項5に記載の半導体素子の形成方法。
- 前記ゲート電極は、前記上部側壁と前記下部側壁との前記融合インターフェース(convergence interface)に重畳され、
前記上部側壁の端(edge portion)は、前記ゲート電極の隣接した側壁の下に突出されていることを特徴とする請求項6に記載の半導体素子の形成方法。 - 前記高速エッチング領域は前記LDDよりも狭い幅を有することを特徴とする請求項1に記載の半導体素子の形成方法。
- 前記高速エッチング領域は前記LDDの底面よりも高いレベルに形成されていることを特徴とする請求項8に記載の半導体素子の形成方法。
- 前記LDDは前記活性領域と前記高速エッチング領域との間に保存されていることを特徴とする請求項9に記載の半導体素子の形成方法。
- 前記高速エッチング領域は前記LDDと前記ストレッサとの間に保存されていることを特徴とする請求項8に記載の半導体素子の形成方法。
- 前記LDDを形成する段階の前に、前記活性領域上に仮設ゲート電極を形成して前記仮設ゲート電極の側壁上に第1スペーサを形成する段階と、
前記ストレッサを形成する段階の後に、前記仮設ゲート電極を除去する段階とをさらに含むことを特徴とする請求項1に記載の半導体素子の形成方法。 - 前記高速エッチング領域を形成する段階の前に、前記活性領域上に仮設ゲート電極を形成して前記仮設ゲート電極の側壁上に第2スペーサを形成する段階と、
前記ストレッサを形成する段階の後に、前記仮設ゲート電極を除去する段階とをさらに含むことを特徴とする請求項1に記載の半導体素子の形成方法。 - 前記第1トレンチを形成する段階の前に、前記活性領域上に仮設ゲート電極を形成して前記仮設ゲート電極の側壁上に第3スペーサを形成する段階と、
前記ストレッサを形成する段階の後に、前記仮設ゲート電極を除去する段階とをさらに含むことを特徴とする請求項1に記載の半導体素子の形成方法。 - 前記ストレッサ(stressor)を形成する段階は、
前記第2トレンチ内に第1半導体膜を形成する段階と、
前記第1半導体膜上に第2半導体膜を形成する段階と、
前記第2半導体膜上に第3半導体膜を形成する段階とを含み、
前記第1半導体膜及び前記第2半導体膜は前記活性領域とは異なる物質を含むことを特徴とする請求項1に記載の半導体素子の形成方法。 - 前記第1半導体膜、前記第2半導体膜、及び前記第3半導体膜は、選択的エピタキシャル成長(selective epitaxial growth)技術を用いて形成されることを特徴とする請求項15に記載の半導体素子の形成方法。
- 前記第1半導体膜及び前記第2半導体膜はSiGe膜を含み、前記第2半導体膜内でのGe含有割合は前記第1半導体膜内よりも高いことを特徴とする請求項16に記載の半導体素子の形成方法。
- 前記第3半導体膜は、Si膜を含むことを特徴とする請求項17に記載の半導体素子の形成方法。
- 第1領域に規定された第1活性領域及び前記第1領域とパターン密度が異なる第2領域に規定された第2活性領域を有する基板を準備する段階と、
前記第1活性領域に第1LDD及び前記第2活性領域に第2LDDを形成する段階と、
前記第1活性領域にリン(P)を含む第1高速エッチング領域及び前記第2活性領域にリン(P)を含む第2高速エッチング領域を形成する段階と、
前記第1高速エッチング領域を除去して第1予備トレンチ及び前記第2高速エッチング領域を除去して第2予備トレンチを形成する段階と、
方向性エッチング工程を用いて、前記第1予備トレンチを拡張して前記第1活性領域内に第1ノッチ部分(notched portion)を有する第1トレンチ及び前記第2予備トレンチを拡張して前記第2活性領域内に第2ノッチ部分(notched portion)を有する第2トレンチを形成する段階と、
前記第1トレンチ内に第1ストレッサ及び前記第2トレンチ内に第2ストレッサを形成する段階と、
前記第1活性領域上に第1ゲート電極及び前記第2活性領域上に第2ゲート電極を形成する段階と、を含むことを特徴とする半導体素子の形成方法。 - 前記第1活性領域の前記第1ノッチ部分は、第1融合インターフェース(convergence interface)で第1下部側壁と接触された第1上部側壁を含み、
前記第2活性領域の前記第2ノッチ部分は、第2融合インターフェース(convergence interface)で第2下部側壁と接触された第2上部側壁を含み、
前記第1ゲート電極は、前記第1融合インターフェースに重畳され、
前記第2ゲート電極は、前記第2融合インターフェースに重畳されず、
前記第1融合インターフェースは、前記第2融合インターフェースよりも高いレベルに形成されていることを特徴とする請求項19に記載の半導体素子の形成方法。 - 前記第1融合インターフェースと前記第1ゲート電極の側面との間の水平距離は0nm〜−5nmであり、
前記第2融合インターフェースと前記第2ゲート電極の側面の間の水平距離は+1nm〜+3nmであることを特徴とする請求項20に記載の半導体素子の形成方法。 - 前記第1融合インターフェースと前記第1活性領域の上部表面との間の垂直高さは3nm〜7nmであり、
前記第2融合インターフェースと前記第2活性領域の上部表面との間の垂直高さは8nm〜12nmであることを特徴とする請求項20に記載の半導体素子の形成方法。 - 前記第1融合インターフェースは前記第1トレンチに露出された前記第1LDDの表面に形成され、前記第2融合インターフェースは前記第2トレンチに露出された前記第2LDDの表面に形成され、
前記第2LDDは前記第1LDDよりも高い濃度のボロン(B)を含むことを特徴とする請求項20に記載の半導体素子の形成方法。 - 前記第2高速エッチング領域は前記第1高速エッチング領域よりも低い濃度のリン(P)を含むことを特徴とする請求項19に記載の半導体素子の形成方法。
- 基板上にゲート構造を形成する段階と、
前記ゲート構造の側壁に隣接した前記基板内にLDDを形成する段階と、
前記基板内の少なくとも前記基板内に形成されたLDD内に前記ゲート構造の前記側壁に隣接したドーピングパターン(doped pattern)を形成する段階と、
前記ゲート構造をエッチングマスクとして用いて前記ドーピングパターンの一部分をエッチングして前記ドーピングパターンが露出された側壁を有する第1予備キャビティを形成する段階と、
前記第1予備キャビティの側壁に露出されたドーピングパターンを選択的にエッチングして第2予備キャビティを形成する段階と、
方向性エッチング工程を用いて、前記第2予備キャビティの露出した表面をエッチングしてキャビティを形成する段階と、
前記キャビティ内にストレッサを形成する段階と、を含み、
前記キャビティは前記ゲート構造の下のリセスを含み、前記リセスは上部側壁及び前記上部側壁に接触した下部側壁からなる2つの収斂する傾斜部(two converging sloped portion)を含むノッチ部分を有し、
前記ノッチ部分は、前記キャビティに露出された前記LDDの表面に位置することを特徴とする半導体素子形成方法。 - 前記ドーピングパターンを形成する段階は、
前記ゲート構造をイオン注入マスクとして用いて前記基板内にイオン注入する段階を含むことを特徴とする請求項25に記載の半導体素子形成方法。 - 前記イオン注入する段階は、前記基板内にリン(P)を注入する段階を含むことを特徴とする請求項26に記載の半導体素子形成方法。
- 前記LDDを形成する段階の後に、前記ゲート構造の側壁上にスペーサパターンを形成する段階をさらに含み、
前記イオン注入する段階は、前記スペーサパターン及び前記ゲート構造をイオン注入マスクとして用いて実行する段階を含むことを特徴とする請求項26に記載の半導体素子形成方法。 - 前記方向性エッチング工程は、前記基板の結晶方向に依存して多数の異なったエッチレート(etch rate)で前記基板をエッチングするエッチング工程を含むことを特徴とする請求項25に記載の半導体素子形成方法。
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