CN109671674A - 半导体装置的制作方法 - Google Patents

半导体装置的制作方法 Download PDF

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CN109671674A
CN109671674A CN201710953110.3A CN201710953110A CN109671674A CN 109671674 A CN109671674 A CN 109671674A CN 201710953110 A CN201710953110 A CN 201710953110A CN 109671674 A CN109671674 A CN 109671674A
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manufacture craft
ion implanting
semiconductor device
production method
implanting manufacture
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叶俊麟
曾学志
蔡佳真
罗大刚
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/803,865 priority patent/US10607891B2/en
Publication of CN109671674A publication Critical patent/CN109671674A/zh
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Abstract

本发明公开一种半导体装置的制作方法，其包括下列步骤，在半导体基底的第一区与第二区上分别形成多个第一栅极结构与多个第二栅极结构。第二栅极结构之间的间距大于第一栅极结构之间的间距。进行第一离子注入制作工艺，用以于第一栅极结构之间形成第一掺杂区。进行第二离子注入制作工艺，用以于第二栅极结构之间形成第二掺杂区。第二离子注入制作工艺的倾斜角度大于第一离子注入制作工艺的倾斜角度。第二离子注入制作工艺的注入剂量低于第一离子注入制作工艺的注入剂量。进行蚀刻制作工艺，用以移除至少部分的第一掺杂区而形成第一凹陷，且用以移除至少部分的第二掺杂区而形成第二凹陷。

Description

半导体装置的制作方法
技术领域
本发明涉及一种半导体装置的制作方法，尤其是涉及一种包括离子注入制作工艺的半导体装置的制作方法。
背景技术
随着半导体集成电路工业的技术发展，越来越多的半导体装置可被整合于一半导体集成电路(integrated circuit，IC)中，而个别半导体装置的体积则变得越来越小。场效晶体管(field-effect transistor，FET)为半导体IC中当作基础单元的典型半导体装置。一个场效晶体管可包括一栅极结构形成于一半导体基底上以及一源极与一漏极形成于半导体基底中且与栅极结构相邻。在现有技术中，源极与漏极以对半导体基底进行掺杂而形成。随着集成电路的集成度越来越高且集成电路中的场效晶体管越来越小，许多不同的制作工艺被开发来形成源极与漏极，而其中一种制作工艺是利用外延技术来形成源极与漏极。在此制作工艺中，半导体基底被蚀刻而形成凹陷，并接着于凹陷中以外延方式形成半导体材料而由此形成源极与漏极。
在凹陷中所形成的半导体材料可视不同种类的场效晶体管而有所变化。举例来说，若要形成P型通道场效晶体管，可于凹陷中形成硅锗(SiGe)材料以形成源极与漏极。由于硅锗具有比硅更大的晶格常数，故硅锗的源极与漏极会对场效晶体管的通道产生压缩应力，进而使得通道的空穴迁移率增加。此外，若要形成N型通道场效晶体管，可于凹陷中形成掺杂磷的硅(Si:P)以形成源极与漏极。然而，外延成长所形成的材料容易受到叠差(stacking fault)等缺陷状况影响其材料特性，而当此些缺陷状况分布不均匀时，不但会使得晶体管的电性表现发生变化，另一方面也会导致不同晶体管之间的电性均匀性变差而直接影响到生产良率。
发明内容
本发明提供了一种半导体装置的制作方法，对于具有不同栅极结构间距的区域进行不同制作工艺条件的离子注入制作工艺以形成所需的掺杂区，由此减少离子注入制作工艺对于具有不同栅极结构间距的区域所造成的影响差异，进而达到改善半导体装置的电性均匀性的效果。
本发明的一实施例提供一种半导体装置的制作方法，包括下列步骤。首先，提供一半导体基底，半导体基底上定义有一第一区与一第二区。在半导体基底的第一区上形成多个第一栅极结构。在半导体基底的第二区上形成多个第二栅极结构。多个第二栅极结构之间的间距大于多个第一栅极结构之间的间距。进行一第一离子注入制作工艺，用以于多个第一栅极结构之间的半导体基底中形成一第一掺杂区。进行一第二离子注入制作工艺，用以于多个第二栅极结构之间的半导体基底中形成一第二掺杂区。第二离子注入制作工艺的倾斜角度大于第一离子注入制作工艺的倾斜角度，且第二离子注入制作工艺的注入剂量低于第一离子注入制作工艺的注入剂量。进行一蚀刻制作工艺，用以移除至少部分的第一掺杂区而于半导体基底中形成一第一凹陷，且用以移除至少部分的第二掺杂区而于半导体基底中形成一第二凹陷。
附图说明
图1至图6为本发明第一实施例的半导体装置的制作方法示意图，其中
图2为沿图1中A-A’剖线所绘示的剖视图；
图3为图2之后的状况示意图；
图4为图3之后的状况示意图；
图5为图4之后的状况示意图；
图6为图5之后的状况示意图。
图7为栅极结构间距与漏极电流变异之间的关系示意图。
图8与图9为本发明第二实施例的半导体装置的制作方法示意图，其中图9为图8之后的状况示意图。
主要元件符号说明
10 半导体基底
10A 主动区
11 浅沟槽隔离
21A 第一介电层
21B 第二介电层
22A 第一栅极材料层
22B 第二栅极材料层
23A 第一盖层
23B 第二盖层
31 第一掺杂区
32 第二掺杂区
41 第一掩模层
42 第二掩模层
51 第一外延结构
52 第二外延结构
81 第一离子注入制作工艺
82 第二离子注入制作工艺
90 蚀刻制作工艺
A1 第一倾斜角
A2 第二倾斜角
D1 第一方向
D2 第二方向
D3 厚度方向
GS1 第一栅极结构
GS2 第二栅极结构
H1 第一高度
H2 第二高度
R1 第一区
R2 第二区
RC1 第一凹陷
RC2 第二凹陷
S1 第一间距
S2 第二间距
SP1 第一间隙子
SP2 第二间隙子
W1 第一宽度
W2 第二宽度
W3 第三宽度
W4 第四宽度
具体实施方式
请参阅图1至图6。图1至图6所绘示为本发明第一实施例的半导体装置的制作方法示意图，其中图1为上视图，而图2可被视为沿图1中A-A’剖线所绘示的剖视图。本实施例的半导体装置的制作方法可包括下列步骤。首先，如图1与图2所示，提供一半导体基底10，半导体基底10上定义有一第一区R1与一第二区R2。然后，在半导体基底10的第一区R1上形成多个第一栅极结构GS1，且于半导体基底10的第二区R2上形成多个第二栅极结构GS2。在一些实施例中，各第一栅极结构GS1以及各第二栅极结构GS2可分别沿第一方向D1延伸，多个第一栅极结构GS1可沿一第二方向D2重复排列且具有相同的间距(例如图2中所示的第一间距S1)，多个第二栅极结构GS2可沿第二方向D2重复排列且具有相同的间距(例如图2中所示的第二间距S2)，而第二方向D2可大体上与第一方向D1正交，但并不以此为限。在一些实施例中，也可视需要使第一栅极结构GS1与第二栅极结构GS2分别沿不同的方向延伸。此外，多个第二栅极结构GS2之间的第二间距S2大于多个第一栅极结构GS1之间的第一间距S1，而第一区R1上未形成有第二栅极结构GS2，且第二区R2上未形成有第一栅极结构GS1。换句话说，第一区R1上的栅极结构具有相对较小的间距，而第二区R2上的栅极结构具有相对较大的间距。
在一些实施例中，第一栅极结构GS1与第二栅极结构GS2可由相同的制作工艺一并形成，故可有相似的结构，但并不以此为限。举例来说，在一些实施例中，各第一栅极结构GS1可包括一第一介电层21A、一第一栅极材料层22A以及一第一盖层23A于半导体基底10的厚度方向D3上堆叠设置，而各第二栅极结构GS2可包括一第二介电层21B、一第二栅极材料层22B以及一第二盖层23B于半导体基底10的厚度方向D3上堆叠设置。第一介电层21A与第二介电层21B可包括相同的材料例如氧化硅、氮氧化硅、高介电常数(high dielectricconstant，high-k)材料或其他适合的介电材料。上述的高介电常数材料可包括例如氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化锆(zirconium oxide,ZrO2)或其他适合的高介电常数材料。第一栅极材料层22A与第二栅极材料层22B可包括相同的材料例如多晶硅、非晶硅或金属导电材料。而第一盖层23A与第二盖层23B可包括相同的材料例如氮化硅、氮氧化硅、氮碳化硅或其他适合的绝缘材料。在一些实施例中，第一栅极结构GS1中的第一栅极材料层22A与第二栅极结构GS2中的第二栅极材料层22B可当作取代金属栅极(replacement metal gate，RMG)制作工艺中的虚置栅极(dummy gate)，但并不以此为限。此外，在一些实施例中，各第一栅极结构GS1的高度(例如图2中所示的第一高度H1)与各第二栅极结构GS2的高度(例如图2中所示的第二高度H2)可大体上相同，而各第一栅极结构GS1的宽度(例如图2中所示的第一宽度W1)可小于各第二栅极结构GS2的宽度(例如图2中所示的第二宽度W2)，但并不以此为限。在一些实施例中，各第一栅极结构GS1的第一宽度W1也可视需要与各第二栅极结构GS2的第二宽度W2大体上相同。
在一些实施例中，半导体基底10可包括硅基底、外延基底、硅覆绝缘(silicon-on-insulator，SOI)基底或其他适合材料的半导体基底。如图1与图2所示，半导体基底10中可形成有浅沟槽隔离11，通过浅沟槽隔离11可于半导体基底10中定义出多个主动区(activearea)10A，而各第一栅极结构GS1与各第二栅极结构GS2可分别部分设置于对应的主动区10A上，但并不以此为限。在一些实施例中，半导体基底10可包括多个鳍状结构(未绘示)，浅沟槽隔离11可位于各鳍状结构之间，而各第一栅极结构GS1与各第二栅极结构GS2可分别跨设于对应的鳍状结构上。
接着，如图3所示，进行一第一离子注入制作工艺81，用以于多个第一栅极结构GS1之间的半导体基底10中形成一第一掺杂区31。在一些实施例中，在第一离子注入制作工艺81进行之前，可于各第一栅极结构GS1与各第二栅极结构GS2的侧壁上形成一第一间隙子SP1，并形成一第一掩模层41覆盖第二区R2以及位于第二区R2上的第二栅极结构GS2。换句话说，在第一离子注入制作工艺81中，半导体基底10的第一区R1被第一掩模层覆盖41，而通过第一掩模层41形成阻挡效果可使得第一离子注入制作工艺81的掺杂质无法注入位于第二栅极结构GS2之间的半导体基底10中。在一些实施例中，第一间隙子SP1可包括由绝缘材料例如氧化硅、氮化硅、氮氧化硅或其他适合的绝缘材料所构成的单层结构或复合层结构，而第一掩模层41可包括光致抗蚀剂材料或其他适合的掩模材料。
然后，如图4所示，进行一第二离子注入制作工艺82，用以于多个第二栅极结构GS2之间的半导体基底10中形成一第二掺杂区32。在一些实施例中，在第二离子注入制作工艺82进行之前，可形成一第二掩模层42覆盖第一区R1以及位于第一区R1上的第一栅极结构GS1。换句话说，于第二离子注入制作工艺82中，半导体基底10的第一区R1被第二掩模层覆盖42，而通过第二掩模层42形成阻挡效果可使得第二离子注入制作工艺82的掺杂质无法注入位于第一栅极结构GS1之间的半导体基底10中。第二掩模层42也可包括光致抗蚀剂材料或其他适合的掩模材料。
如图3与图4所示，在一些实施例中，第一离子注入制作工艺81与第二离子注入制作工艺82可为相同类型的离子注入制作工艺，例如用以形成轻掺杂区(lightly dopedregion)或/袋状注入(pocket implantation)效果的离子注入制作工艺，但并不以为限。因此，在一些实施例中，第一离子注入制作工艺81中使用的掺杂质可与第二离子注入制作工艺82中使用的掺杂质相同，例如第一离子注入制作工艺81中使用的掺杂质与第二离子注入制作工艺82中使用的掺杂质可包括砷(arsenic)、碳或其他适合的材料。
一般来说，离子注入制作工艺将掺杂质注入进入半导体基底10时可能会造成结构损伤、破坏晶格结构等问题而影响后续进行的外延成长制作工艺的外延品质，而所形成的掺杂区内的掺杂质也可能会影响后续进行的蚀刻制作工艺的蚀刻状况。因此，为了避免因为栅极结构的间距不同而导致离子注入制作工艺的效果以及上述的影响状况产生过大差异，进而使得栅极结构的间距不同的区域中所形成的半导体元件的电性表现差异过大而影响生产良率以及线路设计，本发明可通过对具有不同栅极结构间距的区域分开进行相同种类但制作工艺条件不同的离子注入制作工艺，由此缩小具有不同栅极结构间距的区域之间的电性差异，对于制作工艺良率以及集成电路的设计上都有正面帮助。
换句话说，第一离子注入制作工艺81与第二离子注入制作工艺82可为相同类型的离子注入制作工艺，但第二离子注入制作工艺82部分的制作工艺条件可与第一离子注入制作工艺81不同，由此补偿因栅极结构的间距不同而导致离子注入制作工艺的效果与其他影响状况产生过大差异的状况。在一些实施例中，第二离子注入制作工艺82的倾斜角度(例如图4中所示的第二倾斜角A2的角度)可大于第一离子注入制作工艺81的倾斜角度(例如图3中所示的第一倾斜角A1的角度)，且第二离子注入制作工艺82的注入剂量可低于第一离子注入制作工艺81的注入剂量，由此于栅极结构的间距较大的状况下达到降低离子注入所产生的结构损伤以及破坏晶格结构等问题。在一些实施例中，第二离子注入制作工艺82的倾斜角度可介于20度至30度之间，而第二离子注入制作工艺82的注入剂量可介于120E13离子/平方厘米(ions/cm2)至180E13ions/cm2之间，但并不以此为限。在一些实施例中，第二离子注入制作工艺82的注入剂量可介于135E13ions/cm2至165E13ions/cm2之间。
如图3至图5所示，在第一离子注入制作工艺81以及第二离子注入制作工艺82之后，进行一蚀刻制作工艺90，用以移除至少部分的第一掺杂区31而于半导体基底10中形成一第一凹陷RC1，且用以移除至少部分的第二掺杂区32而于半导体基底10中形成一第二凹陷RC2。在一些实施例中，可于蚀刻制作工艺90之前移除第一掩模层41与第二掩模层42，而于蚀刻制作工艺90进行之前可于第一间隙子SP1上形成第二间隙子SP2，并以第一盖层23A、第二盖层23B、第一间隙子SP1以及第二间隙子SP2当作蚀刻制作工艺90时的掩模，但并不以此为限。更明确地说，在一些实施例中，第一离子注入制作工艺81可于第二离子注入制作工艺82之前进行，第一掩模层41可于第二离子注入制作工艺82之前被移除，而第二掩模层42可于移除第一掩模层41的步骤之后形成，但本发明并不以此为限。在另一些实施例中，也可视需要于第二离子注入制作工艺82之后进行第一离子注入制作工艺81，并调整第一掩模层41与第二掩模层42的形成步骤与移除步骤。
此外，在一些实施例中，蚀刻制作工艺90可包括各向异性蚀刻制作工艺例如干式蚀刻制作工艺形成垂直方向的蚀刻效果，并可通过各向同性蚀刻制作工艺例如湿式蚀刻制作工艺来形成横向方向的蚀刻效果，由此形成所需的凹陷状况。如图5所示，在一些实施例中，蚀刻制作工艺90可沿着特定轮廓蚀刻并移除至少部分的第一掺杂区31与第二掺杂区32，故所形成的第一凹陷RC1与第二凹陷RC2可具有如钻石般的多角形剖面形状，但并不此为限。由于第一栅极结构GS1的间距小于第二栅极结构GS2的间距，故第一凹陷RC1的宽度(例如图5所示的第三宽度W3)可小于第二凹陷RC2的宽度(例如图5所示的第四宽度W4)。
接着，如图6所示，可进行一选择性外延成长(selective epitaxial growth，SEG)制作工艺，而于第一凹陷RC1中形成一第一外延结构51，并于第二凹陷RC2中形成一第二外延结构52，故第一外延结构51的成分可与第二外延结构52的成分相同。在一些实施例中，第一外延结构51与第二外延结构52可分别包括一硅锗(silicon germanium，SiGe)外延结构或碳化硅(silicon carbide，SiC)外延结构。此外，在上述的选择性外延成长制作工艺之前、选择性外延成长制作工艺之后或选择性外延成长制作工艺进行时，可进行一同步离子掺杂制作工艺，用以将所需的掺杂质掺入第一外延结构51与第二外延结构52中，使得第一外延结构51与第二外延结构52可分别作为一晶体管元件的源极/漏极。第一外延结构51与第二外延结构52可分别沿着第一凹陷RC1与第二凹陷RC2的底部及侧边的表面形成而具有第一凹陷RC1与第二凹陷RC2的轮廓，故第一外延结构51与第二外延结构52可分别具有指向对应的通道区域的尖角，而此尖角可于晶体管元件的通道区域两侧更有效地提供所需应力，故可用以增加晶体管元件的通道区域的载流子迁移率。
请参阅图6与图7。图7所绘示为对具有不同栅极结构间距的区域进行相同制作工艺条件的离子注入制作工艺的状况下，栅极结构间距与所形成的晶体管的漏极电流变异之间的关系分布状况。如图7所示，若使用相同制作工艺条件的离子布质制作工艺，当栅极结构间距大于100纳米的状况下，漏极电流变异很显著地由约15％上升至25～30％。因此，对于栅极结构间距较大的区域需通过进行不同制作工艺条件的离子注入制作工艺来缩小具有不同栅极结构间距的区域之间的电性差异，进而达到提升制作工艺良率以及改善电性均匀性的效果。因此，在一些实施例中，如图2所示，第二栅极结构GS2之间的第二间距S2可大于100纳米，或者第二栅极结构GS2之间的第二间距S2也可大于120纳米，但并不以此为限。
下文将针对本发明的不同实施例进行说明，且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，以利于各实施例间互相对照。
请参阅图8与图9。图8与图9所绘示为本发明第二实施例的半导体装置的制作方法示意图。如图8与图9所示，与上述第一实施例不同的地方在于，在本实施例的制作方法中，第一离子注入制作工艺81可于第二离子注入制作工艺82之后进行。因此，在一些实施例中，第二掩模层42可于第一离子注入制作工艺81之前被移除，而第一掩模层41可于移除第二掩模层42的步骤之后形成，但并不以此为限。
综上所述，在本发明的半导体装置的制作方法中，可对具有不同栅极结构间距的区域分开进行相同种类但制作工艺条件不同的离子注入制作工艺，由此缩小具有不同栅极结构间距的区域之间于后续所形成的半导体元件的电性差异，进而达到改善半导体装置的电性均匀性以及提升相关生产良率的效果。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种半导体装置的制作方法，包括：
提供一半导体基底，该半导体基底上定义有一第一区与一第二区；
在该半导体基底的该第一区上形成多个第一栅极结构；
在该半导体基底的该第二区上形成多个第二栅极结构，其中该多个第二栅极结构之间的间距大于该多个第一栅极结构之间的间距；
进行一第一离子注入制作工艺，用以于该多个第一栅极结构之间的该半导体基底中形成一第一掺杂区；
进行一第二离子注入制作工艺，用以于该多个第二栅极结构之间的该半导体基底中形成一第二掺杂区，其中该第二离子注入制作工艺的倾斜角度大于该第一离子注入制作工艺的倾斜角度，且该第二离子注入制作工艺的注入剂量低于该第一离子注入制作工艺的注入剂量；以及
进行一蚀刻制作工艺，用以移除至少部分的该第一掺杂区而于该半导体基底中形成一第一凹陷，且用以移除至少部分的该第二掺杂区而于该半导体基底中形成一第二凹陷。
2.如权利要求1所述的半导体装置的制作方法，其中该多个第二栅极结构之间的该间距大于100纳米。
3.如权利要求2所述的半导体装置的制作方法，其中该多个第二栅极结构之间的该间距大于120纳米。
4.如权利要求1所述的半导体装置的制作方法，其中该第二离子注入制作工艺的该倾斜角度介于20度至30度之间。
5.如权利要求1所述的半导体装置的制作方法，其中该第二离子注入制作工艺的该注入剂量介于120E13离子/平方厘米至180E13离子/平方厘米之间。
6.如权利要求5所述的半导体装置的制作方法，其中该第二离子注入制作工艺的该注入剂量介于135E13离子/平方厘米至165E13离子/平方厘米之间。
7.如权利要求1所述的半导体装置的制作方法，其中该第一离子注入制作工艺中使用的掺杂质与该第二离子注入制作工艺中使用的掺杂质相同。
8.如权利要求1所述的半导体装置的制作方法，其中该第一离子注入制作工艺中使用的该掺杂质与该第二离子注入制作工艺中使用的该掺杂质包括砷或碳。
9.如权利要求1所述的半导体装置的制作方法，还包括：
在该第一凹陷中形成一第一外延结构；以及
在该第二凹陷中形成一第二外延结构，其中该第一外延结构的成分与该第二外延结构的成分相同。
10.如权利要求9所述的半导体装置的制作方法，其中该第一外延结构以及该第二外延结构分别包括一硅锗外延结构。
11.如权利要求1所述的半导体装置的制作方法，还包括：
形成一第一掩模层覆盖该半导体基底的该第二区，其中于该第一离子注入制作工艺中，该半导体基底的该第二区被该第一掩模层覆盖；
形成一第二掩模层覆盖该半导体基底的该第一区，其中于该第二离子注入制作工艺中，该半导体基底的该第一区被该第二掩模层覆盖；
在该蚀刻制作工艺之前，移除该第一掩模层；以及
在该蚀刻制作工艺之前，移除该第二掩模层。
12.如权利要求11所述的半导体装置的制作方法，其中该第一离子注入制作工艺于该第二离子注入制作工艺之前进行。
13.如权利要求12所述的半导体装置的制作方法，其中该第一掩模层于该第二离子注入制作工艺之前被移除。
14.如权利要求12所述的半导体装置的制作方法，其中该第二掩模层是于移除该第一掩模层的步骤之后形成。
15.如权利要求11所述的半导体装置的制作方法，其中该第一离子注入制作工艺于该第二离子注入制作工艺之后进行。
16.如权利要求15所述的半导体装置的制作方法，其中该第二掩模层于该第一离子注入制作工艺之前被移除。
17.如权利要求15所述的半导体装置的制作方法，其中该第一掩模层是于移除该第二掩模层的步骤之后形成。
18.如权利要求1所述的半导体装置的制作方法，其中各该第一栅极结构的高度与各该第二栅极结构的高度相同。
19.如权利要求1所述的半导体装置的制作方法，其中各该第一栅极结构的宽度小于各该第二栅极结构的宽度。
20.如权利要求1所述的半导体装置的制作方法，其中该第一凹陷的宽度小于该第二凹陷的宽度。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114446812A (zh) * 2020-11-06 2022-05-06 长鑫存储技术有限公司 测试结构及其制作方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102020112695A1 (de) * 2019-05-31 2020-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. Optimiertes näheprofil für verspanntes source/drain-merkmal und verfahren zu dessen herstellung
US11489062B2 (en) * 2019-05-31 2022-11-01 Taiwan Semiconductor Manufacturing Co., Ltd Optimized proximity profile for strained source/drain feature and method of fabricating thereof
KR20210043842A (ko) * 2019-10-14 2021-04-22 삼성전자주식회사 반도체 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020019103A1 (en) * 1999-11-01 2002-02-14 Taiwan Semiconductor Manufacturing Company Tilt-angle ion implant to improve junction breakdown in flash memory application
CN101677089A (zh) * 2008-09-19 2010-03-24 海力士半导体有限公司 非易失存储器件及其制造方法
CN103839890A (zh) * 2012-11-22 2014-06-04 三星电子株式会社 包括凹槽中的应力源的半导体器件及其形成方法
US20150179654A1 (en) * 2013-12-19 2015-06-25 Texas Instruments Incorporated Epitaxial source/drain differential spacers
CN106024793A (zh) * 2015-03-26 2016-10-12 三重富士通半导体股份有限公司 半导体器件

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784062B2 (en) * 2002-06-03 2004-08-31 Micron Technology, Inc. Transistor formation for semiconductor devices
US6936528B2 (en) * 2002-10-17 2005-08-30 Samsung Electronics Co., Ltd. Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film
US7084025B2 (en) * 2004-07-07 2006-08-01 Chartered Semiconductor Manufacturing Ltd Selective oxide trimming to improve metal T-gate transistor
US7071046B2 (en) 2004-11-18 2006-07-04 United Microelectronics Corp. Method of manufacturing a MOS transistor
US20060234455A1 (en) * 2005-04-19 2006-10-19 Chien-Hao Chen Structures and methods for forming a locally strained transistor
WO2008136158A1 (ja) * 2007-04-24 2008-11-13 Sharp Kabushiki Kaisha 表示装置用基板、表示装置及び配線基板
US7632727B2 (en) * 2008-05-12 2009-12-15 Globalfoundries Inc. Method of forming stepped recesses for embedded strain elements in a semiconductor device
KR101776926B1 (ko) * 2010-09-07 2017-09-08 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8513105B2 (en) * 2010-10-14 2013-08-20 Texas Instruments Incorporated Flexible integration of logic blocks with transistors of different threshold voltages
US8501570B2 (en) * 2010-10-20 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing source/drain structures
US8822278B2 (en) * 2012-03-29 2014-09-02 International Business Machines Corporation Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure
US8691644B2 (en) * 2012-07-05 2014-04-08 Texas Instruments Incorporated Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor
CN105023843A (zh) * 2014-04-22 2015-11-04 联华电子股份有限公司 半导体元件的制作方法
US9548369B2 (en) * 2015-03-26 2017-01-17 Macronix International Co., Ltd. Memory device and method of manufacturing the same
US10163912B2 (en) * 2016-01-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method for semiconductor device fabrication with improved source drain proximity

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020019103A1 (en) * 1999-11-01 2002-02-14 Taiwan Semiconductor Manufacturing Company Tilt-angle ion implant to improve junction breakdown in flash memory application
CN101677089A (zh) * 2008-09-19 2010-03-24 海力士半导体有限公司 非易失存储器件及其制造方法
CN103839890A (zh) * 2012-11-22 2014-06-04 三星电子株式会社 包括凹槽中的应力源的半导体器件及其形成方法
US20150179654A1 (en) * 2013-12-19 2015-06-25 Texas Instruments Incorporated Epitaxial source/drain differential spacers
CN106024793A (zh) * 2015-03-26 2016-10-12 三重富士通半导体股份有限公司 半导体器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114446812A (zh) * 2020-11-06 2022-05-06 长鑫存储技术有限公司 测试结构及其制作方法
CN114446812B (zh) * 2020-11-06 2024-09-27 长鑫存储技术有限公司 测试结构及其制作方法

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