JP6178499B2 - ダイナミックランダムアクセスメモリのスマートリフレッシュのための方法およびシステム - Google Patents
ダイナミックランダムアクセスメモリのスマートリフレッシュのための方法およびシステム Download PDFInfo
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- JP6178499B2 JP6178499B2 JP2016513993A JP2016513993A JP6178499B2 JP 6178499 B2 JP6178499 B2 JP 6178499B2 JP 2016513993 A JP2016513993 A JP 2016513993A JP 2016513993 A JP2016513993 A JP 2016513993A JP 6178499 B2 JP6178499 B2 JP 6178499B2
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- Prior art keywords
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- memory
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- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/893,670 | 2013-05-14 | ||
| US13/893,670 US9336855B2 (en) | 2013-05-14 | 2013-05-14 | Methods and systems for smart refresh of dynamic random access memory |
| PCT/US2014/037525 WO2014186229A1 (en) | 2013-05-14 | 2014-05-09 | Methods and systems for smart refresh of dynamic random access memory |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016524775A JP2016524775A (ja) | 2016-08-18 |
| JP2016524775A5 JP2016524775A5 (enExample) | 2017-03-30 |
| JP6178499B2 true JP6178499B2 (ja) | 2017-08-09 |
Family
ID=50842406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016513993A Active JP6178499B2 (ja) | 2013-05-14 | 2014-05-09 | ダイナミックランダムアクセスメモリのスマートリフレッシュのための方法およびシステム |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9336855B2 (enExample) |
| EP (1) | EP2997576B1 (enExample) |
| JP (1) | JP6178499B2 (enExample) |
| KR (1) | KR101834625B1 (enExample) |
| CN (1) | CN105229743B (enExample) |
| TW (1) | TWI525618B (enExample) |
| WO (1) | WO2014186229A1 (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013183155A1 (ja) * | 2012-06-07 | 2013-12-12 | 富士通株式会社 | 選択的にメモリのリフレッシュを行う制御装置 |
| US9355689B2 (en) * | 2013-08-20 | 2016-05-31 | Oracle International Corporation | Detection of multiple accesses to a row address of a dynamic memory within a refresh period |
| US9626331B2 (en) * | 2013-11-01 | 2017-04-18 | International Business Machines Corporation | Storage device control |
| US9728245B2 (en) | 2015-02-28 | 2017-08-08 | Intel Corporation | Precharging and refreshing banks in memory device with bank group architecture |
| KR102384344B1 (ko) | 2015-06-03 | 2022-04-07 | 삼성전자주식회사 | 모바일 장치 및 모바일 장치의 동작 방법 |
| KR102373544B1 (ko) | 2015-11-06 | 2022-03-11 | 삼성전자주식회사 | 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법 |
| US9972375B2 (en) * | 2016-04-15 | 2018-05-15 | Via Alliance Semiconductor Co., Ltd. | Sanitize-aware DRAM controller |
| US10199115B2 (en) * | 2016-06-20 | 2019-02-05 | Qualcomm Incorporated | Managing refresh for flash memory |
| TWI639920B (zh) | 2017-11-17 | 2018-11-01 | 財團法人工業技術研究院 | 記憶體控制器及其控制方法以及記憶體及其控制方法 |
| US10644004B2 (en) * | 2018-02-13 | 2020-05-05 | Advanced Micro Devices, Inc. | Utilizing capacitors integrated with memory devices for charge detection to determine DRAM refresh |
| US10878880B2 (en) | 2018-09-20 | 2020-12-29 | Qualcomm Incorporated | Selective volatile memory refresh via memory-side data valid indication |
| TWI671632B (zh) | 2018-10-24 | 2019-09-11 | 財團法人工業技術研究院 | 記憶體裝置及其復新資訊同步方法 |
| CN111857560B (zh) * | 2019-04-30 | 2024-06-28 | 伊姆西Ip控股有限责任公司 | 用于管理数据的方法、设备和计算机程序产品 |
| KR102808579B1 (ko) | 2019-10-16 | 2025-05-16 | 삼성전자주식회사 | 뉴럴 네트워크에서 연산을 수행하는 방법 및 장치 |
| CN112965816B (zh) | 2020-07-17 | 2023-06-02 | 华为技术有限公司 | 内存管理技术及计算机系统 |
| KR20240049940A (ko) * | 2022-10-11 | 2024-04-18 | 에스케이하이닉스 주식회사 | 리프레쉬 제어 회로를 포함하는 메모리 장치 및 그의 동작 방법 |
| CN119068939A (zh) * | 2023-05-25 | 2024-12-03 | 长鑫存储技术有限公司 | 存储器刷新方法及设备 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4006468A (en) * | 1973-08-06 | 1977-02-01 | Honeywell Information Systems, Inc. | Dynamic memory initializing apparatus |
| CN85101754B (zh) * | 1985-04-01 | 1988-07-13 | 株式会社日立制作所 | 计算机存储器之刷新电路 |
| JPH01146195A (ja) * | 1987-12-02 | 1989-06-08 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
| JPH01224851A (ja) * | 1988-03-03 | 1989-09-07 | Nec Corp | データ処理装置 |
| US5469559A (en) * | 1993-07-06 | 1995-11-21 | Dell Usa, L.P. | Method and apparatus for refreshing a selected portion of a dynamic random access memory |
| JPH09282873A (ja) | 1996-04-08 | 1997-10-31 | Ricoh Co Ltd | メモリ装置 |
| US6230235B1 (en) * | 1996-08-08 | 2001-05-08 | Apache Systems, Inc. | Address lookup DRAM aging |
| US5890198A (en) * | 1996-10-22 | 1999-03-30 | Micron Technology, Inc. | Intelligent refresh controller for dynamic memory devices |
| JP4246812B2 (ja) * | 1997-06-12 | 2009-04-02 | パナソニック株式会社 | 半導体回路及びその制御方法 |
| US6094705A (en) * | 1999-03-10 | 2000-07-25 | Picoturbo, Inc. | Method and system for selective DRAM refresh to reduce power consumption |
| US6385113B1 (en) * | 1999-04-30 | 2002-05-07 | Madrone Solutions, Inc | Method for operating an integrated circuit having a sleep mode |
| JP2001134484A (ja) * | 1999-11-01 | 2001-05-18 | Canon Aptex Inc | メモリ制御方法および装置 |
| US6650586B1 (en) * | 2000-06-28 | 2003-11-18 | Intel Corporation | Circuit and system for DRAM refresh with scoreboard methodology |
| JP4700223B2 (ja) * | 2001-05-18 | 2011-06-15 | 株式会社バッファロー | Dram装置およびdram装置のリフレッシュ方法 |
| JP2002352579A (ja) | 2001-05-25 | 2002-12-06 | Sony Corp | 情報記憶装置及び方法、メモリユニット、記録媒体、並びにプログラム |
| US6785793B2 (en) * | 2001-09-27 | 2004-08-31 | Intel Corporation | Method and apparatus for memory access scheduling to reduce memory access latency |
| US6741515B2 (en) * | 2002-06-18 | 2004-05-25 | Nanoamp Solutions, Inc. | DRAM with total self refresh and control circuit |
| US6842821B2 (en) * | 2002-12-02 | 2005-01-11 | Lsi Logic Corporation | DDR SDRAM memory controller with multiple dependency request architecture and intelligent requestor interface |
| WO2004095465A1 (ja) * | 2003-04-23 | 2004-11-04 | Fujitsu Limited | 半導体記憶装置 |
| KR100541824B1 (ko) | 2003-10-06 | 2006-01-10 | 삼성전자주식회사 | 반도체 집적회로에 채용하기 적합한 온도감지 회로 |
| WO2006038158A1 (en) * | 2004-10-04 | 2006-04-13 | Koninklijke Philips Electronics N.V. | Overdrive technique for display drivers |
| US7206244B2 (en) * | 2004-12-01 | 2007-04-17 | Freescale Semiconductor, Inc. | Temperature based DRAM refresh |
| US7342841B2 (en) * | 2004-12-21 | 2008-03-11 | Intel Corporation | Method, apparatus, and system for active refresh management |
| KR100655076B1 (ko) * | 2005-01-20 | 2006-12-08 | 삼성전자주식회사 | 반도체 메모리 장치의 내부 온도 데이터 출력 방법 및그에 따른 내부 온도 데이터 출력회로 |
| US7711897B1 (en) * | 2005-06-10 | 2010-05-04 | American Megatrends, Inc. | Method, system, apparatus, and computer-readable medium for improving disk array performance |
| US7565479B2 (en) * | 2005-08-04 | 2009-07-21 | Rambus Inc. | Memory with refresh cycle donation to accommodate low-retention-storage rows |
| CN100410949C (zh) * | 2006-09-20 | 2008-08-13 | 华为技术有限公司 | 数据库系统及管理数据库数据的方法 |
| TWI367486B (en) * | 2007-12-25 | 2012-07-01 | Ind Tech Res Inst | Memory device and refresh method thereof |
| US8095725B2 (en) * | 2007-12-31 | 2012-01-10 | Intel Corporation | Device, system, and method of memory allocation |
| JP2010176783A (ja) * | 2009-02-02 | 2010-08-12 | Elpida Memory Inc | 半導体装置とその制御方法と半導体装置とそれを制御するコントローラとを含む半導体システム |
| US9052902B2 (en) * | 2010-09-24 | 2015-06-09 | Intel Corporation | Techniques to transmit commands to a target device to reduce power consumption |
| US9116634B2 (en) * | 2011-06-10 | 2015-08-25 | International Business Machines Corporation | Configure storage class memory command |
| US8599595B1 (en) * | 2011-12-13 | 2013-12-03 | Michael C. Stephens, Jr. | Memory devices with serially connected signals for stacked arrangements |
| WO2013183155A1 (ja) * | 2012-06-07 | 2013-12-12 | 富士通株式会社 | 選択的にメモリのリフレッシュを行う制御装置 |
-
2013
- 2013-05-14 US US13/893,670 patent/US9336855B2/en active Active
-
2014
- 2014-05-09 CN CN201480027174.5A patent/CN105229743B/zh active Active
- 2014-05-09 WO PCT/US2014/037525 patent/WO2014186229A1/en not_active Ceased
- 2014-05-09 EP EP14727365.0A patent/EP2997576B1/en active Active
- 2014-05-09 JP JP2016513993A patent/JP6178499B2/ja active Active
- 2014-05-09 KR KR1020157035316A patent/KR101834625B1/ko not_active Expired - Fee Related
- 2014-05-14 TW TW103116992A patent/TWI525618B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI525618B (zh) | 2016-03-11 |
| EP2997576A1 (en) | 2016-03-23 |
| TW201510999A (zh) | 2015-03-16 |
| WO2014186229A1 (en) | 2014-11-20 |
| CN105229743A (zh) | 2016-01-06 |
| KR101834625B1 (ko) | 2018-04-13 |
| KR20160010518A (ko) | 2016-01-27 |
| US9336855B2 (en) | 2016-05-10 |
| JP2016524775A (ja) | 2016-08-18 |
| CN105229743B (zh) | 2018-02-02 |
| EP2997576B1 (en) | 2016-11-16 |
| US20140344513A1 (en) | 2014-11-20 |
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