JP5996838B2 - メモリリマップ情報を記憶する不揮発性メモリ - Google Patents
メモリリマップ情報を記憶する不揮発性メモリ Download PDFInfo
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- JP5996838B2 JP5996838B2 JP2010148353A JP2010148353A JP5996838B2 JP 5996838 B2 JP5996838 B2 JP 5996838B2 JP 2010148353 A JP2010148353 A JP 2010148353A JP 2010148353 A JP2010148353 A JP 2010148353A JP 5996838 B2 JP5996838 B2 JP 5996838B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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- General Engineering & Computer Science (AREA)
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- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
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Description
限定するものではない、また排他的なものではない実施形態を、添付図面につき説明するが、特に明示しない限り、図面において同一参照符号は同様の部分を示す。
Claims (17)
- メモリ装置に関するリマップ情報を記憶する内容参照可能メモリ(CAM)と、
前記CAMに記憶された前記リマップ情報が更新されたことに応答して、当該更新されたリマップ情報の少なくとも一部を記憶するように構成されたバックアップ用不揮発性メモリと、
を備え、
前記メモリ装置の読み出し/書き込みプロセスにおいて入力された読み出し/書き込みアドレスに応答して、前記CAM内のリマップ情報に基づき、前記読み出し/書き込みアドレスまたは、前記読み出し/書き込みアドレスに対応するリマップアドレスのいずれかが選択されると共に、当該選択された前記読み出し/書き込みアドレスまたは前記リマップアドレスを用いて読み出し/書き込みプロセスが実行されるように構成され、
前記更新されたリマップ情報の少なくとも一部の前記バックアップ用不揮発性メモリへの記憶は、前記選択された前記読み出し/書き込みアドレスまたは前記リマップアドレスを用いた読み出し/書き込みプロセスの実行中に、実行されるように構成されている、メモリ装置。 - 請求項1記載のメモリ装置において、
前記メモリ装置から読み出したデータを受信し、かつ、前記データに関連するビット誤り率および/またはビット誤り数を決定する誤り訂正コーディング(ECC)デコーダをさらに備え、
前記CAMは、前記ビット誤り率および/または前記ビット誤り数がエラー閾値に一致するか又は越えるかに、少なくとも部分的に基づいて、前記リマップ情報を記憶するよう構成されている、メモリ装置。 - 請求項1記載のメモリ装置において、前記リマップ情報は、1つ以上のリマップアドレステーブルを有する、メモリ装置。
- 請求項1記載のメモリ装置において、前記CAMと前記バックアップ用不揮発性メモリとは、互いに同期する、メモリ装置。
- メモリ装置から読み出したデータに関連するビット誤り率および/またはビット誤り数を決定するステップと、
前記メモリ装置に関するリマップ情報を、内容参照可能メモリ(CAM)に記憶するステップであって、前記リマップ情報は、前記ビット誤り率および/または前記ビット誤り数がエラー閾値に一致するかまたは越えるかに少なくとも部分的に基づく、ステップと、
前記CAMに記憶された前記リマップ情報が更新されたことに応答して、当該更新されたリマップ情報の少なくとも一部を、バックアップ用不揮発性メモリに記憶するステップと、
を含み、
前記更新されたリマップ情報の少なくとも一部を前記バックアップ用不揮発性メモリに記憶するステップは、入力された読み出し/書き込みアドレスに応答して前記CAM内のリマップ情報に基づき選択された前記読み出し/書き込みアドレスまたは前記読み出し/書き込みアドレスに対応するリマップアドレスのいずれかを用いて実行される前記メモリ装置の読み出し/書き込みプロセスの実行中に実行される、方法。 - 請求項5記載の方法において、前記リマップ情報は、1つ以上のリマップアドレスを含む、方法。
- 請求項6記載の方法において、前記メモリ装置は、メインメモリ部分およびスペアメモリ部分を有し、前記リマップアドレスは、前記スペアメモリ部分中のメモリ位置に対応する、方法。
- 請求項5記載の方法において、前記更新されたリマップ情報の少なくとも一部を前記バックアップ用不揮発性メモリに記憶するステップは、さらに、前記更新されたリマップ情報の少なくとも一部を前記バックアップ用不揮発性メモリの一部に書き込むステップを有し、前記バックアップ用不揮発性メモリの前記一部は前記更新されたリマップ情報の少なくとも一部と同じサイズである、方法。
- メモリ装置に対して読み出し/書き込みを行い、1つ以上のアプリケーションを実行するホストと、
前記メモリ装置から読み出したデータを受信し、前記データに関連するビット誤り率および/またはビット誤り数を決定する、誤り訂正コーディング(ECC)デコーダと、
前記ECCデコーダの出力信号に、少なくとも部分的に基づいて、前記メモリ装置のリマップアドレスを内容参照可能メモリ(CAM)に記憶するリマップコントローラと、を備え、
前記リマップコントローラは、前記CAMに記憶された前記リマップアドレスが更新されたことに応答して、当該更新されたリマップアドレスの少なくとも一部をバックアップ用不揮発性メモリへ記憶するように構成され、また、前記更新されたリマップアドレスの少なくとも一部の前記バックアップ用不揮発性メモリへの記憶は、入力された読み出し/書き込みアドレスに応答して前記CAM内のリマップアドレス情報に基づき選択された前記読み出し/書き込みアドレスまたは前記読み出し/書き込みアドレスに対応するリマップアドレスのいずれかを用いて実行される前記メモリ装置の読み出し/書き込みプロセスの実行中に、実行するように構成されている、システム。 - 請求項9記載のシステムにおいて、前記CAMは、読み出し/書き込みアドレスを受信し、前記読み出し/書き込みアドレスが前記CAM内に記憶された前記リマップアドレスに対応するか否かに、少なくとも部分的に応じた応答信号を出力するよう構成されている、システム。
- 請求項10記載のシステムにおいて、さらに、
前記メモリ装置で読み出し/書き込みを行うためのアドレスとして用いるべき、前記読み出し/書き込みアドレスまたは前記リマップアドレスのいずれかを選択する選択部を備え、この選択は、前記応答信号に少なくとも部分的に基づく、システム。 - 請求項9記載のシステムにおいて、前記メモリ装置は、メインメモリ部分およびスペアメモリ部分を有し、前記リマップアドレスは、前記スペアメモリ部分中のメモリ位置に対応する、システム。
- 請求項9記載のシステムにおいて、前記ビット誤り率および/または前記ビット誤り数は、前記メモリ装置の物理的劣化に少なくとも部分的に応じた値である、システム。
- 請求項1記載のメモリ装置において、前記更新されたリマップ情報の少なくとも一部を、前記バックアップ用不揮発性メモリに記憶することを、同期式で実行する、メモリ装置。
- 請求項1記載のメモリ装置において、前記バックアップ用不揮発性メモリは、前記更新されたリマップ情報の少なくとも一部をオン・ザ・フライで記憶するように構成されている、メモリ装置。
- 請求項5記載の方法において、前記更新されたリマップ情報の少なくとも一部を前記バックアップ用不揮発性メモリに記憶するステップは、オン・ザ・フライで実行される、方法。
- 請求項9記載のシステムにおいて、前記リマップコントローラは、前記更新されたリマップアドレスの少なくとも一部を前記バックアップ用不揮発性メモリへオン・ザ・フライで記憶するように構成されている、システム。
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US12/494,994 US8412987B2 (en) | 2009-06-30 | 2009-06-30 | Non-volatile memory to store memory remap information |
US12/494,994 | 2009-06-30 |
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JP2011040051A JP2011040051A (ja) | 2011-02-24 |
JP2011040051A5 JP2011040051A5 (ja) | 2013-08-01 |
JP5996838B2 true JP5996838B2 (ja) | 2016-09-21 |
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US (1) | US8412987B2 (ja) |
JP (1) | JP5996838B2 (ja) |
KR (1) | KR101647845B1 (ja) |
CN (1) | CN101937374B (ja) |
DE (1) | DE102010030745B4 (ja) |
TW (1) | TWI484330B (ja) |
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TW201126329A (en) | 2011-08-01 |
US20100332895A1 (en) | 2010-12-30 |
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TWI484330B (zh) | 2015-05-11 |
CN101937374B (zh) | 2015-07-01 |
DE102010030745A1 (de) | 2011-01-05 |
CN101937374A (zh) | 2011-01-05 |
US8412987B2 (en) | 2013-04-02 |
KR20110001882A (ko) | 2011-01-06 |
DE102010030745B4 (de) | 2015-02-19 |
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