JP5979495B2 - 半導体素子搭載用基板の製造方法 - Google Patents
半導体素子搭載用基板の製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 58
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000007747 plating Methods 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 description 41
- 239000002184 metal Substances 0.000 description 41
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 239000011347 resin Substances 0.000 description 11
- 229920005989 resin Polymers 0.000 description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 6
- 238000010030 laminating Methods 0.000 description 6
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 6
- 229910052753 mercury Inorganic materials 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 238000003475 lamination Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 239000012670 alkaline solution Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910000029 sodium carbonate Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000007921 spray Substances 0.000 description 3
- KYKQHSMYWLWROM-UHFFFAOYSA-N ac1l4yjn Chemical compound [Hg].[Hg] KYKQHSMYWLWROM-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/30—Imagewise removal using liquid means
- G03F7/32—Liquid compositions therefor, e.g. developers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
次に、本発明の半導体素子搭載用基板の製造方法の一実施例を図2に基づいて説明する。図2(a)に示すように、導電性を有する基板1として厚さ0.15mmのSUS430を用いて、基板1の両面に厚さ25μmのドライフィルムレジスト(旭化成イーマテリアルズ製:ADH−252)をラミネートしレジスト層10を形成した(裏面側は図示せず)。この時のラミネート条件は、ロール温度105℃、ロール圧力0.5MPa、送り速度2.5m/minで行なった。尚、ラミネートしたドライフィルムレジストはネガ型レジストであって、h線照射(感光波長:405nm)による露光が可能なドライフィルムレジストである。
次に、3層のドライフィルムレジストを使用した場合の実施例を図3に基づいて説明する。図3(a)に示すように、基板1として厚さ0.15mmのCu板を用いて、基板1の両面に厚さ25μmのドライフィルムレジスト(旭化成イーマテリアルズ製:ADH−252)をラミネートしレジスト層10を形成した(裏面側は図示せず)。この時のラミネート条件は、ロール温度105℃、ロール圧力0.5MPa、送り速度2.5m/minで行なった。尚、ラミネートしたドライフィルムレジストはネガ型レジストであって、h線照射(感光波長:405nm)による露光が可能なレジストである。
同じく、3層のドライフィルムレジストを使用した場合の実施例を図4に基づいて説明する。図4(a)に示すように、基板1として厚さ0.15mmのCu板を用いて、基板1の両面に厚さ25μmのドライフィルムレジスト(旭化成イーマテリアルズ製:AQ−2558)をラミネートしレジスト層10を形成した(裏面側は図示せず)。この時のラミネート条件は、ロール温度105℃、ロール圧力0.5MPa、送り速度2.5m/minで行なった。尚、ラミネートしたドライフィルムレジストはネガ型レジストであって、i線照射(感光波長:365nm)による露光が可能なレジストである。
2・・・めっき層(金属層、電極層)
3・・・バンドパスフィルタ
4・・・光源
10,11,12・・・レジスト層(レジストマスク)
20,21・・・マスク
30,31,32・・・未露光部分
40,41,42・・・開口部
Claims (4)
- 導電性を有する基板の表面に端子等となるめっき層を備えた半導体素子搭載用基板の製造方法であって、メインの感光波長が異なる2種類のドライフィルムレジストを用いて前記基板の表面にこの2種類のドライフィルムレジストで複数層のレジスト層を形成する工程と、前記複数層のレジスト層の上から第1の露光用マスクを用いて前記複数層のレジスト層の中から特定のレジスト層のみを第1のパターンに感光する第1の露光工程と、前記複数層のレジスト層の上から第2の露光用マスクを用いて前記複数層のレジスト層の中から別のレジスト層を第2のパターンに感光する第2の露光工程と、前記複数層のレジスト層の未露光部分を除去して前記基板の表面を部分的に露出させて開口部を有するレジストマスクを形成する現像工程と、前記基板の表面が露出している部分に所望のめっきを施してめっき層を形成する工程と、前記レジストマスクを除去する工程を順次経ることを特徴とする半導体素子搭載用基板の製造方法。
- 前記第1の露光用マスクと前記第2の露光用マスクは描かれているパターンが異なり、この描かれているパターンが異なる第1と第2の露光用マスクを用いて前記2種類のドライフィルムレジストからなる前記複数層のレジスト層を露光し現像することによって、前記基板表面が露出しているめっき用のレジストマスクの前記開口部の断面に段差が形成されることを特徴とする請求項1に記載の半導体素子搭載用基板の製造方法。
- 露光の際に、バンドパスフィルタを用いて所定の波長の紫外線を選択して前記第1の露光工程または前記第2の露光工程を行うことを特徴とする請求項1または請求項2に記載の半導体素子搭載用基板の製造方法。
- 露光の際に、選ばれたレジスト層のみを露光できる波長の紫外線を使用して前記第1の露光工程または前記第2の露光工程を行うことを特徴とする請求項1または請求項2に記載の半導体素子搭載用基板の製造方法。
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JP2013056466A JP5979495B2 (ja) | 2013-03-19 | 2013-03-19 | 半導体素子搭載用基板の製造方法 |
CN201480013843.3A CN105190870B (zh) | 2013-03-19 | 2014-03-11 | 半导体元件搭载用基板的制造方法 |
US14/777,834 US10204801B2 (en) | 2013-03-19 | 2014-03-11 | Method for producing substrate for semiconductor element mounting |
KR1020157019303A KR102162913B1 (ko) | 2013-03-19 | 2014-03-11 | 반도체 소자 탑재용 기판의 제조방법 |
PCT/JP2014/056304 WO2014148308A1 (ja) | 2013-03-19 | 2014-03-11 | 半導体素子搭載用基板の製造方法 |
TW103109919A TWI588947B (zh) | 2013-03-19 | 2014-03-17 | A method of manufacturing a semiconductor element mounting substrate |
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JP5979495B2 true JP5979495B2 (ja) | 2016-08-24 |
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JP (1) | JP5979495B2 (ja) |
KR (1) | KR102162913B1 (ja) |
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JP5979495B2 (ja) | 2013-03-19 | 2016-08-24 | Shマテリアル株式会社 | 半導体素子搭載用基板の製造方法 |
JP6681165B2 (ja) * | 2014-12-27 | 2020-04-15 | マクセルホールディングス株式会社 | 半導体装置用基板、半導体装置用基板の製造方法、及び半導体装置 |
CN105404418B (zh) * | 2015-11-03 | 2018-09-04 | 京东方科技集团股份有限公司 | 触控屏及其制备方法、显示面板和显示装置 |
JP6327427B1 (ja) * | 2017-06-22 | 2018-05-23 | 大口マテリアル株式会社 | 半導体素子搭載用基板及び半導体装置、並びに半導体素子搭載用基板の製造方法 |
JP6867080B2 (ja) * | 2017-06-30 | 2021-04-28 | 大口マテリアル株式会社 | 半導体素子搭載用基板及びその製造方法 |
JP6849858B2 (ja) | 2017-09-18 | 2021-03-31 | グーグル エルエルシーGoogle LLC | 2段階成膜プロセスにおける接合抵抗の変動の低減 |
US11764062B2 (en) * | 2017-11-13 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor structure |
JP7059139B2 (ja) * | 2018-07-13 | 2022-04-25 | 大口マテリアル株式会社 | 半導体素子搭載用基板の製造方法 |
CN113140448B (zh) * | 2020-01-16 | 2022-10-28 | 芯恩(青岛)集成电路有限公司 | 一种半导体结构及其制作方法 |
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JP4015756B2 (ja) * | 1998-06-30 | 2007-11-28 | ユーディナデバイス株式会社 | 半導体装置の製造方法 |
CN1110065C (zh) * | 2000-04-05 | 2003-05-28 | 信息产业部电子第十三研究所 | 半导体器件栅帽与栅足自对准的t形栅加工方法 |
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JP4508064B2 (ja) | 2005-09-30 | 2010-07-21 | 住友金属鉱山株式会社 | 半導体装置用配線基板の製造方法 |
US7579137B2 (en) * | 2005-12-24 | 2009-08-25 | International Business Machines Corporation | Method for fabricating dual damascene structures |
US7476980B2 (en) * | 2006-06-27 | 2009-01-13 | Infineon Technologies Ag | Die configurations and methods of manufacture |
US8536031B2 (en) * | 2010-02-19 | 2013-09-17 | International Business Machines Corporation | Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme |
JP5626785B2 (ja) * | 2010-09-27 | 2014-11-19 | Shマテリアル株式会社 | 半導体素子搭載用リードフレームおよびその製造方法 |
US8455312B2 (en) * | 2011-09-12 | 2013-06-04 | Cindy X. Qiu | Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits |
JP5979495B2 (ja) | 2013-03-19 | 2016-08-24 | Shマテリアル株式会社 | 半導体素子搭載用基板の製造方法 |
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Publication number | Publication date |
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CN105190870A (zh) | 2015-12-23 |
US10204801B2 (en) | 2019-02-12 |
WO2014148308A1 (ja) | 2014-09-25 |
JP2014183172A (ja) | 2014-09-29 |
TWI588947B (zh) | 2017-06-21 |
US20160300732A1 (en) | 2016-10-13 |
TW201508869A (zh) | 2015-03-01 |
CN105190870B (zh) | 2018-02-27 |
KR102162913B1 (ko) | 2020-10-07 |
KR20150135203A (ko) | 2015-12-02 |
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