WO2014148308A1 - 半導体素子搭載用基板の製造方法 - Google Patents
半導体素子搭載用基板の製造方法 Download PDFInfo
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- WO2014148308A1 WO2014148308A1 PCT/JP2014/056304 JP2014056304W WO2014148308A1 WO 2014148308 A1 WO2014148308 A1 WO 2014148308A1 JP 2014056304 W JP2014056304 W JP 2014056304W WO 2014148308 A1 WO2014148308 A1 WO 2014148308A1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/30—Imagewise removal using liquid means
- G03F7/32—Liquid compositions therefor, e.g. developers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a method for manufacturing a substrate for mounting a semiconductor element provided with a plating layer serving as a terminal on the surface of a conductive substrate such as a metal plate.
- a resist mask is formed in a predetermined pattern on one side of a substrate having conductivity, and a conductive metal is plated on the substrate exposed from the resist mask to connect the metal layer for mounting a semiconductor element to the outside.
- An electrode layer is formed and a resist mask is removed to form a semiconductor element mounting substrate.
- the semiconductor element is mounted on the metal layer portion of the semiconductor element mounting substrate, and the semiconductor element and the electrode layer are wire bonded.
- Such a semiconductor device has been conventionally formed of a metal base having a thickness of 0.1 to 0.25 mm, which is called a lead frame. However, it is about 0.01 to 0.08 mm instead of the conventional metal base. Thinning is realized by using a metal layer and an electrode layer formed by plating with a thickness. In this case, the base material used for the production is removed, but at that time, it is important that the metal layer or the electrode layer formed by plating is firmly adhered to the sealing resin and remains on the resin side.
- Patent Document 1 a conductive element is electrodeposited (plated) beyond the formed resist mask to obtain a semiconductor element mounting substrate having a protruding portion on the periphery of the upper end of the metal layer and the electrode layer. It is described that the protruding portions of the metal layer and the electrode layer bite into the resin during sealing so as to surely remain on the resin side.
- Patent Document 2 describes that a resist mask is formed into a trapezoid using scattered ultraviolet light to form a metal layer or an electrode layer in a trapezoidal shape with a wide cross section on the top side.
- the metal layer and the electrode layer to be formed are formed by overhanging from the resist mask and plating.
- the amount of overhang of the metal layer and electrode layer is proportional to the plating thickness beyond the resist mask.
- the variation in the plating thickness also increases, so that the length of the metal layer and the electrode layer also increases in the same manner. Therefore, when setting the dimensions and intervals of the metal layer and the electrode layer of the semiconductor mounting substrate, it is necessary to consider the variation in the length of the metal, and it is difficult to reduce the dimensions and the interval of the metal layer and the electrode layer. .
- the method of forming the cross-sectional shape of the opening portion of the resist mask into a trapezoid having a wide top side using scattered ultraviolet light shown in Patent Document 2 is effective if the thickness of the resist layer to be used is up to about 25 ⁇ m. . Therefore, it can be said that the method disclosed in Patent Document 2 is an effective method if the thickness of the formed metal layer or electrode layer is up to about 20 ⁇ m.
- the ultraviolet light is absorbed by the resist and the light attenuates as it goes in the direction of the metal plate. (Ie, a rectangle) or a smaller trapezoidal shape with the long side of the metal plate side. Therefore, the shape of the metal layer or electrode layer formed by plating in the opening does not form a trapezoid having a wide top side, and the adhesion between the metal layer or electrode layer and the resin is lowered.
- the cross section of the metal layer and the electrode layer is formed in a trapezoidal shape with a wide top side, or has a rough contour, or a trapezoidal shape with a wide top side. In addition, it is effective to form it with an uneven contour.
- the thickness of the metal layer and the electrode layer by increasing the thickness of the resist layer.
- a resist mask that will form a trapezoidal shape with a wide cross-section on the top side and a plating layer with an uneven contour is formed. It is more preferable to form a plating layer having a certain contour.
- the semiconductor element mounting substrate although depending on the shape of the trapezoid and the shape of the unevenness, it is basically possible to manufacture the semiconductor element mounting substrate so that the thickness of the metal layer or electrode layer formed by the plating layer is about 30 to 100 ⁇ m. is necessary.
- the method for manufacturing a substrate for mounting a semiconductor element according to the present invention has been made to solve the above-described problems.
- the metal layer or electrode layer is thick and the cross-sectional shape of the metal layer or electrode layer is formed with irregularities, whereby the adhesion between the metal layer or electrode layer and the resin is improved. It is possible to provide a semiconductor element mounting substrate that can be further enhanced.
- a method for manufacturing a substrate for mounting a semiconductor element having a plating layer serving as a terminal on the surface of a conductive substrate has different main photosensitive wavelengths.
- Forming a plurality of resist layers on the surface of the substrate with one dry film resist and a second dry film resist, and using the first exposure mask from above the plurality of resist layers A first exposure step of selectively exposing at least one resist layer made of the first dry film resist among the layers to a first pattern; and a second exposure step from above the plurality of resist layers.
- the first exposure mask and the second exposure mask have different drawn patterns.
- a resist mask for plating in which the substrate surface is exposed is created.
- a step is formed in the cross section of the opening of the resist mask because the patterns drawn on the first exposure mask and the second exposure mask are different.
- the first exposure step or the second exposure step it is preferable to perform the first exposure step or the second exposure step by selecting ultraviolet rays having a predetermined wavelength using a bandpass filter during exposure.
- the first exposure step or the second exposure step it is preferable to perform the first exposure step or the second exposure step using ultraviolet rays having a wavelength capable of exposing only a selected resist layer during exposure.
- a conductive material which is a semiconductor substrate material, with two or three layers, and exposed with single-line ultraviolet light that exposes the target layer through an exposure mask. Therefore, patterning exposure is performed only on the target layer in the laminated dry film resist that has been bonded, and this is applied to each layer to develop the dry film resist.
- An opening having a concavo-convex shape can be produced. After that, by electroplating plating, the plating metal can be formed in the same shape as the opening using the opening of the dry film resist as a mold, so that the cross-sectional shape of the metal layer or electrode layer has irregularities.
- a semiconductor element mounting substrate can be provided in which the adhesion between the metal layer or electrode layer and the resin can be improved.
- FIG. 4B is a cross-sectional view when a desired plating is performed
- FIGS. 5B and 5C illustrate a desired plating by forming a three-layer resist mask using two types of dry film resists having different photosensitive wavelengths. It is sectional drawing when giving.
- (A)-(e) shows the process in each process along the manufacturing flow of the manufacturing method in case the resist layer shown in Example 1 is two layers with sectional drawing.
- (A)-(e) shows the process in each process along the manufacturing flow of the manufacturing method in case the resist layer shown in Example 2 is 3 layers with sectional drawing.
- (A)-(e) shows the process in each process along the manufacturing flow of the manufacturing method in case the resist layer shown in Example 3 is 3 layers with sectional drawing.
- two or three resist layers are formed on the surface of a conductive substrate using dry film resists having different photosensitive wavelengths. Although it is possible to form four or more layers, two or three layers are preferable because the cost increases.
- the first exposure mask is used to perform the first exposure with the ultraviolet light that the target resist layer is exposed to, and then the second exposure mask is used to expose the other resist layer to the ultraviolet light that is exposed to light. Then, the second exposure is performed, and development is performed to provide openings in the plurality of resist layers to form a resist mask. At this time, the exposure mask is formed so that irregularities are formed by a plurality of resist layers on the outline of the opening section.
- the resist mask in which the opening is formed is used as a plating mask.
- the resist mask is peeled off to mount a semiconductor element. A substrate can be obtained.
- a dry film resist having a different main photosensitive wavelength for example, DFR for DI (h line), general-purpose DFR (main wavelength i line) as shown in FIG. ) Etc.
- a dry film resist having a different main photosensitive wavelength for example, DFR for DI (h line), general-purpose DFR (main wavelength i line) as shown in FIG. ) Etc.
- DFR for DI h line
- DFR main wavelength i line
- Etc. main photosensitive wavelength
- Example 1 Next, an experiment conducted by the present inventor will be described with reference to FIG. 2 as an embodiment of the method for manufacturing a semiconductor element mounting substrate of the present invention.
- a 25 ⁇ m thick dry film resist (Asahi Kasei E-materials: ADH-252) is laminated on both sides of a 0.15 mm thick SUS430 as a conductive substrate 1 and a resist layer 10 was formed (the back side was not shown).
- Lamination conditions at this time were performed at a roll temperature of 105 ° C., a roll pressure of 0.5 MPa, and a feed rate of 2.5 m / min.
- the laminated dry film resist is a negative resist, and is a dry film resist that can be exposed by h-ray irradiation (photosensitive wavelength: 405 nm).
- a dry film resist (AQ-5038, manufactured by Asahi Kasei E-Materials) having a thickness of 50 ⁇ m different from that of the resist layer 10 is superimposed on the resist layer 10 on one side (front side) under the same conditions as described above.
- the upper resist layer 11 was formed.
- this dry film resist is also a negative resist, it is a dry film resist that can be exposed by i-line irradiation (photosensitive wavelength: 365 nm).
- resist layers 10 and 11 are formed on the front side of the substrate 1 by two types of dry film resists having different photosensitive wavelengths, and on the back side (not shown), The same resist layer as the lower layer on the surface side is formed.
- an exposure mask 20 in which a predetermined pattern is formed is put on the resist layers 10 and 11 on the surface side, and the mask 20 and the light source 4 for exposure are formed.
- a 405 nm bandpass filter 3 was set between them.
- a mercury lamp (Oak: short arc lamp) having a main wavelength of i-line and including h-line and g-line as the light source 4, so that the wavelength of the lower resist layer 10 on the surface side is changed.
- the resist layer 10 was directly exposed and cured by the same light source on the back side to be cured with a pattern drawn on the mask 20 by 405 nm ultraviolet light (the back side was not shown). Exposure dose at this time, 18 mJ / cm 2 surface is at a wavelength of 405nm detector, the back side was 80 mJ / cm 2 at a wavelength of 365nm detector.
- the surface side is exposed by h-ray irradiation by the band-pass filter 3 of 405 nm, and the upper resist layer 11 is in an unexposed state.
- the back side is a resist mask whose entire surface is cured by exposure with mixed lines.
- a mask 21 in which a predetermined pattern different from the mask 20 for exposure is formed is put on the resist layers 10 and 11 on the surface side, and the light source 4 (cross-link) is covered.
- the resist layer 11 was exposed to light by the pattern of the mask 21 for exposure and cured.
- the mask 20 and the mask 21 are hardened on the unexposed portion 30 of the resist layer 10 previously exposed by setting the planar area to be cured to a smaller exposure area in the mask 21 to be exposed later. There is no.
- the exposure dose at this time was 70 mJ / cm 2 with a detector having a wavelength of 365 nm.
- the resist layer 11 on the upper surface side is formed in a predetermined pattern, and one resist mask in which the opening 41 is formed in the unexposed portion 31 is formed.
- the opening portion 40 is formed in the unexposed portion 30 in the resist layer 10 in the lower layer, and becomes a part 10 of the resist mask, and the substrate 1 is exposed.
- This development process was performed by processing a 1% sodium carbonate solution at a liquid temperature of 30 ° C. and a spray pressure of 0.08 MPa for about 80 seconds.
- the opening 40 and the opening 41 form an opening having a substantially T-shaped cross section.
- the openings 40 and 41 from which the substrate 1 is exposed are subjected to surface activation treatment by surface oxide film removal and general plating pretreatment, and then nickel plating is performed. Then, a plating layer (metal layer, electrode layer) 2 having a thickness of 45 ⁇ m was formed.
- an ultraviolet LED lamp having a specific wavelength without using a mercury lamp as a light source, it is possible to expose a desired resist layer without using a bandpass filter.
- the plating layer 2 to be formed may be formed by laminating a plurality of platings, selecting plating with gold, palladium, nickel, copper, cobalt, etc. and their alloys as necessary and sequentially laminating them. You can also.
- Example 2 Next, an experiment conducted by the inventor using a three-layer dry film resist will be described as Example 2 with reference to FIG.
- a 0.15 mm thick Cu plate is used as the substrate 1 and a 25 ⁇ m thick dry film resist (Asahi Kasei E-Materials: ADH-252) is laminated on both sides of the substrate 1.
- a resist layer 10 was formed (the back side is not shown).
- Lamination conditions at this time were performed at a roll temperature of 105 ° C., a roll pressure of 0.5 MPa, and a feed rate of 2.5 m / min.
- the laminated dry film resist is a negative resist and can be exposed by h-ray irradiation (photosensitive wavelength: 405 nm).
- a 25 ⁇ m thick dry film resist (AQ-2558, manufactured by Asahi Kasei E-materials) having a photosensitive wavelength different from that of the resist layer 10 is superimposed on the resist layer 10 on one side (front side) under the same conditions as described above. Then, a second resist layer 11 was formed.
- this dry film resist is also a negative resist, it is a resist that can be exposed by i-line irradiation (photosensitive wavelength: 365 nm).
- the same dry film resist (Asahi Kasei E-Materials: ADH-252) as that of the resist layer 10 is laminated under the same conditions as above, overlaid on the resist layers 10 and 11 on one side (front side). An upper resist layer 12 was formed.
- three resist layers 10, 11, and 12 are sequentially formed on the front surface side of the substrate 1 by two types of dry films having different photosensitive wavelengths, and the back surface side (FIG. (Not shown), the same resist layer as the lowermost layer on the surface side is formed.
- an exposure mask 20 in which a predetermined pattern is formed is put on the resist layers 10, 11 and 12 on the surface side, and the mask 20 and the light source 4 for exposure are covered.
- 405 nm band pass filter 3 was set between the two.
- Exposure dose at this time 30 mJ / cm 2 surface is at a wavelength of 405nm detector, the back side was 80 mJ / cm 2 at a wavelength of 365nm detector.
- the surface side is exposed by h-ray irradiation by the band-pass filter 3 of 405 nm, and the intermediate resist layer 11 sandwiched between the uppermost layer and the lowermost layer is in an unexposed state.
- the back side is a resist layer whose entire surface has been cured by exposure with mixed lines.
- a mask 21 in which a predetermined pattern different from the mask 20 for exposure is formed on the resist layers 10, 11, 12 on the surface side is covered with the light source 4.
- the resist layer 11 was exposed to light with a pattern of the mask 21 for exposure and cured by performing exposure with a (mercury mercury lamp).
- the mask 20 and the mask 21 are cured so that the planar area to be cured is smaller in the mask 21 to be exposed later, so that the unexposed portion 30 and the resist layer 12 of the resist layer 10 exposed earlier.
- the unexposed portion 32 is not cured.
- the exposure dose at this time was 70 mJ / cm 2 with a detector having a wavelength of 365 nm.
- the uppermost resist layer 12 and the lowermost resist layer 10 on the surface side are formed in a predetermined pattern, and an opening is formed in the unexposed portion 32. It becomes a part 12 of the resist mask in which 42 is formed, and a part 10 of the resist mask in which the opening 40 is formed in the unexposed part 30. Further, the intermediate resist layer 11 sandwiched between the uppermost layer and the lowermost layer is similarly formed with an opening 41 in the unexposed portion 31 to become a part 11 of the resist mask, and the substrate 1 is exposed.
- This development process was performed by processing a 1% sodium carbonate solution at a liquid temperature of 30 ° C. and a spray pressure of 0.08 MPa for about 120 seconds.
- the opening 40, the opening 41 and the opening 42 form a cross-sectional shape of a resist mask having a concave shape on both sides.
- the openings 40, 41, and 42 where the substrate 1 is exposed are subjected to surface activation treatment by surface oxide film removal and general plating pretreatment, and then nickel.
- Plating was performed to form a plating layer (metal layer, electrode layer) 2 having a thickness of 70 ⁇ m.
- the resist masks 10, 11, and 12 formed on both surfaces of the substrate 1 are all peeled off with an alkaline solution to form a plating layer (metal layer, electrode layer) 2 having a cross-sectional shape and a convex shape on both sides.
- the obtained semiconductor element mounting substrate was obtained.
- the plating layer 2 to be formed may be formed by laminating a plurality of platings, selecting plating with gold, palladium, nickel, copper, cobalt, etc. and their alloys as necessary, and laminating them sequentially. You can also.
- Example 3 Another experiment conducted by the inventor using the same three-layer dry film resist will be described as Example 3 with reference to FIG.
- a 0.15 mm thick Cu plate is used as the substrate 1, and a 25 ⁇ m thick dry film resist (AQ-2558 made by Asahi Kasei E-materials) is laminated on both sides of the substrate 1.
- a resist layer 10 was formed (the back side is not shown).
- Lamination conditions at this time were performed at a roll temperature of 105 ° C., a roll pressure of 0.5 MPa, and a feed rate of 2.5 m / min.
- the laminated dry film resist is a negative resist and can be exposed by i-ray irradiation (photosensitive wavelength: 365 nm).
- a dry film resist (Asahi Kasei E-Materials: ADH-252) having a thickness of 25 ⁇ m different from that of the resist layer 10 on the one surface side (surface side) is subjected to the same conditions as described above.
- the upper resist layer 11 was formed.
- this dry film resist is also a negative resist, it is a resist that can be exposed by h-ray irradiation (photosensitive wavelength: 405 nm).
- the same dry film resist (AQ-2558 manufactured by Asahi Kasei E-Materials) as the resist layer 10 is laminated under the same conditions as above, overlaid on the resist layers 10 and 11 on one side (front side). An upper resist layer 12 was formed.
- three resist layers 10, 11, and 12 are sequentially formed on the front surface side of the substrate 1 by two types of dry films having different photosensitive wavelengths, and the back surface side (FIG. (Not shown), the same resist layer as the lowermost layer on the surface side is formed.
- an exposure mask 20 in which a predetermined pattern is formed is put on the resist layers 10, 11 and 12 on the surface side, and the mask 20 and the exposure light source 4 are covered.
- 405 nm band pass filter 3 was set between the two.
- Exposure dose at this time 16 mJ / cm 2 surface is at a wavelength of 405nm detector, the back side was 80 mJ / cm 2 at a wavelength of 365nm detector.
- the surface side is exposed by h-ray irradiation by the band-pass filter 3 of 405 nm, and the uppermost resist layer 12 and the lowermost resist layer 10 are in an unexposed state.
- the back side is a resist layer whose entire surface has been cured by exposure with mixed lines.
- a mask 21 in which a predetermined pattern different from the mask 20 for exposure is formed on the resist layers 10, 11 and 12 on the surface side, and the light source 4
- a (mercury mercury lamp) lamp By performing exposure with a (mercury mercury lamp), the uppermost resist layer 12 and the lowermost resist layer 10 were exposed and cured with the pattern of the mask 21 for exposure.
- the mask 20 and the mask 21 are cured so that the unexposed portion 31 of the resist layer 11 previously exposed is cured by setting the planar area to be cured to be a smaller exposure area for the mask 21 to be exposed later. There is no.
- the exposure dose at this time was 100 mJ / cm 2 with a detector having a wavelength of 365 nm.
- the uppermost resist layer 12 and the lowermost resist layer 10 on the surface side are formed in a predetermined pattern, and an opening is formed in the unexposed portion 32.
- 42 becomes a part 12 of the resist mask in which the opening 42 is formed, and becomes a part 10 of the resist mask in which the opening 40 is formed in the unexposed portion 30, and an intermediate resist layer 11 sandwiched between the uppermost layer and the lowermost layer.
- an opening 41 is formed in the unexposed portion 31 to become a part 11 of the resist mask, and the substrate 1 is exposed.
- This development process was performed by processing a 1% sodium carbonate solution at a liquid temperature of 30 ° C. and a spray pressure of 0.08 MPa for about 120 seconds.
- the opening 40, the opening 41 and the opening 42 form a cross-sectional shape of a resist mask having a concave shape on both sides.
- the openings 40, 41, and 42 where the substrate 1 is exposed are subjected to surface activation treatment by surface oxide film removal and general plating pretreatment, and then nickel.
- Plating was performed to form a plating layer (metal layer, electrode layer) 2 having a thickness of 70 ⁇ m.
- the resist masks 10, 11, and 12 formed on both surfaces of the substrate 1 are all peeled off with an alkaline solution to form a plating layer (metal layer, electrode layer) 2 having a cross-sectional shape and a concave shape on both sides.
- the obtained semiconductor element mounting substrate was obtained.
- the plating layer 2 to be formed may be formed by laminating a plurality of platings, selecting plating with gold, palladium, nickel, copper, cobalt, etc. and their alloys as necessary, and laminating them sequentially. You can also.
Abstract
Description
次に、本発明者の行った一実験を本発明の半導体素子搭載用基板の製造方法の一実施例として図2に基づいて説明する。図2(a)に示すように、導電性を有する基板1として厚さ0.15mmのSUS430の両面に厚さ25μmのドライフィルムレジスト(旭化成イーマテリアルズ製:ADH-252)をラミネートしレジスト層10を形成した(裏面側は図示せず)。この時のラミネート条件は、ロール温度105℃、ロール圧力0.5MPa、送り速度2.5m/minで行なった。尚、ラミネートしたドライフィルムレジストはネガ型レジストであって、h線照射(感光波長:405nm)による露光が可能なドライフィルムレジストである。
次に、本発明者が行った、3層のドライフィルムレジストを使用した場合の実験を実施例2として図3に基づいて説明する。図3(a)に示すように、基板1として厚さ0.15mmのCu板を用いて、基板1の両面に厚さ25μmのドライフィルムレジスト(旭化成イーマテリアルズ製:ADH-252)をラミネートしレジスト層10を形成した(裏面側は図示せず)。この時のラミネート条件は、ロール温度105℃、ロール圧力0.5MPa、送り速度2.5m/minで行なった。尚、ラミネートしたドライフィルムレジストはネガ型レジストであって、h線照射(感光波長:405nm)による露光が可能なレジストである。
本発明者が行った同じく3層のドライフィルムレジストを使用した場合の別の実験を実施例3として図4に基づいて説明する。図4(a)に示すように、基板1として厚さ0.15mmのCu板を用いて、基板1の両面に厚さ25μmのドライフィルムレジスト(旭化成イーマテリアルズ製:AQ-2558)をラミネートしレジスト層10を形成した(裏面側は図示せず)。この時のラミネート条件は、ロール温度105℃、ロール圧力0.5MPa、送り速度2.5m/minで行なった。尚、ラミネートしたドライフィルムレジストはネガ型レジストであって、i線照射(感光波長:365nm)による露光が可能なレジストである。
2・・・めっき層(金属層、電極層)
3・・・バンドパスフィルタ
4・・・光源
10,11,12・・・レジスト層(レジストマスク)
20,21・・・露光用マスク
30,31,32・・・未露光部分
40,41,42・・・開口部
Claims (8)
- 導電性を有する基板の表面に端子等となるめっき層を備えた半導体素子搭載用基板の製造方法であって、メインの感光波長が異なる第1のドライフィルムレジストと第2のドライフィルムレジストとで前記基板の表面に複数のレジスト層を形成する工程と、前記複数のレジスト層の上から第1の露光用マスクを用いて前記複数のレジスト層の中から前記第1のドライフィルムレジストでできた少なくとも1つのレジスト層を選択的に第1のパターンに感光する第1の露光工程と、前記複数のレジスト層の上から第2の露光用マスクを用いて前記複数のレジスト層の中から前記第2のドライフィルムレジストでできた少なくとも1つのレジスト層を第2のパターンに感光する第2の露光工程と、前記複数のレジスト層の未露光部分を除去して前記基板の表面を部分的に露出させて開口部を有するレジストマスクを形成する現像工程と、前記基板の表面が露出している部分にめっきを施してめっき層を形成する工程と、前記レジストマスクを除去する工程を順次経ることを特徴とする半導体素子搭載用基板の製造方法。
- 前記第1の露光用マスクと前記第2の露光用マスクは描かれているパターンが異なり、この描かれているパターンが異なる第1と第2の露光用マスクを用いて前記第1のドライフィルムレジストと前記第2のドライフィルムレジストからなる前記複数のレジスト層を露光し現像することによって、前記基板表面が露出しているめっき用のレジストマスクの前記開口部の断面に段差が形成されることを特徴とする請求項1に記載の半導体素子搭載用基板の製造方法。
- バンドパスフィルタを用いて所定の波長の紫外線を選択して前記第1の露光工程または前記第2の露光工程を行うことを特徴とする請求項1または請求項2に記載半導体素子搭載用基板の製造方法。
- 選ばれたレジスト層のみを露光できる波長の紫外線を使用して前記第1の露光工程または前記第2の露光工程を行うことを特徴とする請求項1または請求項2に記載半導体素子搭載用基板の製造方法。
- 前記第2の露光用マスクは前記第1の露光用マスクより露光させる面積が小さいことを特徴とする請求項2に記載の半導体素子搭載用基板の製造方法。
- 前記基板の表面に複数のレジスト層を形成する工程は、前記第1のドライフィルムレジストで下側のレジスト層を形成し前記2のドライフィルムレジストで上側のレジスト層を形成して2層構造を形成する工程を含み、前記第1の露光工程では前記下側のレジスト層が露光され、前記第2の露光工程では前記上側のレジスト層が露光されることにより、前記現像工程で形成した、基板表面が露出しているめっき用のレジストマスクの前記開口部の断面がT字状であることを特徴とする、請求項5に記載の半導体素子搭載用基板の製造方法。
- 前記基板の表面に複数のレジスト層を形成する工程は、前記第1のドライフィルムレジストで下側のレジスト層を形成し前記2のドライフィルムレジストで中間のレジスト層を形成し前記第1のドライフィルムレジストで上側のレジスト層を形成することで3層構造を形成する工程を含み、前記第1の露光工程では前記下側のレジスト層と前記上側のレジスト層が露光され、前記第2の露光工程では前記中間のレジスト層が露光されることにより、前記現像工程で形成した、基板表面が露出しているめっき用のレジストマスクの前記開口部の断面が両側に凸形状をもつことを特徴とする、請求項5に記載の半導体素子搭載用基板の製造方法。
- 前記基板の表面に複数のレジスト層を形成する工程は、前記第2のドライフィルムレジストで下側のレジスト層を形成し前記1のドライフィルムレジストで中間のレジスト層を形成し前記第2のドライフィルムレジストで上側のレジスト層を形成することで3層構造を形成する工程を含み、前記第1の露光工程では前記中間のレジスト層が露光され、前記第2の露光工程では前記下側のレジスト層と前記上側のレジスト層とが露光されることにより、前記現像工程で形成した、基板表面が露出しているめっき用のレジストマスクの前記開口部の断面が両側に凹形状をもつことを特徴とする、請求項5に記載の半導体素子搭載用基板の製造方法。
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JP6327427B1 (ja) * | 2017-06-22 | 2018-05-23 | 大口マテリアル株式会社 | 半導体素子搭載用基板及び半導体装置、並びに半導体素子搭載用基板の製造方法 |
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CN117998973A (zh) | 2017-09-18 | 2024-05-07 | 谷歌有限责任公司 | 制造约瑟夫森结的方法 |
US11764062B2 (en) * | 2017-11-13 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor structure |
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CN113140448B (zh) * | 2020-01-16 | 2022-10-28 | 芯恩(青岛)集成电路有限公司 | 一种半导体结构及其制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH065631A (ja) * | 1992-06-23 | 1994-01-14 | Nec Corp | 金属電極の形成方法 |
JP2000022131A (ja) * | 1998-06-30 | 2000-01-21 | Fujitsu Quantum Devices Kk | 半導体装置およびその製造方法 |
JP2002009196A (ja) * | 2000-06-20 | 2002-01-11 | Kyushu Hitachi Maxell Ltd | 半導体装置の製造方法 |
US20070298603A1 (en) * | 2006-06-27 | 2007-12-27 | Kenneth Rebibis | Die configurations and methods of manufacture |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1110065C (zh) * | 2000-04-05 | 2003-05-28 | 信息产业部电子第十三研究所 | 半导体器件栅帽与栅足自对准的t形栅加工方法 |
JP4052915B2 (ja) * | 2002-09-26 | 2008-02-27 | 三洋電機株式会社 | 回路装置の製造方法 |
JP4508064B2 (ja) | 2005-09-30 | 2010-07-21 | 住友金属鉱山株式会社 | 半導体装置用配線基板の製造方法 |
US7579137B2 (en) * | 2005-12-24 | 2009-08-25 | International Business Machines Corporation | Method for fabricating dual damascene structures |
US8536031B2 (en) * | 2010-02-19 | 2013-09-17 | International Business Machines Corporation | Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme |
JP5626785B2 (ja) * | 2010-09-27 | 2014-11-19 | Shマテリアル株式会社 | 半導体素子搭載用リードフレームおよびその製造方法 |
US8455312B2 (en) * | 2011-09-12 | 2013-06-04 | Cindy X. Qiu | Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits |
JP5979495B2 (ja) | 2013-03-19 | 2016-08-24 | Shマテリアル株式会社 | 半導体素子搭載用基板の製造方法 |
-
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH065631A (ja) * | 1992-06-23 | 1994-01-14 | Nec Corp | 金属電極の形成方法 |
JP2000022131A (ja) * | 1998-06-30 | 2000-01-21 | Fujitsu Quantum Devices Kk | 半導体装置およびその製造方法 |
JP2002009196A (ja) * | 2000-06-20 | 2002-01-11 | Kyushu Hitachi Maxell Ltd | 半導体装置の製造方法 |
US20070298603A1 (en) * | 2006-06-27 | 2007-12-27 | Kenneth Rebibis | Die configurations and methods of manufacture |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10204801B2 (en) | 2013-03-19 | 2019-02-12 | Ohkuchi Materials Co., Ltd. | Method for producing substrate for semiconductor element mounting |
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