JP5886617B2 - 配線基板及びその製造方法、半導体パッケージ - Google Patents

配線基板及びその製造方法、半導体パッケージ Download PDF

Info

Publication number
JP5886617B2
JP5886617B2 JP2011264488A JP2011264488A JP5886617B2 JP 5886617 B2 JP5886617 B2 JP 5886617B2 JP 2011264488 A JP2011264488 A JP 2011264488A JP 2011264488 A JP2011264488 A JP 2011264488A JP 5886617 B2 JP5886617 B2 JP 5886617B2
Authority
JP
Japan
Prior art keywords
electrode pad
insulating layer
layer
wiring
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2011264488A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013118255A5 (enExample
JP2013118255A (ja
Inventor
金子　健太郎
健太郎 金子
小林　和弘
和弘 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2011264488A priority Critical patent/JP5886617B2/ja
Priority to US13/681,732 priority patent/US8810040B2/en
Publication of JP2013118255A publication Critical patent/JP2013118255A/ja
Publication of JP2013118255A5 publication Critical patent/JP2013118255A5/ja
Application granted granted Critical
Publication of JP5886617B2 publication Critical patent/JP5886617B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/032—Organic insulating material consisting of one material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/695—Organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Structure Of Printed Boards (AREA)
JP2011264488A 2011-12-02 2011-12-02 配線基板及びその製造方法、半導体パッケージ Active JP5886617B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011264488A JP5886617B2 (ja) 2011-12-02 2011-12-02 配線基板及びその製造方法、半導体パッケージ
US13/681,732 US8810040B2 (en) 2011-12-02 2012-11-20 Wiring substrate including projecting part having electrode pad formed thereon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011264488A JP5886617B2 (ja) 2011-12-02 2011-12-02 配線基板及びその製造方法、半導体パッケージ

Publications (3)

Publication Number Publication Date
JP2013118255A JP2013118255A (ja) 2013-06-13
JP2013118255A5 JP2013118255A5 (enExample) 2014-10-09
JP5886617B2 true JP5886617B2 (ja) 2016-03-16

Family

ID=48523402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011264488A Active JP5886617B2 (ja) 2011-12-02 2011-12-02 配線基板及びその製造方法、半導体パッケージ

Country Status (2)

Country Link
US (1) US8810040B2 (enExample)
JP (1) JP5886617B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022240236A1 (ko) * 2021-05-13 2022-11-17 엘지이노텍 주식회사 반도체 패키지

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102114314B1 (ko) 2013-06-26 2020-05-25 삼성디스플레이 주식회사 유기발광 디스플레이 장치 및 그 제조방법
JP6161437B2 (ja) * 2013-07-03 2017-07-12 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
JP6131135B2 (ja) * 2013-07-11 2017-05-17 新光電気工業株式会社 配線基板及びその製造方法
JP6197420B2 (ja) * 2013-07-11 2017-09-20 凸版印刷株式会社 配線基板
JP2015032649A (ja) * 2013-08-01 2015-02-16 イビデン株式会社 配線板の製造方法および配線板
JP6133227B2 (ja) * 2014-03-27 2017-05-24 新光電気工業株式会社 配線基板及びその製造方法
US9603247B2 (en) * 2014-08-11 2017-03-21 Intel Corporation Electronic package with narrow-factor via including finish layer
TWI576930B (zh) * 2015-02-26 2017-04-01 胡志良 Circuit package of circuit component module and its product
KR101665242B1 (ko) * 2015-03-20 2016-10-11 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이의 제조 방법
US9755030B2 (en) 2015-12-17 2017-09-05 International Business Machines Corporation Method for reduced source and drain contact to gate stack capacitance
JP6715618B2 (ja) * 2016-02-23 2020-07-01 イビデン株式会社 プリント配線板
JP2017152536A (ja) * 2016-02-24 2017-08-31 イビデン株式会社 プリント配線板及びその製造方法
JP6674284B2 (ja) * 2016-02-29 2020-04-01 株式会社フジクラ 実装構造及びモジュール
JP6816964B2 (ja) * 2016-03-10 2021-01-20 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP6619294B2 (ja) 2016-05-24 2019-12-11 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
JP6776686B2 (ja) * 2016-07-21 2020-10-28 凸版印刷株式会社 配線基板及び配線基板、半導体装置の製造方法
US10347507B2 (en) * 2017-09-29 2019-07-09 Lg Innotek Co., Ltd. Printed circuit board
KR102531762B1 (ko) 2017-09-29 2023-05-12 엘지이노텍 주식회사 인쇄회로기판 및 이의 제조 방법
CN109803481B (zh) * 2017-11-17 2021-07-06 英业达科技有限公司 多层印刷电路板及制作多层印刷电路板的方法
TWI693872B (zh) 2018-10-29 2020-05-11 欣興電子股份有限公司 電路板製造方法
US11683890B2 (en) * 2018-12-20 2023-06-20 Intel Corporation Reflow grid array to support late attach of components
KR20200097977A (ko) * 2019-02-11 2020-08-20 삼성전기주식회사 인쇄회로기판
US12205877B2 (en) * 2019-02-21 2025-01-21 AT&S(Chongqing) Company Limited Ultra-thin component carrier having high stiffness and method of manufacturing the same
CN111599687B (zh) * 2019-02-21 2022-11-15 奥特斯科技(重庆)有限公司 具有高刚度的超薄部件承载件及其制造方法
TWI742991B (zh) * 2021-01-20 2021-10-11 啟耀光電股份有限公司 基板結構與電子裝置
CN116528466A (zh) * 2022-01-21 2023-08-01 奥特斯奥地利科技与系统技术有限公司 具有突出部的部件承载件和制造方法
CN120568609A (zh) * 2025-07-08 2025-08-29 芯爱科技(南京)有限公司 一种表面镀覆形成无凹陷深度的ets基板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3629178B2 (ja) * 2000-02-21 2005-03-16 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置及びその製造方法
JP2004288785A (ja) * 2003-03-20 2004-10-14 Sony Corp 導電突起の接合構造及び接合方法
TW200505304A (en) * 2003-05-20 2005-02-01 Matsushita Electric Industrial Co Ltd Multilayer circuit board and method for manufacturing the same
JP2005005504A (ja) * 2003-06-12 2005-01-06 Sharp Corp プリント配線基板の突起電極構造およびその製造方法
JP5653144B2 (ja) * 2004-12-16 2015-01-14 新光電気工業株式会社 半導体パッケージの製造方法
JP4619223B2 (ja) * 2004-12-16 2011-01-26 新光電気工業株式会社 半導体パッケージ及びその製造方法
JP5210839B2 (ja) * 2008-12-10 2013-06-12 新光電気工業株式会社 配線基板及びその製造方法
JP5221315B2 (ja) * 2008-12-17 2013-06-26 新光電気工業株式会社 配線基板及びその製造方法
JP5147779B2 (ja) * 2009-04-16 2013-02-20 新光電気工業株式会社 配線基板の製造方法及び半導体パッケージの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022240236A1 (ko) * 2021-05-13 2022-11-17 엘지이노텍 주식회사 반도체 패키지

Also Published As

Publication number Publication date
US8810040B2 (en) 2014-08-19
US20130140692A1 (en) 2013-06-06
JP2013118255A (ja) 2013-06-13

Similar Documents

Publication Publication Date Title
JP2013118255A (ja) 配線基板及びその製造方法、半導体パッケージ
JP5693977B2 (ja) 配線基板及びその製造方法
JP6161437B2 (ja) 配線基板及びその製造方法、半導体パッケージ
JP5101169B2 (ja) 配線基板とその製造方法
JP6133227B2 (ja) 配線基板及びその製造方法
JP6375159B2 (ja) 配線基板、半導体パッケージ
JP7253946B2 (ja) 配線基板及びその製造方法、半導体パッケージ
JP6341714B2 (ja) 配線基板及びその製造方法
US9334576B2 (en) Wiring substrate and method of manufacturing wiring substrate
JP2010245280A (ja) 配線基板の製造方法及び配線基板
JP2017108019A (ja) 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法
JP5406572B2 (ja) 電子部品内蔵配線基板及びその製造方法
CN102132639A (zh) 电子部件内置线路板及其制造方法
JP7198154B2 (ja) 配線基板、及び配線基板の製造方法
JP2019016683A (ja) 配線基板及びその製造方法、半導体パッケージ
JP4022405B2 (ja) 半導体チップ実装用回路基板
JP2010129998A (ja) 金属バンプを持つプリント基板及びその製造方法
JP2016149517A (ja) 配線基板及びその製造方法
JP6691031B2 (ja) 配線基板及びその製造方法、半導体パッケージ
JP6671256B2 (ja) 配線基板及びその製造方法
JP2012074487A (ja) 半導体パッケージの製造方法
JP2018195600A (ja) 配線基板、配線基板の製造方法
JP6220799B2 (ja) 配線基板及びその製造方法
JP2017152477A (ja) プリント配線板
JP6392140B2 (ja) 配線基板及び半導体パッケージ

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140827

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140827

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150520

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150602

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150723

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160202

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160212

R150 Certificate of patent or registration of utility model

Ref document number: 5886617

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150