TWI576930B - Circuit package of circuit component module and its product - Google Patents

Circuit package of circuit component module and its product Download PDF

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Publication number
TWI576930B
TWI576930B TW104106284A TW104106284A TWI576930B TW I576930 B TWI576930 B TW I576930B TW 104106284 A TW104106284 A TW 104106284A TW 104106284 A TW104106284 A TW 104106284A TW I576930 B TWI576930 B TW I576930B
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Taiwan
Prior art keywords
terminals
metal plate
wafers
wafer
component module
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TW104106284A
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English (en)
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TW201631676A (zh
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Zhi-Liang Hu
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Zhi-Liang Hu
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Priority to TW104106284A priority Critical patent/TWI576930B/zh
Priority to US14/921,369 priority patent/US9735138B2/en
Publication of TW201631676A publication Critical patent/TW201631676A/zh
Application granted granted Critical
Publication of TWI576930B publication Critical patent/TWI576930B/zh

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    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

電路元件模組的封裝方法及其製品
本發明是有關於一種封裝方法，特別是指一種電路元件模組的封裝方法及其製品。
隨著半導體製程技術的提升，使得現今電子元件的性能隨著製程演進而逐漸提高，然而，在電子元件性能提高的同時，也代表著電子元件的功耗同步提升，如此將使得電子元件的工作溫度上升。此外，電子元件需搭配周邊線路使能運作，然而現今的電子產品常利用多層基板相互堆疊以形成線路層，然而多層基板的堆疊除了體積龐大外，多層基板的堆疊也需要預留堆疊的公差。
因此，本發明之其中一目的，即在提供一種具有良好散熱能力且利用單一基板形成線路層的電路元件模組的封裝方法。
因此，本發明之其中另一目的，即在提供一種有良好散熱能力且利用單一基板形成線路層的電路元件模組。
於是，本發明電路元件模組的封裝方法在一些實施態樣中，是包含以下步驟：
在一金屬板的一第一板面上利用蝕刻技術移除該金屬板的一部份以形成多對彼此相鄰的端子。
在每一對端子上設置一晶片，並使每一對端子與對應的各該晶片電連接。
在該金屬板的第一板面形成一覆蓋並密封每一對端子及該等晶片的絕緣層。
由該金屬板相反於該第一板面的一第二板面利用蝕刻技術移除該金屬板的一部份，以形成一與該等端子相連接的線路結構，且該等端子與該線路結構共同形成一與該等晶片電連接的線路單元。
在一些實施態樣中，先增加該金屬板至一定厚度，再利用蝕刻技術移除該金屬板的一部份以形成該等端子或該線路結構。
在一些實施態樣中，是利用電鍍製程增加該金屬板至一定厚度。
在一些實施態樣中，該金屬板是以金、銀、銅、鎳或鋁所製成。
在一些實施態樣中，該等晶片選自二極體晶片、電晶體晶片、發光二極體晶片、金氧半場效電晶體晶片、雙極性電晶體晶片及積體電路晶片其中至少一者。
在一些實施態樣中，設置該等晶片時，先在每一對端子塗佈導電膠後再將各該晶片對應各該導電膠設置 。
於是，本發明電路元件模組在一些實施態樣中，是包含：一線路單元、多個晶片及一絕緣層
該線路單元包括由一金屬板製成的多對彼此相鄰的端子，及一與該等端子相連接的線路結構，且每一對端子與該線路結構電連接。
該等晶片分別設置於對應的該等端子，並透過該等端子與該線路結構電連接。
該絕緣層包覆該等晶片及該等端子的一部份。
在一些實施態樣中，該金屬板是以金、銀、銅、鎳或鋁所製成。
在一些實施態樣中，該等晶片選自二極體晶片、電晶體晶片、發光二極體晶片、金氧半場效電晶體晶片、雙極性電晶體晶片及積體電路晶片其中至少一者。
本發明之功效在於：透過在同一金屬板上形成端子與線路結構，提高了金屬板的利用率，同時減少製作端子與線路結構時所需預留的公差。
101‧‧‧步驟
13‧‧‧端子
102‧‧‧步驟
14‧‧‧線路結構
103‧‧‧步驟
15‧‧‧線路單元
104‧‧‧步驟
2‧‧‧晶片
1‧‧‧金屬板
3‧‧‧導電膠
11‧‧‧第一板面
4‧‧‧絕緣層
12‧‧‧第二板面
本發明之其他的特徵及功效，將於參照圖式的實施例詳細說明中清楚地呈現，其中：圖1是一流程方塊圖，說明本發明電路元件模組的封裝方法之實施例的主要步驟；及圖2至5是說明該實施例的實施步驟的流程示意圖。
參閱圖1，為本發明電路元件模組的封裝方法之實施例主要實施步驟的流程方塊圖，包含以下步驟：步驟101，在一金屬板的一第一板面上利用蝕刻技術移除金屬板的一部份以形成多對彼此相鄰的端子；步驟102，在每一對端子上設置一晶片，並使每一對端子與對應的晶片電連接；步驟103，在金屬板的第一板面形成一覆蓋並密封每一對端子及晶片的絕緣層；步驟104，由金屬板相反於第一板面的一第二板面利用蝕刻技術移除金屬板的一部份，以形成一與端子相連接的線路結構，且端子與線路結構共同形成一與晶片電連接的線路單元。
以下配合圖2至圖5具體說明本實施例的實施步驟。
參閱圖2，步驟101是在一金屬板1的一第一板面11上利用蝕刻技術移除金屬板1的一部份以形成多對彼此相鄰的端子13。在本實施例中，金屬板1是以銅所製成，並利用微影蝕刻製程移除銅板的一部分以形成多對彼此相鄰的端子13。而在其他的實施態樣中，金屬板1亦可以其他金屬，例如金、銀、鎳或鋁等製成。而蝕刻方式在本實施例中是利用微影蝕刻製程，但在其他的實施態樣中也可利用例如雷射移除的方式來達成。此外，使用者也可先利用例如電鍍製程增加金屬板1至一定厚度，再利用微影 蝕刻製程移除金屬板1的一部份以形成特定厚度的端子13。使用者也可交互使用電鍍製程與微影蝕刻製程來製作特定厚度或圖案的端子13。也就是說，端子13的厚度與圖案、金屬板1材料的選用或是蝕刻方法的選擇是可依使用者的需求或視製程上的考量進行變更，而不以此處揭露的內容為限。
參閱圖3，步驟102是在每一對端子13上設置一晶片2，並使每一對端子13與對應的晶片2電連接。晶片2可為任何電子元件，例如二極體晶片、電晶體晶片、(LED Chip)、金氧半場效電晶體晶片(Metal-Oxide-Semiconductor Field-Effect Transistor)、雙極性電晶體晶片(Bipolar Transistor Chip)、積體電路晶片(Integrated Circuit Chip)，或是以元素週期表中三、五族，例如砷化鎵(GaAs)所製成的晶片等，也就是說，晶片2可全為單一類型的晶片，例如晶片2可全部為發光二極體晶片；晶片2也可為兩種以上晶片類型的組合，例如部分晶片2為發光二極體晶片，部分晶片2為雙極性電晶體晶片。此外，在本實施例中，晶片2是透過在對應的端子13上以印刷或點膠方式塗佈導電膠3而與對應的端子13固定並電連接。導電膠3是一種固化或乾燥後具有一定導電性能的膠黏劑，通常以基體樹脂和導電填料為主要組成成分。而適用的導電填料包括有金、錫、鉛、銀、鋁、鎳、銅、鉍或上述元素之組合等。
參閱圖4，步驟103是在金屬板1的第一板面 11形成一覆蓋並密封每一對端子13及晶片2的絕緣層4。待步驟102中所塗佈的導電膠3固化或乾燥後，以流體狀或粉末狀的絕緣材料覆蓋於金屬板1的第一板面11並填充晶片2與端子13之間的空隙，使絕緣材料固結後形成覆蓋並密封端子13及晶片2的絕緣層4。絕緣層4用以防禦輻射、水氣、氧氣，以及外力破壞晶片2。適用的絕緣材料例如環氧樹脂、聚亞醯胺等，或者一些在固結成形為絕緣層4時不會影響晶片2性質的矽化物、氧化物等。
參閱圖5，步驟104是由金屬板1相反於第一板面11的一第二板面12利用蝕刻技術移除金屬板1的一部份，以形成一與端子13相連接的線路結構14，且端子13與線路結構14共同形成一與晶片2電連接的線路單元15。在本實施例中，蝕刻方式為微影蝕刻製程，但也可利用例如雷射移除的方式來達成。此外，雖然在本實施例中是直接對金屬板1的第二板面12進行蝕刻而得到線路結構14，但在其他的實施態樣中，亦可先利用例如電鍍製程增加金屬板1至一定厚度，再利用微影蝕刻技術移除金屬板1的一部份以形成線路結構14。也可以先利用電鍍製程增加金屬板1至一定厚度，再利用微影蝕刻製程移除金屬板1的一部份，接著再次利用電鍍製程增加線路結構14至一定厚度以達到使用者的需求。也就是說，線路結構14的厚度與圖案是依使用者在製程或應用上的考量而可自由運用電鍍或蝕刻等製程增加或減少金屬板1的厚度而達成。
透過與端子13相連接的線路結構14，使得晶片 2得以與外部電路(圖未示)電性連結。且由於線路結構14與端子13是利用同一金屬板1透過蝕刻技術一體製作而成，因此除了可節省承載線路結構14的基板(圖未示)使用外，同時也可省略後續兩基板(即承載線路結構14的基板與承載晶片2的基板)相疊合的製程。另一方面，也由於線路結構14與端子13是利用同一金屬板1蝕刻而得，因此線路結構14與端子13在製程的公差控制上也可明顯小於傳統的多層基板疊合的公差。原因是因為多層基板的疊合往往是各個基板獨立製造後再相互疊合，如此則必須保留較大的公差範圍以避免各基板上的線路在疊合時無法順利對準。而在本實施例中，使用者可透過在步驟101的蝕刻步驟中預先蝕刻出步驟104蝕刻線路結構14的對準點(alignment mark)(圖未示)，如此在步驟104中蝕刻線路結構14時可依此對準點進行對準，進而大大減少線路結構14與端子13之間的公差，而較小的公差將可使電路設計者有較多的空間設計出更多元且性能更強大的電路元件模組。
除此之外，由於金屬板1的散熱能力普遍較非金屬板(例如FR4板)佳，因此可透過步驟101與104中的蝕刻製程預留金屬板1的散熱區(圖未示)，待晶片2通電運作後，其所產生的廢熱將可透過端子13與線路結構14傳遞至散熱區，以避免熱能累積而影響晶片2的運作效能及使用壽命。
參閱圖5，利用本實施例所製成的電子元件模組包含一線路單元15、多個晶片2及一絕緣層4。
線路單元15包括由一金屬板1(見圖2)製成的多對彼此相鄰的端子13及一與端子13相連接的線路結構14，且每一對端子13與線路結構14電連接。在本實施例中，金屬板1是以銅所製成，但亦可以金、銀、鎳或鋁等其他金屬材料製作。
多個晶片2分別設置於對應的端子13，並透過端子13與線路結構14電連接。晶片2在本實施例中可為二極體晶片、電晶體晶片、發光二極體晶片、金氧半場效電晶體晶片、雙極性電晶體晶片、積體電路晶片，或是以元素週期表中三、五族，例如砷化鎵所製成的晶片等，也就是說，晶片2可全為單一類型的晶片，例如晶片2可全部為發光二極體晶片；晶片2也可為兩種以上晶片類型的組合，例如部分晶片2為發光二極體晶片，部分晶片2為雙極性電晶體晶片。且在本實施例中，晶片2是透過在對應的端子13上以印刷或點膠方式塗佈導電膠3而與對應的端子13固定並電連接。
絕緣層4包覆晶片2及端子13的一部份，以防禦輻射、水氣、氧氣，以及外力等破壞晶片2。
因此，晶片2可透過線路單元15與外部電路電性連接，且透過由同一金屬板1製成的端子13及一線路結構14，使得端子13與線路結構14間所需預留的公差較小。
值得一提的是，儘管本發明電子元件模組中的晶片2已可透過線路單元15與外部電性連接，然而在其他 的實施態樣中，使用者也可將兩個電子元件模組相互堆疊，並透過穿孔(through hole)或是拉線等方式電性連接上下兩個電子元件模組而達到使用上的變化。
綜上所述，透過在同一金屬板1上形成端子13與線路結構14，不僅可以提高金屬板1的利用率，同時減少製作端子13與線路結構14時所需預留的公差。此外，藉由在金屬板1上預留供晶片2散熱的散熱區，以避免熱能累積而影響晶片2運作效能及使用壽命，故確實能達成本發明之目的。
惟以上所述者，僅為本發明之實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。
13‧‧‧端子
14‧‧‧線路結構
15‧‧‧線路單元
2‧‧‧晶片
3‧‧‧導電膠
4‧‧‧絕緣層

Claims (9)

  1. 一種電路元件模組的封裝方法，包含以下步驟：在一金屬板的一第一板面上利用蝕刻技術移除該金屬板的一部份以形成多對彼此相鄰的端子；在每一對端子上設置一晶片，並使每一對端子與對應的各該晶片電連接；在該金屬板的第一板面形成一覆蓋並密封每一對端子及該等晶片的絕緣層；及由該金屬板相反於該第一板面的一第二板面利用蝕刻技術移除該金屬板的一部份，以形成一與該等端子相連接的線路結構，且該等端子與該線路結構共同形成一與該等晶片電連接的線路單元。
  2. 如請求項1所述電路元件模組的封裝方法，其中，先增加該金屬板至一定厚度，再利用蝕刻技術移除該金屬板的一部份以形成該等端子或該線路結構。
  3. 如請求項2所述電路元件模組的封裝方法，其中，是利用電鍍製程增加該金屬板至一定厚度。
  4. 如請求項1所述電路元件模組的封裝方法，其中，該金屬板是以金、銀、銅、鎳或鋁所製成。
  5. 如請求項1所述電路元件模組的封裝方法，其中，該等晶片選自二極體晶片、電晶體晶片、發光二極體晶片、金氧半場效電晶體晶片、雙極性電晶體晶片及積體電路晶片其中至少一者。
  6. 如請求項1所述電路元件模組的封裝方法，其中，設置 該等晶片時，先在每一對端子塗佈導電膠後再將各該晶片對應各該導電膠設置。
  7. 一種電路元件模組，包含：一線路單元，包括由一金屬板製成的多對彼此相鄰的端子，及一與該等端子相連接的線路結構，且每一對端子與該線路結構電連接；多個晶片，分別設置於對應的該等端子，並透過該等端子與該線路結構電連接；及一絕緣層，包覆該等晶片及該等端子的一部份。
  8. 如請求項7所述電路元件模組，其中，該金屬板是以金、銀、銅、鎳或鋁所製成。
  9. 如請求項7所述電路元件模組，其中，該等晶片選自二極體晶片、電晶體晶片、發光二極體晶片、金氧半場效電晶體晶片、雙極性電晶體晶片及積體電路晶片其中至少一者。
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