JP5870433B2 - XOR and XNOR logic circuit and layout - Google Patents

Description

  The present invention relates to XOR and XNOR logic circuitry and layout.

  High performance and small die size requirements are driving the semiconductor industry to reduce circuit chip area by approximately 50% every two years. The reduction in chip area provides an economic benefit for moving to a new technology. A 50% chip area reduction is achieved by a feature size reduction of 25-30%. The feature size (process dimension) can be reduced by improving manufacturing apparatuses and materials. For example, improvements in the lithographic process have made it possible to achieve small feature sizes, whereas improvements in chemical mechanical polishing (CMP) have made it possible in part to achieve multilayering of interconnect layers. It was.

  In lithographic development, unintended interactions occur between adjacent features as the minimum feature size approaches the wavelength of the light source used to expose the feature shape. Today, the minimum feature size has been reduced to less than 45 nm (nanometers), while the wavelength of the light source used in the lithography process remains at 193 nm. The difference between the minimum feature size and the wavelength of the light source used in the lithographic process is defined as the lithographic gap. As the lithographic gap increases, the resolution of the lithographic process decreases.

  Each shape on the mask interacts with light to generate interference fringes. Interference fringes from adjacent shapes can produce constructive or destructive interference. In the case of constructive interference, undesirable shapes may be produced by chance. In the case of destructive interference, the required shape may be accidentally removed. In either case, a specific shape is printed in a manner different from the intended one, which may cause a malfunction of the device. A correction method such as optical proximity correction (OPC) is an attempt to correct the mask by predicting the effects from adjacent shapes so that the printed shape is created as required. The predictive quality of light interaction decreases as process graphics are scaled down and as light interaction becomes more complex.

  In view of the above, as technology continues to evolve in the direction of reducing the feature size of semiconductor devices, there is a need for solutions for circuit design and layout improvements that can improve lithographic gap management. .

  In one embodiment, an exclusive OR (XOR) logic circuit is disclosed. The XOR logic circuit includes a first input node, a second input node, and an output node. A pass gate is connected to be controlled by the logic state present at the second input node. The passgate is connected to pass one version of the logic state present at the first input node to the output node when controlled to transmit according to the logic state present at the second input node. ing. A transmission gate is connected to be controlled by the logic state present at the first input node. The transmission gate is connected to pass one version of the logic state present at the second input node to the output node when controlled to transmit by the logic state present at the first input node. Yes. Pull-up logic is connected to be controlled by both the logic state present at the first input node and the logic state present at the second input node. The pull-up logic sets the state present at the output node to low when both the logic state present at the first input node and the logic state present at the second input node are high. Connected to drive.

  In one embodiment, an exclusive OR (XOR) logic circuit layout is disclosed. The XOR logic circuit layout comprises 6 PMOS transistors and 5 NMOS transistors. Each of the five NMOS transistors is paired with five of the six PMOS transistors, and each pair of NMOS and PMOS transistors is a continuous array disposed along each one of the five gate electrode tracks. Defined to share a common gate electrode structure. The sixth of the six PMOS transistors is defined by a gate electrode structure disposed along the sixth gate electrode track, the sixth PMOS transistor dedicating the sixth gate electrode track as an exclusive OR logic circuit. Not shared with other transistors in the layout. The six gate electrode tracks are oriented parallel to each other.

In one embodiment, an exclusive NOR (XNOR) logic circuit is disclosed.
The XNOR logic circuit includes a first input node, a second input node, and an output node. A pass gate is connected to be controlled by the logic state present at the second input node. The passgate is connected to pass one version of the logic state present at the first input node to the output node when controlled to transmit according to the logic state present at the second input node. ing. A transmission gate is connected to be controlled by the logic state present at the first input node. The transmission gate is connected to pass one version of the logic state present at the second input node to the output node when controlled to transmit by the logic state present at the first input node. Yes. Pull-down logic is connected to be controlled by both the logic state present at the first input node and the logic state present at the second input node. The pull-down logic drives the state present at the output node high when both the logic state present at the first input node and the logic state present at the second input node are low. Connected to (drive).

  In one embodiment, a layout for an exclusive-NOR (XNOR) logic circuit is disclosed. The XNOR logic circuit layout comprises 5 PMOS transistors and 6 NMOS transistors. The five PMOS transistors are each paired with five of the six NMOS transistors, and each pair of PMOS and NMOS transistors is a continuous array disposed along each one of the five gate electrode tracks. Defined to share a common gate electrode structure. The sixth of the six NMOS transistors is defined by a gate electrode structure disposed along the sixth gate electrode track, the sixth NMOS transistor dedicating the sixth gate electrode track to an exclusive NOR logic. Not shared with other transistors in the circuit layout. The six gate electrode tracks are oriented parallel to each other.

  Other aspects and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, shown as examples of the present invention.

It is a figure which shows the conventional XOR logic gate circuit. It is a figure which shows the state table | surface of the conventional XOR logic gate circuit of FIG. 1A. It is a figure which shows the state table | surface of the conventional XOR logic gate circuit of FIG. 1A. It is a figure which shows the state table | surface of the conventional XOR logic gate circuit of FIG. 1A. It is a figure which shows the state table | surface of the conventional XOR logic gate circuit of FIG. 1A. FIG. 4 is a diagram illustrating a layout of a conventional XOR according to an embodiment of the present invention. It is a figure which shows an example of the inverter structure by a prior art. FIG. 4 illustrates an XNOR logic gate circuit according to an embodiment of the present invention. 2B is a diagram illustrating a state table of the XNOR logic gate circuit of FIG. 2A according to one embodiment of the present invention. FIG. 2B is a diagram illustrating a state table of the XNOR logic gate circuit of FIG. 2A according to one embodiment of the present invention. FIG. 2B is a diagram illustrating a state table of the XNOR logic gate circuit of FIG. 2A according to one embodiment of the present invention. FIG. 2B is a diagram illustrating a state table of the XNOR logic gate circuit of FIG. 2A according to one embodiment of the present invention. FIG. 2B is a diagram illustrating a layout of the XNOR logic gate circuit of FIG. 2A according to one embodiment of the present invention. FIG. FIG. 3 illustrates an XOR logic gate circuit according to an embodiment of the present invention. FIG. 3B is a diagram illustrating a state table of the XOR logic gate circuit of FIG. 3A according to one embodiment of the present invention. FIG. 3B is a diagram illustrating a state table of the XOR logic gate circuit of FIG. 3A according to one embodiment of the present invention. FIG. 3B is a diagram illustrating a state table of the XOR logic gate circuit of FIG. 3A according to one embodiment of the present invention. FIG. 3B is a diagram illustrating a state table of the XOR logic gate circuit of FIG. 3A according to one embodiment of the present invention. FIG. 3B is a diagram illustrating a layout of the XOR logic gate circuit of FIG. 3A according to one embodiment of the present invention. FIG. 4 illustrates an example of a gate electrode track defined within a restricted gate level layout architecture, according to one embodiment of the invention. 4B is a diagram illustrating an example of the restrictive gate level layout architecture of FIG. 4A having many illustrative gate level features defined therein, according to one embodiment of the present invention. FIG.

  In the following description, numerous detailed descriptions are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without some or all of these detailed descriptions. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

(Conventional XOR circuit)
FIG. 1A shows a conventional XOR logic gate circuit (hereinafter “XOR100”). XOR 100 has two inputs A and B and one output Q. Input A is supplied to node 101. Input B is supplied to node 102. The output Q is supplied from the node 105.
1B to 1E show state tables of the XOR 100. FIG. As shown in FIGS. 1B-1E, XOR 100 provides the appropriate state of output Q for various state combinations of inputs A and B.

  As shown in FIG. 1A, the node 101 that receives the input A is connected to the gate of the PMOS transistor 117 and the gate of the NMOS transistor 120. Node 101 is also connected to the input of inverter 110. The output of the inverter 110 is connected to the node 103. The node 103 is connected to the gate of the PMOS transistor 113 and the gate of the NMOS transistor 116.

  The node 102 is connected to the gate of the PMOS transistor 114 and the gate of the NMOS transistor 119. Node 102 is also connected to the input of inverter 111. The output of the inverter 111 is connected to the node 104. The node 104 is connected to the gate of the NMOS transistor 115 and the gate of the PMOS transistor 118.

  The PMOS transistors 113 and 114 are connected in series between the power supply (VDD) and the node 105 that supplies the output Q of the XOR 100. The NMOS transistors 115 and 116 are connected in series between the node 105 and the reference ground potential (GND). The PMOS transistors 117 and 118 are connected in series between the power supply (VDD) and the node 105. The NMOS transistors 119 and 120 are connected in series between the node 105 and the reference ground potential (GND).

  Based on the above, the conventional XOR 100 comprises two sets of pull-up logic, a first set defined by PMOS transistors 113 and 114 and a second set defined by PMOS transistors 117 and 118. XOR 100 also includes two sets of pull-down logic, a first set defined by NMOS transistors 115 and 116 and a second set defined by NMOS transistors 119 and 120. Each set of pull-up and pull-down logic is controlled by both an input A version and an input B version. Thus, based on inputs A and B, a conventional XOR 100 circuit drives output Q either high or low by the use of either set of pull-up logic or pull-down logic. Is defined as follows.

  Furthermore, it will be appreciated that each of the inverters 110 and 111 comprises one PMOS transistor and one NMOS transistor. FIG. 1G shows an example of an inverter configuration according to the prior art. This inverter receives an input signal A and generates an output signal Q. The inverter has a PMOS connected to be controlled by an input signal A, a first terminal connected to a power supply (VDD), and a second terminal connected to supply an output signal Q. A transistor 192 is provided. This inverter receives an input signal A and generates an output signal Q. The inverter also has a gate connected to be controlled by the input signal A, a first terminal connected to supply the output signal Q, and a second terminal connected to a reference ground potential (GND). And an NMOS transistor 193. When the input A of this inverter is high, the output will be low and vice versa. Of course, based on each inverter comprising one PMOS transistor and one NMOS transistor, the conventional XOR 100 comprises a total of six PMOS transistors and six NMOS transistors.

  FIG. 1F shows a layout of XOR 100 according to one embodiment of the present invention. The layout of XOR 100 is defined according to a restrictive gate level layout architecture, as described herein. The various PMOS and NMOS transistors described above with respect to FIG. 1A are correspondingly labeled in FIG. 1F. The various nodes described above with respect to FIG. 1A are also correspondingly labeled in FIG. 1F. The gate electrodes of PMOS transistor 118 and NMOS transistor 119 are co-linear such that they are separated within the gate level by an end-to-end space 195. Defined. Also, the gate electrodes of PMOS transistor 114 and NMOS transistor 115 are co-linear such that they are separated within the gate level by an end-to-end space 196. ).

  To lay out a conventional XOR 100 in six gate electrode tracks using a restrictive gate level architecture, end-to-end space (eg, 195 and 196) of at least two gate electrodes within the gate level of the XOR 100. It should be understood that it is necessary to have Such end-to-end gate electrode space is defined according to available design rules that require a minimum end-to-end space size. Thus, of course, the presence of the end-to-end gate electrode space separates the P-type and N-type diffusion regions further apart than would be required without the end-to-end gate electrode space. Requires a power, thereby requiring a larger overall cell height.

(Embodiment of XOR circuit and layout)
FIG. 3A illustrates an XOR logic gate circuit 300 (hereinafter “XOR 300”) according to one embodiment of the invention. XOR 300 comprises two inputs A and B and one output Q. Input A is supplied to node 301. Input B is supplied to node 302. The output Q is supplied from the node 307. 3B-3E illustrate a state table for the XOR 300 according to one embodiment of the present invention. As shown in FIGS. 3B-3E, XOR 300 provides the appropriate state of output Q for various state combinations of inputs A and B.

As shown in FIG. 3A, node 301 that receives input A is connected to both the input of inverter 310 and the gate of PMOS transistor 314. The node 302 that receives the input B is connected to the input of the inverter 311. The output of the inverter 310 is connected to the node 303. The node 303 is connected to 1) the first terminal of the NMOS transistor 312, 2) the gate of the PMOS transistor 316, and 3) the gate of the NMOS transistor 313. The output of the inverter 311 is connected to the node 304.
The node 304 is connected to 1) the gate of the NMOS transistor 312, 2) the gate of the PMOS transistor 315, 3) the first terminal of the NMOS transistor 313, and 4) the first terminal of the PMOS transistor 314.

  The node 305 is connected to 1) the second terminal of the NMOS transistor 312, 2) the second terminal of the NMOS transistor 313, 3) the second terminal of the PMOS transistor 314, and 4) the second terminal of the PMOS transistor 316. . A first terminal of the PMOS transistor 315 is connected to a power supply (VDD). The second terminal of the PMOS transistor 315 is connected to a node 306 that is connected to the first terminal of the PMOS transistor 316. Node 305 is connected to the input of inverter 317. The output of the inverter 317 is connected to a node 307 that provides the output Q of the XOR 300.

  The state tables of FIGS. 3B-3E show the different states of the various nodes (from node 301 to node 307) of XOR 300 when different state combinations are applied to inputs A and B. Each of the inverters 310, 311, and 317 includes one PMOS transistor and one NMOS transistor. Thus, compared to the conventional XOR100 with a total of 6 PMOS transistors and 6 NMOS transistors, the XOR300 has a total of 6 PMOS transistors and 5 NMOS transistors, thereby saving one NMOS transistor doing.

  As shown in FIGS. 3B-3E, a two-input XOR 300 is defined to process four unique combinations of inputs A and B. In particular, NMOS transistor 313 and PMOS transistor 314 together define a transmission gate 350 that is controlled by input A. When the state of input A is low, that is, logic 0, transmission gate 350 contributes to the control of the state of output Q and the state of output Q matches the state of input B. NMOS transistor 312 defines a pass gate 360 controlled by input B. When the state of the input B is low, that is, when the logic is 0, the pass gate 360 contributes to the control of the state of the output Q, and the state of the output Q matches the state of the input A.

  PMOS transistors 315 and 316 together define pull-up logic 370 that is controlled by both inputs A and B. When both the state of input A and the state of input B are high, i.e. logic 1, both transmission gate 350 and pass gate 360 are disabled and pull-up logic 370 is in the output Q state. And the state of the output Q becomes low, that is, logic 0. Pull-up logic 370 is disabled when either input A or B state is low, ie, logic zero.

XOR 300 is defined by either:
Pass the version of the state of input A to output Q by passgate 360 controlled by input B;
Pass the version of the state of input B to output Q by transmission gate 350 controlled by input A, or pull the state of output Q low by pull-up logic 370 under the control of both inputs A and B. To drive.

  As described above, the XOR logic circuit 300 includes the first input A node 301, the second input B node 302, and the output Q node 307. Passgate 360 is connected to be controlled by the logic state present at second input node 302. Passgate 360 is connected to pass a version of the logic state present at first input node 301 to output node 307 when controlled to transmit according to the logic state present at second input node 302. The Transmission gate 350 is connected to be controlled by the logic state present at first input node 301. The transmission gate 350 is connected to pass the version of the logic state present at the second input node 302 to the output node 307 when controlled to transmit according to the logic state present at the first input node 301. Is done. The pull-up logic 370 is connected to be controlled by both the logic state present at the first input node 301 and the logic state present at the second input node 302. Pull-up logic 370 drives the state present at output node 307 low when both the logic state present at first input node 301 and the logic state present at second input node 302 are high. Connected to.

  FIG. 3F shows a layout of XOR 300 according to one embodiment of the present invention. In one embodiment, the layout of XOR 300 is defined based on a restrictive gate level layout architecture, as described herein. The inverter 310 is defined by a PMOS transistor 310P and an NMOS transistor 310N that share a continuous gate electrode structure 310G defined along a single gate electrode track 380. The inverter 311 is defined by a PMOS transistor 311P and an NMOS transistor 311N that share a continuous gate electrode structure 311G defined along a single gate electrode track 384. The inverter 317 is defined by a PMOS transistor 317P and an NMOS transistor 317N that share a continuous gate electrode structure 317G defined along a single gate electrode track 385.

  The PMOS transistor 315 of the pull-up logic 370 and the NMOS transistor 312 of the pass gate 360 share a continuous gate electrode structure 381G defined along a single gate electrode track 381. The PMOS transistor 316 of the pull-up logic 370 and the NMOS transistor 313 of the transmission gate 350 share a continuous gate electrode structure 382G defined along a single gate electrode track 382. The PMOS transistor 314 of the transmission gate 350 is defined along a single gate electrode track 383. Nodes 301-307 are connected by various combinations of contacts, interconnect structures (M1, M2), and vias (Via1) in the XOR300 layout to make connections between the various transistors as shown in FIG. 3A. Defined.

  Of course, the layout of XOR 300 is defined using six adjacent gate electrode tracks (380-385) as defined by the restrictive gate electrode architecture. In one embodiment, six adjacent gate electrode tracks (380-385) are evenly spaced. However, in other embodiments, different vertical spaces can be used to separate six adjacent gate electrode tracks (380-385). Also, it will be appreciated that the XOR 300 layout does not require the placement of opposing gate electrode line ends as defined by a restrictive gate electrode architecture. In other words, there is no gate electrode structure placed end-to-end along any gate electrode track in the XOR 300 layout. Thus, lithography difficulties associated with producing end-to-end space between gate electrode features are avoided.

  Also, since there is no end-to-end gate electrode space located along any gate electrode track between the P-type and N-type diffusion regions, the vertical layout between the P-type and N-type diffusion regions The space does not have to follow minimum size requirements as defined by design rules related to the placement / manufacture of end-to-end gate electrode space. Thus, if required in certain embodiments, the overall cell height of the XOR 300 layout, ie, the vertical distance between VDD and GND, can be reduced by making the space between the P-type and N-type diffusion regions closer. .

  Further, the embodiment of FIGS. 3A and 3F is defined such that the gate of the PMOS transistor 315 is connected to the output of the second input inverter 311 and the gate of the PMOS transistor 316 is connected to the output of the first input inverter 310. Although pulled-up logic 370 is shown, it should be understood that the stacking of PMOS transistors 315 and 316 can be reversed. In particular, in one embodiment, the pull-up logic 370 is defined such that the PMOS transistor 315 is connected to the output of the first input inverter 310 and the gate of the PMOS transistor 316 is connected to the output of the second input inverter 311. Is done.

(XNOR circuit and layout embodiments)
FIG. 2A illustrates an XNOR logic gate circuit 200 (hereinafter “XNOR 200”) according to one embodiment of the invention. The XNOR 200 has two inputs A and B and one output Q. Input A is supplied to node 201. Input B is supplied to node 202. The output Q is supplied from the node 207. 2B-2E illustrate state tables of XNOR 200 according to one embodiment of the present invention. As shown in FIGS. 2B-2E, XNOR 200 provides the appropriate state of output Q for various state combinations of inputs A and B.

As shown in FIG. 2A, node 201 receiving input A is connected to both the input of inverter 210 and the gate of NMOS transistor 214. The node 202 that receives the input B is connected to the input of the inverter 211. The output of the inverter 210 is connected to the node 203. The node 203 is connected to 1) a first terminal of the PMOS transistor 212, 2) a gate of the PMOS transistor 213, and 3) a gate of the NMOS transistor 215. The output of the inverter 211 is connected to the node 204.
The node 204 is connected to 1) the gate of the PMOS transistor 212, 2) the gate of the NMOS transistor 216, 3) the first terminal of the PMOS transistor 213, and 4) the first terminal of the NMOS transistor 214.

  The node 205 is connected to each of 1) the second terminal of the PMOS transistor 212, 2) the second terminal of the PMOS transistor 213, 3) the second terminal of the NMOS transistor 214, and 4) the second terminal of the NMOS transistor 215. Yes. A first terminal of the NMOS transistor 216 is connected to a reference ground potential (GND). The second terminal of the NMOS transistor 216 is connected to a node 206 that is connected to the first terminal of the NMOS transistor 215. Node 205 is connected to the input of inverter 217. The output of the inverter 217 is connected to a node 207 that provides the output Q of the XNOR 200. The state tables of FIGS. 2B-2E show different states of the various nodes (from node 201 to node 207) of XNOR 200 when different state combinations are applied to inputs A and B. Each of the inverters 210, 211, and 217 includes one PMOS transistor and one NMOS transistor. Accordingly, the XNOR 200 includes a total of five PMOS transistors and six NMOS transistors.

  As shown in FIGS. 2B-2E, a two-input XNOR 200 is defined to process four unique combinations of inputs A and B. In particular, PMOS transistor 213 and NMOS transistor 214 together define a transmission gate 250 controlled by input A. When the state of input A is high, i.e. logic 1, transmission gate 250 contributes to control of the state of output Q and the state of output Q matches the state of input B. PMOS transistor 212 defines a pass gate 260 controlled by input B. When the state of the input B is high, that is, when the logic is 1, the pass gate 260 contributes to the control of the state of the output Q and the state of the output Q matches the state of the input A.

  NMOS transistors 215 and 216 together define pull-down logic 270 that is controlled by both inputs A and B. When both the state of input A and the state of input B are low, ie, logic 0, both transmission gate 250 and pass gate 260 are disabled, and pull-down logic 270 changes the state of output Q. Control, the state of the output Q is high, ie, logic one. Pull-down logic 270 is disabled when either state of inputs A and B is high, ie, logic one.

Based on the above, XNOR 200 is defined by one of the following:
Pass a version of the state of input A to output Q by passgate 260 controlled by input B;
Pass the version of the state of input B to output Q by transmission gate 250 controlled by input A, or pull the state of output Q high by pull-down logic 270 under the control of both inputs A and B To drive.

  As described above, the XNOR logic circuit 200 includes the first input A node 201, the second input B node 202, and the output Q node 207. Pass gate 260 is connected to be controlled by the logic state present at second input node 202. Passgate 260 is connected to pass the version of the logic state present at first input node 201 to output node 207 when controlled to transmit according to the logic state present at second input node 202. The Transmission gate 250 is connected to be controlled by the logic state present at first input node 201. The transmission gate 250 is connected to pass the version of the logic state present at the second input node 202 to the output node 207 when controlled to transmit according to the logic state present at the first input node 201. Is done. The pull-down logic 270 is connected to be controlled by both the logic state present at the first input node 201 and the logic state present at the second input node 202. Pull-down logic 270 drives the state present at output node 207 high when both the logic state present at first input node 201 and the logic state present at second input node 202 are low. Connected.

  FIG. 2F shows a layout of XNOR 200 according to one embodiment of the present invention. In one embodiment, the layout of XNOR 200 is defined based on a restrictive gate level layout architecture, as described herein. Inverter 210 is defined by PMOS transistor 210P and NMOS transistor 210N sharing a continuous gate electrode structure 210G defined along a single gate electrode track 280. The inverter 211 is defined by a PMOS transistor 211P and an NMOS transistor 211N that share a continuous gate electrode structure 211G defined along a single gate electrode track 284. Inverter 217 is defined by PMOS transistor 217P and NMOS transistor 217N sharing a continuous gate electrode structure 217G defined along a single gate electrode track 285.

  The NMOS transistor 216 of the pull-down logic 270 and the PMOS transistor 212 of the pass gate 260 share a continuous gate electrode structure 281G defined along a single gate electrode track 281. The NMOS transistor 215 of the pull-down logic 270 and the PMOS transistor 213 of the transmission gate 250 share a continuous gate electrode structure 282G defined along a single gate electrode track 282. The NMOS transistor 214 of the transmission gate 250 is defined along a single gate electrode track 283. Nodes 201-207 are connected by various combinations of contacts, interconnect structures (M1, M2), and vias (Via1) in the XNOR200 layout to provide connections between the various transistors as shown in FIG. 2A. Defined.

  Of course, the layout of XNOR 200 is defined using six adjacent gate electrode tracks (280-285) as defined by the restrictive gate electrode architecture. In one embodiment, six adjacent gate electrode tracks (280-285) are evenly spaced. However, in other embodiments, different vertical spaces can be used to separate six adjacent gate electrode tracks (280-285). Also, it will be appreciated that the XNOR 200 layout does not require the placement of opposing gate electrode line ends as defined by a restrictive gate electrode architecture. In other words, there is no gate electrode structure placed end-to-end along any gate electrode track in the XNOR 200 layout. Thus, lithography difficulties associated with producing end-to-end space between gate electrode features are avoided.

  Also, since there is no end-to-end gate electrode space located along any gate electrode track between the P-type and N-type diffusion regions, the vertical layout between the P-type and N-type diffusion regions The space does not have to follow minimum size requirements as defined by design rules related to the placement / manufacture of end-to-end gate electrode space. Thus, if required in certain embodiments, the overall cell height of the XNOR200 layout, ie, the vertical distance between VDD and GND, can be reduced by making the space between the P-type and N-type diffusion regions closer. .

  Of course, the XOR 300 circuit and associated layout described herein can be converted to an XNOR circuit and associated layout by removing the output inverter 317. In this transformed configuration, output node 307 corresponds to node 305 and the relationship between output Q and inputs A and B is the same as that shown in the state tables of XNOR 200 in FIGS.

  Of course, the XNOR 200 circuit and associated layout shown herein can be converted to an XOR circuit and associated layout by removing the output inverter 217. In this converted configuration, output node 207 corresponds to node 205 and the relationship between output Q and inputs A and B is the same as that shown in the state tables of FIGS. 3B-3E of XOR 300.

  Further, the embodiment of FIGS. 2A and 2F is defined such that the gate of NMOS transistor 216 is connected to the output of second input inverter 211 and the gate of NMOS transistor 215 is connected to the output of first input inverter 210. Although pulled down logic 270 is shown, it should be understood that the stacking of NMOS transistors 216 and 215 can be reversed. In particular, in one embodiment, pull-down logic 270 is defined such that NMOS transistor 216 is connected to the output of first input inverter 210 and the gate of NMOS transistor 215 is connected to the output of second input inverter 211. The

(Restrictive gate level layout architecture)
As described above, the XOR 300 and XNOR 200 circuits according to the present invention are implemented within a limited gate level layout architecture of a portion of a semiconductor chip. Because of the gate level, a number of parallel virtual lines are defined across the layout. These parallel virtual lines are referred to as gate electrode tracks and they are used as indicators of the placement of the gate electrodes of the various transistors in the layout. In one embodiment, the parallel virtual lines that form the gate electrode tracks are defined by a vertical space between them equal to the specified gate electrode pitch. Therefore, the arrangement of the gate electrode segments on the gate electrode track corresponds to the specified gate electrode pitch. In other embodiments, the gate electrode tracks are spaced at various pitches above the specified gate electrode pitch.

  FIG. 4A illustrates an example of gate electrode tracks 401A-401E defined within a restrictive gate level layout architecture, according to one embodiment of the invention. The gate electrode tracks 401A-401E are formed by parallel virtual lines extending across the gate level layout of the chip with a vertical space between them equal to the specified gate electrode pitch 407. For illustration purposes, complementary diffusion regions 403 and 405 are shown in FIG. 4A. Of course, the diffusion regions 403 and 405 are defined at a diffusion level below the gate level. It should also be appreciated that the diffusion regions 403 and 405 are shown by way of example and have limited diffusion region size, shape, and / or placement within the diffusion level in connection with the restrictive gate level layout architecture. It is not something.

  Within the restrictive gate level layout architecture, a gate level feature layout channel is defined near a predetermined gate electrode track so as to extend between gate electrode tracks adjacent to the predetermined gate electrode track. For example, gate level feature layout channels 401A-1 to 401E-1 are defined near gate electrode tracks 401A to 401E, respectively. Of course, each gate electrode track has a corresponding gate level feature layout channel. Also, as exemplified by the gate level feature layout channels 401A-1 to 401E-1, for gate electrode tracks located adjacent to the edges of the defined layout space, eg, adjacent to cell boundaries, The corresponding gate level feature layout channel expands as if the virtual gate electrode track is outside the defined layout space. Further, it will be appreciated that each gate level feature layout channel is defined to extend along the entire length of its corresponding gate electrode track. Thus, each gate level feature layout channel is defined such that it extends across the gate level layout within the portion of the chip to which the gate level layout relates.

  Within the restrictive gate level layout architecture, the gate level features associated with a given gate electrode track are defined within the gate level feature layout channel associated with that given gate electrode track. The continuous gate level feature can include both a portion that defines the gate electrode of the transistor and a portion that does not define the gate electrode of the transistor. Thus, continuous gate level features can extend over both the underlying chip level diffusion and dielectric regions.

  In one embodiment, the substantial center of each portion of the gate level feature that forms the gate electrode of the transistor is positioned to be on a given gate electrode track. Further, in this embodiment, the portion of the gate level feature that does not form the gate electrode of the transistor can be placed in a gate level feature layout channel associated with a given gate electrode track. Thus, as long as the center of the gate electrode portion of a given gate level feature is on the gate electrode track corresponding to the given gate level feature layout channel, and as long as the given gate level feature is in the adjacent gate level layout channel A given gate level feature can be defined essentially anywhere within a given gate level feature layout channel as long as it matches the design rule space requirements for other gate level features. In addition, physical contact is prevented between gate level features defined in gate level feature layout channels associated with adjacent gate electrode tracks.

FIG. 4B shows an example of the restrictive gate level layout architecture of FIG. 4A with many illustrative gate level features 409-423 defined therein, according to one embodiment of the invention. The gate level feature 409 is defined in the gate level feature layout channel 401A-1 associated with the gate electrode track 401A.
The substantial center of the gate electrode portion of the gate level feature 409 is on the gate electrode track 401A. Also, the non-gate electrode portion of the gate level feature 409 maintains the design rule space requirements for the gate level features 411 and 413 defined in the adjacent gate level feature layout channel 401B-1.
Similarly, the gate level features 411-423 are defined within their respective gate level feature layout channels, and the substantial center of their gate electrode portion is the gate electrode track corresponding to their respective gate level feature layout channel. It is above. It will also be appreciated that each of the gate level features 411-423 maintains the design rule space requirements for the gate level features defined in the adjacent gate level feature layout channel and is defined in the adjacent gate level feature layout channel. Prevent physical contact with other gate level features

  The gate electrode corresponds to a portion of each gate level feature that extends over the diffusion region, and each gate level feature is generally defined within a gate level feature layout channel. Each gate level feature is defined in its gate level feature layout channel without physically contacting other gate level features defined in adjacent gate level feature layout channels. As illustrated by the exemplary gate level feature layout channels 401A-1 through 401E-1 in FIG. 4B, each gate level feature layout channel is associated with a predetermined gate electrode track and along a predetermined gate electrode track. Corresponding to a layout region extending vertically outward in the opposite direction from a predetermined gate electrode track to an adjacent gate electrode track or a virtual gate electrode track outside the layout boundary.

  Some gate level features may have one or more contact head portions defined at a number of locations along their length. The contact head portion of a given gate level feature is defined as a segment of a gate level feature having a height and width sufficient to accept a gate contact structure, and the “width” The height is defined over the entire substrate in a direction parallel to the gate electrode track of a predetermined gate level feature. Of course, the gate level feature contact head may be defined by essentially any layout shape, including a square or a rectangle, when viewed from above. Also, depending on layout requirements and circuit design, a given contact head portion of the gate level feature may or may not have a gate contact defined thereon.

  The gate levels of the various embodiments described herein are defined as restrictive gate levels, as described above. Some of the gate level features form the gate electrode of the transistor element. Other gate level features can form conductive segments that extend between two points in the gate level. Other gate level features may also be non-functional with respect to integrated circuit operation. Of course, each of the gate level features, regardless of function, will have their respective gate level features without physical contact with other gate level features defined by adjacent gate level feature layout channels. It is defined to extend across the entire gate level in the layout channel.

  In one embodiment, the gate level feature is a lithographic interaction between a finite number of controlled layout shapes that are accurately predicted and optimized in the manufacturing and design process (shape-to-shape). Is defined to provide In this embodiment, the gate level feature prevents spatial correlation between layout shapes that may generate reverse lithographic interactions in the layout that cannot be accurately predicted and mitigated with high probability. Defined. However, it will be appreciated that changes in the orientation of gate level features within the gate level layout channel are acceptable when the corresponding lithographic interaction is predictable and manageable.

  Of course, each of the gate level features connect directly within the gate level to other gate level features defined along different gate electrode tracks, regardless of function, without using non-gate level features Defined to be free of gate level features along a predetermined gate electrode track configured in such a manner. In addition, each connection between gate level features located in different gate level layout channels associated with different gate electrode tracks is made through one or more non-gate level features, although the non-gate level A feature may be defined through a higher interconnect level, ie, one or more interconnect levels above the gate level, or by local interconnect features below the gate level.

  Of course, the XOR 300 and XNOR 200 circuits and layouts disclosed herein can be stored in a specific form such as a digital format on a computer readable medium. For example, the layout of the XOR 300 and / or XNOR 200 circuit disclosed herein may be stored in a layout data file as one or more cells selectable from one or more cell libraries. Is possible. The layout data file may be a GDS2 (Graphic Data System) database file, an OASIS (Open Artwork System Interchange Standard) database file, or other suitable for storing and communicating semiconductor device layouts It can be formatted as any kind of data file format. Also, the multi-level layout of the XOR 300 and / or XNOR 200 circuit can be included within the multi-level layout of a larger semiconductor device. Multi-level layouts of larger semiconductor devices can also be stored in the form of layout data files as described above.

  The invention described in the present specification can also be embodied as computer readable code on a computer readable medium. For example, the computer readable code may include a layout data file in which the XOR 300 and / or XNOR 200 circuit layout is stored. The computer readable code may also include one or more layout libraries including XOR 300 and / or XNOR 200 circuit layouts and / or program instructions for selecting cells. Also, the layout library and / or cells can be stored in a digital format on a computer readable medium.

  The computer readable medium described herein is any data storage device that can store data, which can be thereafter read by a computer system. Examples of computer readable media include hard drives, network attached storage (NAS), read only memory (ROM), random access memory (RAM) CD-ROM, CD-R, magnetic tape, and Includes other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network of connected computer systems so that the computer readable code is stored and executed in a distributed fashion.

  All the operations described herein that form part of the present invention are useful machine operations. The invention also relates to a device or apparatus for implementing these operations. The device may be configured for a predetermined purpose, such as a special purpose computer in particular. When defined as a special purpose computer, that computer can also perform other processing, program execution or routines that are not part of the special purpose, but can also perform special purpose operations. is there. Alternatively, the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in computer memory, cache, or acquired over a network. When data is acquired over a network, the data may be processed by other computers on the network, such as a cloud of computer resources.

  Embodiments of the present invention can also be defined as machines that convert from one state to another. The data may represent articles that can be expressed as electronic signals and electronic processing data. The transformed data can in some cases be visually depicted on a display, displaying the physical objects that result from the transformation of the data. The transformed data can be stored in a storage device in a general or specific format that allows the construction or depiction of physical and specific objects. In such an example, the processor thus converts data from one thing to another. Furthermore, the method can be processed by one or more machines or processors connected via a network. Each machine can convert data from one state or thing to another state or thing, can process the data, can store the data in a storage device, Can be transmitted, the results can be displayed, or the results can be communicated to other machines.

  Of course, the XOR 300 and XNOR 200 circuits and layouts disclosed herein can be manufactured as part of a semiconductor device or chip. In the manufacture of semiconductor devices such as integrated circuits, memory cells, etc., a series of manufacturing operations are performed to define features on a semiconductor wafer. The wafer includes integrated circuit devices in the form of multilevel structures defined on a silicon substrate. At the substrate level, a transistor element having a diffusion region is formed. At the next level, interconnect metallization lines are patterned and electrically connected to the transistor elements to define the desired integrated circuit device. The patterned conductive layer is insulated from other conductive layers by a dielectric material.

  While the invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art after reading the foregoing specification and studying the drawings embody various modifications, additions, substitutions and equivalents thereof. Will do. Accordingly, the present invention is intended to embrace all such alterations, additions, substitutions and equivalents as included within the true spirit and scope of the present invention.

200 XNOR (Exclusive NAND circuit)
250, 350 Transmission gate 260, 360 Pass gate 270 Pull-down logic 300 XOR (exclusive OR logic circuit)
370 Pull-up logic

Claims (16)

An exclusive OR logic circuit layout,
6 PMOS transistors,
5 NMOS transistors,
Each of the five NMOS transistors is paired with five of the six PMOS transistors, and each pair of NMOS and PMOS transistors is a series arranged along each one of the five gate electrode tracks. Defined to share a common gate electrode structure,
The sixth of the six PMOS transistors is defined by a gate electrode structure disposed along a sixth gate electrode track, and the sixth PMOS transistor defines the sixth gate electrode track as the exclusive logic. Do not share with other transistors in the sum logic circuit layout,
6. The exclusive OR logic circuit layout, wherein the six gate electrode tracks are oriented parallel to each other. The exclusive OR logic circuit layout according to claim 1,
The exclusive OR logic circuit layout is characterized in that there are no gate electrodes arranged on the same line having an end-to-end space between them. The exclusive OR logic circuit layout according to claim 1,
An exclusive OR logic circuit layout, wherein each gate electrode structure is defined to have a rectangular cross-section when viewed in a drafted state. The exclusive OR logic circuit layout according to claim 1,
An exclusive OR logic circuit layout, wherein the six gate electrode tracks are evenly spaced. The exclusive OR logic circuit layout according to claim 1,
The exclusive OR logic circuit layout is recorded in a digital format on a computer readable medium, wherein the exclusive OR logic circuit layout is recorded. The exclusive OR logic circuit layout according to claim 5,
The exclusive OR logic circuit layout, wherein the digital format is a data file format for storing and communicating one or more semiconductor device layouts. The exclusive OR logic circuit layout according to claim 5,
The computer readable medium includes program instructions for accessing and retrieving the exclusive OR logic circuit layout in the digital format from the computer readable medium. Sum logic circuit layout. The exclusive OR logic circuit layout according to claim 7,
The program instructions for accessing and retrieving include program instructions for selecting a library, cell, or both library and cell, including the exclusive OR logic circuit layout in the digital format. An exclusive OR logic circuit layout. An exclusive logical OR logic circuit layout,
5 PMOS transistors,
6 NMOS transistors,
Each of the five PMOS transistors is paired with five of the six NMOS transistors,
Each pair of PMOS and NMOS transistors is defined to share a continuous gate electrode structure disposed along each one of the five gate electrode tracks;
The sixth of the six NMOS transistors is defined by a gate electrode structure disposed along a sixth gate electrode track, and the sixth NMOS transistor rejects the sixth gate electrode track with the exclusive negation. Do not share with other transistors in the logical OR logic circuit layout,
6. The exclusive OR logic circuit layout, wherein the six gate electrode tracks are oriented parallel to each other. The exclusive NOR logic circuit layout according to claim 9,
The exclusive NOR logic circuit layout has no gate electrode arranged on the same line having an end-to-end space between them. The exclusive NOR logic circuit layout according to claim 9,
An exclusive NOR logic circuit layout, wherein each gate electrode structure is defined to have a rectangular cross-section when viewed in a drafted state. The exclusive NOR logic circuit layout according to claim 9,
6. An exclusive NOR logic circuit layout wherein the six gate electrode tracks are evenly spaced. The exclusive NOR logic circuit layout according to claim 9,
The exclusive-NOR logic circuit layout is recorded in a digital format on a computer-readable medium, wherein the exclusive-NOR logic circuit layout is recorded. The exclusive NOT logic circuit layout according to claim 13,
The exclusive logical OR logic circuit layout, wherein the digital format is a data file format for storing and communicating one or more semiconductor device layouts. The exclusive NOT logic circuit layout according to claim 13,
The computer readable medium includes program instructions for accessing and retrieving the exclusive NOR logic circuit layout in the digital format from the computer readable medium. NOT OR logic circuit layout. The exclusive-NOR logic circuit layout according to claim 15,
The program instructions for accessing and retrieving include program instructions for selecting a library, cell, or both library and cell, including the exclusive-or logic circuit layout in the digital format; Exclusive exclusive OR logic circuit layout.