FR2860920A1 - Multiple short local electrical connections for selective linkage of integrated circuit elements comprise masked selective humid attack of deposited metal - Google Patents

Multiple short local electrical connections for selective linkage of integrated circuit elements comprise masked selective humid attack of deposited metal Download PDF

Info

Publication number
FR2860920A1
FR2860920A1 FR0311987A FR0311987A FR2860920A1 FR 2860920 A1 FR2860920 A1 FR 2860920A1 FR 0311987 A FR0311987 A FR 0311987A FR 0311987 A FR0311987 A FR 0311987A FR 2860920 A1 FR2860920 A1 FR 2860920A1
Authority
FR
France
Prior art keywords
material
characterized
substrate
method according
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR0311987A
Other languages
French (fr)
Inventor
Stephan Niel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0311987A priority Critical patent/FR2860920A1/en
Publication of FR2860920A1 publication Critical patent/FR2860920A1/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides

Abstract

An electric connection selectively linking elements (10, 12) on an integrated circuit substrate (28) comprises: (a) realizing the elements on a substrate of which a part of the surface is made of a first material, depositing, on the substrate and the elements, a second conducting material (44, 46) that is able to create a reaction with the first material to form a conducting material on the substrate surface; (b) treating the substrate to produce the reaction; and (c) realizing a selective withdrawal of the second material that has not reacted with the first material, in order to leave some of the second material according to a pattern that corresponds with at least a part of the connection. An independent claim is also included for an integrated circuit incorporating the above electrical connections.

Description

PROCEDE DE REALISATION DE CONNEXIONS CONDUCTRICES DE PROCESS FOR CONDUCTING CONNECTIONS FOR CARRYING

CIRCUITS INTEGRES, ET CIRCUIT INTEGRE METTANT EN UVRE DES TELLES CONNEXIONS. INTEGRATED CIRCUITS AND INTEGRATED CIRCUIT USING SUCH CONNECTIONS UVRE.

L'invention concerne la réalisation de circuits intégrés, et plus particulièrement une technique de connexion électrique sélective entre des éléments du circuit intégré, notamment lorsque ces derniers sont relativement proches l'un de l'autre. The invention concerns the production of integrated circuits, and particularly selective electrical connection technology between elements of the integrated circuit, especially when they are relatively close to one another. A ce titre, l'invention permet de réaliser des interconnexions dites locales sur de courtes distances à l'échelle du circuit intégré. As such, the invention allows for so-called local interconnections for short distances across the integrated circuit.

Dans l'état de l'art, on réalise ces connexions locales par des techniques dites de niveau d'interconnexion local (connues par l'acronyme anglais de LIL, pour "Local Interconnect Level"). In the state of the art, we realize these local connections by techniques called local interconnect level (known by the acronym LIL, for "Local Interconnect Level"). De manière générale, ces interconnexions sont réalisées avec des niveaux de métallisation sur le silicium dans une structure diélectrique pré- métallique. Generally, these interconnections are formed with metallization levels on the silicon in a dielectric structure pre- metal. De telles interconnexions sont typiquement réalisées par dépôt de tungstène directement sur le silicium. Such interconnects are typically made by directly depositing tungsten on silicon.

La figure 1 illustre un exemple, vu de dessus, d'une topographie d'interconnexion de niveau local (abrévié dans ce qui suit à "interconnexion locale"), dans lequel sont représentées deux zones actives 2 et 4, chacune formant un îlot dans un substrat en silicium 6 du circuit intégré 8. L'isolation des deux zones actives est obtenue par formation d'un oxyde de champ du type dit tranchée d'isolation à faible profondeur 3 (connu par l'acronyme anglais STI, pour "Shallow Trench Isolation"). Figure 1 shows an example seen from above, of an interconnection of local topography (abbreviated hereinafter to "local interconnect"), wherein are represented two active areas 2 and 4, each forming an island in a silicon substrate 6 of the integrated circuit 8. the isolation of two active areas is obtained by forming a field oxide of the type known isolation trench shallow 3 (known by the acronym TSI, for "shallow Trench Isolation ").

Une première zone active 2 représentée comporte deux transistors MOS, dont les grilles respectives 10 et 12 sont reliées électriquement par une première interconnexion locale 14. A first active region 2 shown comprises two MOS transistors whose respective gates 10 and 12 are electrically connected by a first local interconnect 14.

Par ailleurs, les deux zones actives 2 et 4 sont reliées électriquement entre elles de part et d'autre de la tranchée 3 par une deuxième interconnexion locale 16. Furthermore, the two active areas 2 and 4 are electrically interconnected to either side of the trench 3 by a second local interconnect 16.

Enfin, la seconde zone active 4 comporte une troisième interconnexion locale 18, qui est verticale afin de relier deux niveaux conducteurs superposés, en l'occurrence au voisinage de la grille de contrôle 20 d'un transistor MOS. Finally, the second active area 4 comprises a third local interconnection 18, which is vertical in order to connect two superposed conductive levels, namely in the vicinity of the control gate 20 of a MOS transistor.

Les interconnexions locales sont réalisées au niveau du silicium dans le but de connecter entre elles des lignes de silicium polycristallin et des lignes de zones actives. Local interconnections are formed at the silicon in order to connect to each of the lines of polysilicon and the active areas of lines.

Selon les techniques classiques de réalisation, les interconnexions locales 14, 16, 18 sont en métal, typiquement du tungstène (W). According to conventional techniques embodiment, local interconnects 14, 16, 18 are made of metal, typically tungsten (W). Les interconnexions locales qui sont latérales relativement au plan du circuit intégré, comme les première et deuxième interconnexions 14, 16, sont chacune sous forme de tranchée. Local interconnections that are lateral relative to the plane of the integrated circuit, as the first and second interconnects 14, 16 are each in the form of trench. Les interconnexions verticales, par exemple la troisième interconnexion 18, sont sous forme d'un trou rempli d'un matériau conducteur formant un contact connu par le terme anglais de "plug". The vertical interconnections, for example the third interconnection 18 are in the form of a hole filled with a conductive material forming a contact known by the English term "plug".

Plus généralement, les interconnexions locales se répartissent en deux types tranchées et trous, comblés de matériau conducteur. More generally, the local interconnections are divided into two types trenches and holes filled with conductive material.

Les tranchées servent à connecter notamment deux zones du circuit, par exemple deux zones actives, deux ligne de polysilicium, ou une zone active et une ligne de polysilicium. The trenches serve to connect two particular areas of the circuit, for example two active areas, two polysilicon line, or an active area and a polysilicon line. Les trous servent à connecter juste un point particulier à un autre. The holes are used to connect just one particular point to another.

La réalisation des interconnexions locales fait intervenir un niveau supplémentaire de photolithographie et gravure. The realization of local interconnections involves an additional level of photolithography and etching.

Pour mémoire, les figures 2a à 2d représentent schématiquement les étapes principales dans la formation d'un motif en relief sur une plaquette de silicium par une technique de photolithographie et gravure. For reference, Figures 2a to 2d show schematically the main steps in the formation of a relief pattern on a silicon wafer by a technique of photolithography and etching.

A un stade initial (figure 2a), un masque 22 comportant sous forme de découpes 24 un motif de matériau à supprimer est apposé sur une couche de résine photosensible 26 déposée uniformément sur la surface de la plaquette de silicium 28. Un rayonnement 30 apte à provoquer une réaction sur la résine est appliqué à travers le masque. At an initial stage (Figure 2a), a mask 22 having cutouts 24 in the form of a pattern of material to be deleted is displayed on a photoresist layer 26 deposited uniformly on the surface of the silicon wafer 28. A suitable radiation 30 cause a reaction on the resin is applied through the mask.

L'ensemble comprenant le substrat 28 et la résine 26 est développé dans un bain chimique de sorte à retirer les parties exposée de la résine, rendues non résistantes au bain. The assembly comprising the substrate 28 and the resin 26 is developed in a chemical bath in order to remove the exposed portions of the resin, rendered non-resistant to the bath. On obtient alors le motif du masque 22 reproduit en relief sur la résine, permettant d'exposer la surface supérieure 28a du substrat 28 aux endroits où la résine est retirée (figure 2b). One then obtains the mask pattern 22 reproduces in relief on the resin, for exposing the upper surface 28a of the substrate 28 at locations where the resin is removed (Figure 2b).

L'ensemble précité est ensuite soumis à une gravure, par exemple du type par contact, durant laquelle la surface exposée 28a du silicium est usinée chimiquement pour former des tranchées 32, dont la surface du fond 32a est sensiblement en retrait de la surface supérieure 28a du substrat (figure 2c). The above assembly is then subjected to etching, for example contact type, in which the silicon of the exposed surface 28a is machined chemically to form trenches 32, the surface of the bottom 32a is substantially set back from the upper surface 28a of the substrate (Figure 2c).

Enfin, la résine est complètement retirée du substrat silicium 28 (figure 2d). Finally, the resin is completely removed from the silicon substrate 28 (Figure 2d).

La figure 3 illustre, par une vue selon la ligne III-III' de la figure 1, la réalisation concrète des interconnexions locales de la figure 1 selon un état de la technique. Figure 3 illustrates, in a view along the line III-III 'of Figure 1, the practical realization of local interconnections of Figure 1 according to a prior art.

Pour définir les tranchées et les trous ("plugs") devant former les interconnexions locales du circuit, on prévoit le dépôt, sur la surface du substrat 28, de deux niveaux de diélectrique dits pré-métalliques (plus connue par l'acronyme anglais PMD, pour "Pre-Metal Dielectric"), chacun comportant les éléments conducteurs 14, 16 qui constituent les interconnexions locales. To define the trenches and the holes ( "plugs") to form the local interconnections of the circuit, there is provided the deposition on the substrate surface 28, two levels of said pre-metal dielectric (known by the acronym PMD for "Pre-Metal Dielectric"), each having the conductive elements 14, 16 which constitute the local interconnections. (Le terme "pré-métallique provient du fait que ces niveaux sont situés entre le substrat 28 et un premier niveau de métallisation 34, dit "métal 1" du circuit intégré.) Dans la figure, les premier et second niveaux de la structure, comptés à partir du substrat 28, sont respectivement désignés PMD1 et PMD2. (The term "pre-metal from the fact that these levels are located between the substrate 28 and a first level of metallization 34, known as" metal 1 "of the integrated circuit.) In the figure, the first and second levels of the structure, counted from the substrate 28, and are respectively designated PMD1 PMD2.

On observe que les éléments sur lesquels doivent être formés les interconnexions locales, à savoir les contacts de grilles de contrôle 10, 12, ainsi que les zones de contact pour les deuxième et troisième interconnexions locales 16, 20 précitées, sont recouvertes de CoSi2 (ces parties sont repérées par des hachures). It is noted that the elements that are to be formed local interconnects, i.e. contacts the control gates 10, 12 and the contact areas for the second and third local interconnections 16, 20 above, are covered CoSi2 (these parts are indicated by hatching). Le CoSi2 recouvre également d'autres éléments, notamment la grille de contrôle 20. The CoSi2 also includes other elements, including control gate 20.

Les reliefs verticaux sur la surface du substrat 28, constitués ici par les grilles de contrôle 10, 12, 20, sont bordés sur leur flancs par des éléments dits "espaceur" (plus connus par le terme anglais de "spacer") 38, dont les faces extérieures présentent des pentes. Vertical reliefs on the surface of substrate 28, here formed by the control gates 10, 12, 20 are bordered on their sides by the said elements "spacer" (better known by the English term "spacer") 38, which the outer surfaces have slopes. Les espaceurs sont ici formés par un bicouche oxyde-nitrure gravé de manière anisotropique. The spacers are here formed by an oxide-nitride bi-layer etched anisotropically.

Initialement, le premier niveau PMD1 est formé selon les étapes suivantes: Al. Formation préalable d'une couche de siliciure de cobalt (CoSi2), comprenant: A1.1. Initially, the first level PMD1 is formed in the following steps:. Al prior formation of a cobalt silicide layer (CoSi 2), comprising: A1.1. le dépôt d'une couche de cobalt, ou autre conducteur équivalent, sur l'ensemble de la partie exposée du substrat semiconducteur 6, après nettoyage de celle-ci; depositing a cobalt layer, or other conductive equivalent, on the entire exposed portion of the semiconductor substrate 6, after cleaning thereof; A1.2. A1.2. un recuit rapide de cette couche enrobée, (connu par l'acronyme anglais de RTP, pour "Rapid Thermal Processing") ; rapid annealing of the coated layer (known by the acronym of RTP for "Rapid Thermal Processing"); A1.3. A1.3. le retrait sélectif par voie humide d'une partie de la couche, soit du cobalt non réagi et du TiN. selectively removing wet a portion of the layer or the unreacted cobalt and TiN.

A2. A2. Dépôt de la couche PMD1, comprenant: A2.1. Deposition of the layer PMD1 comprising: A2.1. le dépôt d'une couche en nitrure, du type connu par le terme anglais de "borderless nitride" (traduction littérale: "nitrure sans bordure") ; depositing a nitride layer, of the type known by the English term "borderless nitride" (literal translation: "Borderless nitride"); A2.2. A2.2. le dépôt d'oxyde de silicium SiO2 en utilisant par exemple une technique de dépôt chimique sub-atmosphérique en phase vapeur (connu par l'acronyme anglais SACVD, pour "Sub-Atmospheric Chemical Vapour Deposition"), ou de dépôt chimique en phase vapeur renforcé par plasma (connu par l'acronyme anglais PECVD, pour "Plasma-Enhanced Chemical Vapour Deposition), ou de dépôt en plasma à haute densité (connu par l'acronyme anglais HOP, pour "High density plasma), etc. SiO2 silicon oxide deposition using for example a technique for sub-atmospheric chemical vapor deposition (known by the acronym SACVD to "Sub-Atmospheric Chemical Vapor Deposition"), or chemical vapor deposition plasma enhanced (known by the acronym PECVD for "plasma-enhanced Chemical Vapor deposition), or high density plasma deposition (known by the acronym HOP, for" high density plasma), etc. Selon l'application, ce dépôt peut être soit non dopé, soit dopé. Depending on the application, this deposit can be either undoped or doped. Dans ce dernier cas, le matériau de dopage peut être, à titre d'exemple, du bore et du phosphore formant un dépôt connu par l'acronyme anglais BPSG, pour "Boron/Phosphorous-Doped Silicon Glass") ; In the latter case, the doping material can be, for example, boron and phosphorus forming a deposit known by the acronym BPSG, for "Boron / Phosphorous-Doped Silicon Glass"); et A2.3. and A2.3. une étape de densification de la couche PMD1 ainsi formée, avec transformation du matériau CoSi en CoSi2. a step of densifying the PMD1 layer thus formed, with transformation CoSi material CoSi2.

A.2.4. A.2.4. un polissage ou de planarisation mécano- chimique (connu par l'acronyme anglais CMP, pour "Chemical-Mechanical Polising/Planarisation")de l'oxyde. polishing or planarization chemical mechanical (known by the acronym CMP, to "Chemical-Mechanical Polising / Planarization") of the oxide. Cette étape permet d'obtenir une couche PMD plane. This step allows to obtain a PMD planar layer.

A3. A3. Photolithographie et gravure du motif des interconnexions locales avec remplissage du motif par du tungstène. Photolithography and etching of the local interconnect pattern with filling pattern by tungsten. Cette phase permet de définir, par un masque approprié, les "plugs" et les tranchées de la l'interconnexion locale. This phase set by a suitable mask, the "plugs" and the trenches of the local interconnection. Elle comprend les étapes suivantes. It includes the following steps.

A3.1. A3.1. une photolithographie pour la formation du motif de résine photosensible 26 (cf. figures 2a et 2b) ; photolithography for forming the resist pattern 26 (see Figures 2a and 2b); A3.2. A3.2. une gravure sèche (par plasma) des interconnexions locales (cf. figures 2c et 2d), avec arrêt critique sur le CoSi2 et/ou sur la tranchée d'isolation STI 3 servant à isoler les zones actives entre elles A3.3. dry etching (plasma) of local interconnections (see Figures 2c and 2d), with critical judgment on the CoSi2 and / or the trench isolation STI 3 for isolating the active regions therebetween A3.3. le retrait de la résine; removal of the resin; A3.4. A3.4. la réalisation d'un dépôt barrière (couche conductrice) sur toute la plaquette, réalisée en bicouche, par exemple avec du Ti/TiN, entrant dans les contacts (tranchées ou "plugs"). producing a barrier deposit (conductive layer) over the entire wafer, performed bilayer, for example with Ti / TiN, entering the contacts (trenches or "plugs"). Plus particulièrement, cette couche très fine, typiquement de 200 Angstrom au total, se dépose au fond des contacts et surtout sur les flancs de ces derniers; More particularly, this very thin layer, typically 200 Angstroms in total deposits at the bottom of the contacts and especially on the sides thereof; A3.5. A3.5. le dépôt de tungstène formant les éléments conducteurs 14 et 20, ainsi que la partie du "plug" 18 sur l'étendu de la section verticale du diélectrique pré-métallique PMD1; depositing tungsten forming the conductive elements 14 and 20 as well as the part of the "plug" 18 of the extent of the vertical section of the pre-metal dielectric PMD1; et A3.6. and A3.6. le polissage/la planarisation mécanochimique utilisant une technique CMP comme pour l'étape A.2.4 supra. polishing / planarization using the mechanochemical a CMP technique as in step A.2.4 supra. Cette étape a pour but d'enlever par usinage le tungstène qui se trouve au- dessus de l'oxyde afin de ne le laisser que dans les "plugs" et dans les tranchées. This step is intended to remove by machining tungsten which is above the oxide so as to leave it only in the "plugs" and in the trenches.

A l'issu de ces étapes, il ne subsiste du tungstène que dans les tranchées 14 et dans les "plugs" 18 de l'interconnexion locale. At the end of these steps, there remains tungsten in the trenches 14 and the "plugs" of 18 local interconnection. A partir de cette préparation, on réalise le second niveau diélectrique PMD2, constitué d'un ensemble de "plugs" destiné à la connexion sélective des parties du tungstène du premier diélectrique avec la première métallisation 34, désigné métal 1. From this preparation, there is provided the second dielectric level PMD2, consisting of a set of "plugs" for selectively connecting portions of the first tungsten dielectric with the first metallization 34, designated 1 metal.

Pour ce faire, on dépose à nouveau une couche pré-métallique (soit diélectrique) servant à définir les connexions. To do this, is deposited again a pre-metal layer (or dielectric) for defining connections. Cette seconde couche prémétallique ne définit que des "plugs". This second layer premetal defines as "plugs". Ces derniers sont destinés à relier le métal 1 avec soit les "plugs" du niveau PMD1, soit les lignes réalisées par le premier dépôt de tungstène. These are for connecting the metal 1 with either the "plugs" of PMD1 level or lines created by the first deposition of tungsten.

Le second niveau PMD2 est réalisé par les étapes suivantes, consistant à former les "plugs" : 4.1. The second level PMD2 is formed by the steps comprising forming the "plugs": 4.1. un dépôt d'oxyde de silicium SiO2 qui, comme pour le premier niveau PMD1, peut être non dopé ou dopé, le dopage dans ce dernier cas pouvant être avec du bore et du phosphore pour former la composition BPSG précitée; a SiO2 silicon oxide deposit, as for the first level PMD1 may be undoped or doped, doping in the latter case may be with boron and phosphorus to form the aforementioned BPSG composition; 4.2. 4.2. si le dépôt est dopé, une densification de ce dépôt, par exemple de BPSG; if the deposit is doped, a densification of the deposit, for example BPSG; 4.3. 4.3. une photolithographie afin de définir les trous pour les "plugs"; photolithography to define the holes for the "plugs"; 4.4. 4.4. une gravure des "plugs" ; etching of "plugs"; et 4.5. and 4.5. le retrait de la résine utilisée lors de la gravure. the shrinkage of the resin used in the etching.

Concernant l'ensemble de ce processus classique de fabrication des connexions locales, on remarque que l'étape de photolithographie est très critique et nécessite un masque coûteux, s'agissant d'un masque à décalage de phase, spécialement conçu pour définir des motifs très fins. Regarding all of the conventional process of making local connections, we note that the photolithography step is very critical and requires expensive mask, with regard to a phase shift mask, specially designed to define patterns very purposes.

Au niveau de la gravure, un point de criticité très élevé dans l'exemple de la figure 3 est indiqué par le repère A, situé au bord de la tranchée 3 et du substrat 28, soit à l'arrêt de la gravure. At the etching, a very high criticality point in the example of Figure 3 is indicated at A, located at the edge of the trench 3 and the substrate 28, or the stopping of etching. En effet, ce masque doit définir simultanément, pour un même niveau et avec un même masque, des ouvertures à la fois en forme de tranchée et en forme de trou, pour les "plugs". Indeed, this mask is set simultaneously to the same level and with the same mask, openings both in the form of trench-shaped hole, for the "plugs".

L'étape de photolithogravure est également très critique, car elle nécessite d'être hautement sélective, à la fois: - par rapport au siliciure de cobalt (CoSi2), celui-ci se présentant sous forme d'une couche métallique formée sélectivement sur les zones actives et sur les lignes de polysilicium, afin de réduire les résistances de ligne de contact, et - par rapport à l'oxyde de la tranchée d'isolation STI 3, s'agissant d'un oxyde de champ servant à isoler entre elles les zones actives 2, 4 (cf. repère A de la figure 3). The photolithographic step is also very critical, since it needs to be highly selective, both: - with respect to the cobalt silicide (CoSi 2), the latter being in the form of a metal layer selectively formed on the active areas and the polysilicon lines, to reduce the contact line resistances, and - with respect to the oxide of the STI isolation trench 3 in the case of a field oxide for isolating them the active areas 2, 4 (see item A of Figure 3).

En effet, une sur-gravure du cobalt ou de l'oxyde en bord du tranché d'isolation précité peut provoquer des courants de fuite, par fuite de jonction, destructeurs pour le circuit. Indeed, over-etching of the cobalt oxide or board sliced ​​aforementioned insulation can cause leakage currents, by junction leakage, destructive to the circuit.

De plus, il est pénalisant d'avoir recours à un second dépôt de diélectrique pré-métallique (cf. phase 4 supra) afin de permettre d'établir un contact entre le tungstène de l'interconnexion avec l'aluminium du métal 1. In addition, it is detrimental to have recourse to a second deposit of pre-metal dielectric (cf. step 4 supra) in order to allow to establish a contact between the tungsten interconnection with aluminum metal 1.

Au vu de ce qui précède, l'invention propose une nouvelle approche permettant de réaliser notamment des connexions conductrices avec une simplification par rapport à l'état de la technique, entre autres au niveau des masques. In view of the above, the invention provides a new approach to achieve such conductive connections with simplified compared to the prior art, among others in masks.

Dans le mode de réalisation qui sera décrit, l'invention permet la suppression d'une gravure critique à sec au niveau des lignes locales d'interconnexion, en la remplaçant par une attaque humide sélective masquée du métal déposé, en l'occurrence du cobalt dans l'exemple décrit. In the embodiment to be described, the invention allows the removal of a dry etching critical in local interconnect lines, replacing it by a masked selective wet etching of the deposited metal, in this case cobalt in the example described.

Plus particulièrement, l'invention prévoit, selon un premier aspect, un procédé de réalisation d'au moins une connexion électriquement conductrice reliant sélectivement des éléments sur un substrat de circuit intégré, caractérisé en ce qu'il comprend les étapes de: - réaliser lesdits éléments sur un substrat dont au moins une portion de la surface est constituée d'un premier matériau, - déposer, sur le substrat et lesdits éléments, au moins un deuxième matériau, qui est conducteur et susceptible de créer une réaction avec le premier matériau pour former un matériau conducteur à la surface du substrat, - traiter le substrat pour réaliser ladite réaction, - réaliser un retrait sélectif du deuxième matériau n'ayant pas réagi avec ledit premier matériau, pour laisser du deuxième matériau selon un motif qui correspond à au moins une partie de la connexion. More particularly, the invention provides, in a first aspect, a method for producing at least one electrically conductive connection selectively connecting elements on an integrated circuit substrate characterized in that it comprises the steps of: - making said elements on a substrate at least a portion of the surface consists of a first material, - depositing on the substrate and said elements, at least one second material which is conductive and capable of creating a reaction with the first material to forming a conductive material to the substrate surface, - processing the substrate to carry out said reaction, - achieve selective removal of the second material unreacted with said first material, to leave the second material in a pattern corresponding to at least a part of the connection.

Avantageusement, le retrait sélectif du deuxième matériau n'ayant pas réagi est réalisé par au moins un masque définissant ledit motif, par exemple en utilisant une technique de gravure par voie humide. Advantageously, the selective removal of the second material unreacted is conducted by at least one mask defining said pattern, for example using a technique of wet etching. Dans ce cas, le retrait sélectif peut être réalisé par immersion du substrat et de son masque dans un bain. In this case, selective removal may be achieved by immersing the substrate and the mask in a bath.

Dans le mode de réalisation, au moins une connexion relie un desdits éléments à une aire du substrat rendue conductrice par ladite réaction entre le premier et le deuxième matériau. In the embodiment, at least one connection connects one of said elements to an area of ​​the conductive substrate made by said reaction between the first and the second material.

Au moins une aire du substrat rendue conductrice par ladite réaction entre le premier et le deuxième matériau peut être utilisée comme point de base pour un contact par trou, connu par le terme anglais de "plug", permettant une connexion vers un point de contact superposé. At least one area of ​​the rendered conductive substrate by said reaction between the first and the second material can be used as a base point for a contact hole, known by the English term "plug" allowing a connection to a point of superimposed contact .

De préférence, le retrait sélectif réalise de multiples connexions. Preferably, the selective removal takes multiple connections.

Avantageusement, la connexion est réalisée sous forme de ligne/les connexions sont réalisées uniquement sous forme de lignes. Advantageously, the connection is designed as a line / connections are made only in the form of lines.

Le masque peut alors comporter un motif uniquement de ligne(s) pour définir la ou chaque connexion. The mask may then comprise a pattern only line (s) to define the or each connection.

Le masque peut être formé par une technique de photolithographie. The mask can be formed by a photolithography technique.

Ladite étape de traitement peut comprendre un traitement thermique rapide, connu par l'acronyme anglais RTP, pour "Rapid Thermal Processing". Said processing step may include a rapid thermal processing, known by the acronym RTP for "Rapid Thermal Processing".

Le deuxième matériau déposé, ou l'un au moins des matériaux déposés, peut être un métal, par exemple un métal réfractaire. The second material deposited, or at least one of the deposited materials may be a metal, for example a refractory metal. Dans ce dernier cas, le métal réfractaire peut être au moins l'un parmi du cobalt, du titane, du nickel. In the latter case, the refractory metal may be at least one of cobalt, titanium, nickel.

L'étape de dépôt d'au moins un deuxième matériau peut, selon une option avantageuse, consister à déposer un bicouche formé d'une première composante qui est recouverte, ou encapsulée, par une deuxième composante, différente le la première. The step of depositing at least one second material may, according to an advantageous option, include depositing a bilayer consisting of a first component which is coated, or encapsulated by a second component, the first different.

Si cette option est utilisée, la première composante du bicouche peut comprendre, entre autres, du cobalt, et la seconde composante, qui la recouvre ou la l'encapsule, peut comprendre, entre autres, du titane (Ti), la première composante étant en contact avec le premier matériau. If this option is used, the first component of the bilayer can comprise, among others, cobalt, and the second component, which covers or encapsulates may comprise, inter alia, titanium (Ti), the first component being in contact with the first material.

Ledit premier matériau formant au moins une portion de ladite surface exposée du substrat peut être du silicium. Said first material forming at least a portion of said exposed surface of the substrate may be silicon. Dans ce cas, le matériau conducteur formé par ladite réaction peut être un siliciure. In this case, the conductive material formed by said reaction can be a silicide. Dans ce dernier cas, le siliciure peut être au moins l'un parmi: un siliciure de cobalt (CoSi), un siliciure de titane, un siliciure de nickel. In the latter case, the silicide may be at least one of: a cobalt silicide (CoSi), a titanium silicide, a nickel silicide.

Le procédé peut comprendre en outre la réalisation d'une structure dite diélectrique pré-métallique (PMD) unique comprenant au moins un contact par trou, connu par le terme anglais de "plug", permettant une connexion vers un point de contact superposé destiné à relier des points de ladite connexion électrique avec un niveau de métallisation. The method may further include performing a pre-metal dielectric said structure (PMD) comprising at least a single contact hole, known by the English term "plug" allowing a connection to a superimposed point of contact for connecting points of said electrical connection with a metallization level.

La ou chaque connexion électrique ainsi réalisée peut former une connexion locale s'étendant sur de courtes distances à l'échelle du circuit intégré. The or each electrical connection can thus produced forming a local connection extending over short distances on the scale of the integrated circuit.

Selon un second aspect, l'invention concerne en outre un circuit intégré comprenant au moins une connexion électriquement conductrice reliant sélectivement des éléments sur son substrat, dont au moins une portion de la surface est constitué d'un premier matériau, caractérisé en ce que la connexion est réalisée par un motif formé par au moins un deuxième matériau qui est conducteur, ce deuxième matériau formant en outre au moins une région conductrice sur la substrat par réaction avec le premier matériau de ce dernier. According to a second aspect, the invention further relates to an integrated circuit comprising at least one electrically conductive connection selectively connecting elements on its substrate, at least a portion of the surface consists of a first material, characterized in that the connection is made by a pattern formed by at least one second material which is conductive, said second material further forming at least one conductive region on the substrate by reacting with the first material of the latter. Le second matériau peut être du nitrure de titane. The second material may be titanium nitride.

Les aspects optionnels présentés dans la cadre du procédé selon le premier objet, peuvent s'appliquer mutatis mutandis à ce circuit intégré selon le second objet, et ne seront pas repris ici par souci de concision. The optional aspects presented in the context of the process according to the first object can be applied mutatis mutandis to this integrated circuit according to the second object, and will not be repeated here for brevity.

L'invention et les avantages qui en découlent apparaîtront plus clairement à la lecture des modes de réalisation préférés, donnés purement à titre d'exemples non-limitatifs, par référence aux dessins annexés, dans lesquelles: - la figure 1, déjà décrite, est une vue de plan d'un exemple d'interconnexions à un niveau local d'une zone d'un circuit intégré, les figures 2a à 2d, déjà décrites, sont des vues en coupe simplifiées montrant les étapes 0 successives intervenant lors d'une opération de photolithographie et de gravure sur un substrat en silicium, utilisée notamment lors de la réalisation d'interconnexions à un niveau local, la figure 3, déjà décrite, est une vue en coupe selon la ligne III-III' de la zone du circuit de la figure 1, pour le cas d'une structure d'interconnexions à un niveau local réalisée selon une technique classique à deux niveaux de diélectrique pre-métal, et - les figures 4a à 4g sont des vues en coupe d'une portion de plaq The invention and the advantages thereof appear more clearly on reading the preferred embodiments, given by way of non-limiting examples, with reference to the accompanying drawings in which: - Figure 1, already described, a plan view of an example of interconnections to a local level of an area of ​​an integrated circuit, figures 2a to 2d, already described, are schematic sectional views showing the sequential steps involved in a 0 operation of photolithography and etching on a silicon substrate, used in particular during the production of interconnections at a local level, Figure 3, already described, is a sectional view along the line III-III 'in circuit area of Figure 1, for the case of an interconnect structure at a local level realized by a conventional technique to two pre-metal dielectric levels, and - figures 4a to 4g are cross-sectional views of a portion of plat uette silicium sur laquelle sont formées des interconnexions locales conformément au mode de réalisation préféré de l'invention, montrant l'évolution de la fabrication à travers des étapes successives. uette silicon on which are formed of local interconnections according to the preferred embodiment of the invention, showing the evolution of the manufacture through successive steps.

Le mode de réalisation préféré de l'invention est décrit dans le cadre de connexions locales sur un substrat en silicium, en reprenant l'exemple de la topographie de la figure 1. The preferred embodiment of the invention is described in connection with local connections on a silicon substrate, using the example of the topography of Figure 1.

Dans ce contexte, l'invention permet d'éliminer le niveau critique que constitue l'utilisation d'un type particulier de masque utilisé classiquement pour réaliser l'interconnexion au niveau local LIL, celuici devant, dans l'état de la technique, définir à la fois des trous et des tranchés. In this context, the invention eliminates the critical level that constitutes the use of a particular type of mask used typically to realize interconnection locally LIL latter front, in the state of the art set both holes and trenches.

Dans l'exemple, cette élimination est obtenue, inter alla, par une exploitation judicieuse d'un matériau, ici sous forme d'un bicouche, pour réaliser les chemins conducteurs des interconnexions de niveau local. In the example, this elimination is obtained, inter alla, by judicious use of a material, here in the form of a bilayer to realize the conductive paths local level interconnects. (Par contraste, dans l'état de la technique, lorsqu'un bicouche est utilisé, celui-ci ne sert qu'à former les points de contact, lesquels sont recouverts par des tranchées de tungstène formant les chemins conducteurs de l'interconnexion). (By contrast, in the prior art, when a bi-layer is used, it only serves to form the contact points, which are covered with tungsten trenches forming the conductive paths interconnect) . Ainsi, on utilise la propriété conductrice d'un bicouche, en l'occurrence le couple cobalt/TiN, pour supprimer le niveau local d'interconnexion LIL. Thus, the conductive property is used a two-layer, namely the couple cobalt / TiN to suppress the local interconnect LIL.

Le bicouche ainsi utilisé conformément au mode de réalisation sert à réduire la résistance des contacts et la résistance des lignes, s'agissant d'une couche équipotentielle. The bilayer and used according to the embodiment serves to reduce the contact resistance and the line resistance, in relation to an equipotential layer.

L'ensemble des étapes du présent mode de réalisation de l'invention est représentée par les figures 4a à 4g, qui reprennent comme élément de base la structure d'interconnexion locale représenté à la figure 1. Les parties structurelles de ces figures déjà décrites dans le cadre des figures précédentes ne seront pas répétées, et portent les mêmes références que ces dernières. All the steps of this embodiment of the invention is shown in Figures 4a to 4g, which take as a basic element the local interconnect structure shown in Figure 1. The structural parts of these figures already described in as part of the previous figures will not be repeated, and the same references as the latter. Pour les mêmes raisons, toute étape de fabrication utilisée également dans le mode de réalisation de l'état de la technique et déjà décrite (cf. figures 2a-2d, 3) ne sera pas décrite à nouveau. For the same reasons, any manufacturing step also used in the embodiment of the prior art and already described (cf. Figures 2a-2d, 3) will not be described again.

La figure 4a reprend la configuration décrite dans le cadre de la figure 3, en ce qui concerne le substrat de silicium 28 constituant la plaquette, la tranchée d'isolation STI 3 constituant l'oxyde de champ, les grilles de contrôle 10, 12, 20 des transistors MOS, et les espaceurs de nitrure 38. Figure 4a shows the configuration described in connection with Figure 3, as regards the silicon substrate 28 constituting the wafer, the trench isolation STI 3 forming the field oxide, the control gates 10, 12, MOS transistors 20, and the nitride spacers 38.

Cette configuration initiale est obtenue selon des techniques classiques. This initial configuration is achieved using conventional techniques.

A partir de cette base, on procède à un nettoyage approprié de la surface de la plaquette 28. From this basis, we proceed to an appropriate cleaning of the surface of the wafer 28.

Ensuite, comme le montre la figure 4b, on dépose un bicouche 42 sur l'ensemble de la surface de la plaquette (ou du moins sur au moins une zone de sa surface destinée à recevoir des interconnexions locales si possible). Then, as shown in Figure 4b, a bilayer 42 is deposited on the entire surface of the wafer (or at least on at least one region of its surface for receiving local interconnections if possible). Dans l'exemple, ce bicouche 42 est réalisé par dépôt d'une fine couche de cobalt 44 avec une couche de nitrure de titane (TiN) 46. Cette dernière constitue une couche d'enrobage, ou d'encapsulation, de la couche de cobalt 44. In the example, this bilayer 42 is formed by deposition of a thin cobalt layer 44 with a titanium nitride layer (TiN) 46. The latter constitutes a coating layer, or encapsulating, the layer cobalt 44.

Une transformation par recuit rapide (connu par l'acronyme anglais RTP, pour "Rapid Thermal Processing") est ensuite effectuée pour faire réagir le cobalt avec le silicium en contact de la plaquette 28, pour y former du siliciure de cobalt (CoSi). Transformation by rapid thermal annealing (known by the acronym RTP for "Rapid Thermal Processing") is then performed to react the cobalt with the silicon in contact with the wafer 28, to form cobalt silicide (CoSi).

Comme le montre la figure 4c, le CoSi n'est donc formé qu'aux endroits où le cobalt 44 a été en contact avec le silicium. As shown in Figure 4c, the CoSi is therefore formed only where the cobalt 44 was in contact with silicon. Ainsi, il ne se forme pas sur les surfaces comprenant de l'oxyde ou du nitrure, notamment sur les portions constituées par les espaceurs 38 et sur l'oxyde de champ 3 constitué par la tranchée d'isolation (STI). Thus, it is not formed on the surfaces comprising the oxide or nitride, including the portions formed by the spacers 38 and the field oxide 3 formed by the trench isolation (STI). Dans ces portions, le cobalt non réagi reste à l'état métallique pur. In these portions, the unreacted cobalt remains in a pure metallic state.

On obtient ainsi deux zones de formation de CoSi - une première zone 48 sur les éléments de silicium en relief, en l'occurrence le sommet des grilles de contrôle 10, 12, 20, et - une seconde zone 50 au niveau du silicium du substrat. There is thus obtained two forming zones CoSi - a first region 48 of the raised silicon elements, in this case the top of the control gates 10, 12, 20, and - a second zone 50 at the silicon substrate .

Ces zones 48, 50 laissent exposées en surface la couche conductrice de TiN. These areas 48, 50 leave the conductive surface exposed layer of TiN.

Globalement, le bicouche 42, ayant réagi ou pas, reste conducteur. Overall, the bilayer 42, reacted or not, remains conductive.

De la sorte, on peut former la topographie de l'ensemble des lignes d'interconnexion locale en utilisant le bicouche, par retrait sélectif des portions de celui-ci non affectées aux lignes conductrices. In this way, the topography can be formed of all the local interconnection lines using the bilayer, by selective removal of portions thereof unallocated to the conductive lines.

Conformément au mode de réalisation, ce retrait sélectif est réalisé non pas en pleine plaque, mais en plaque masquée. According to the embodiment, this selective removal is carried out not in full plate, but masked plate. De manière remarquable, il suffit alors de masquer les zones que l'on souhaite relier électriquement, puis de plonger la plaquette dans le bain de retrait sélectif. Remarkably, it is sufficient to mask the areas which it is desired to connect electrically, and then to immerse the wafer in bath of selective withdrawal. Le cobalt et le TiN ne seront retirés qu'aux endroits où la résine est ouverte (exposée). Cobalt and TiN will be removed only where the resin is opened (exposed).

On garde ainsi le bicouche cobalt/TiN 42 dans les zones protégées par la résine, et obtient alors une interconnexion électrique basse impédance qui correspond fonctionnellement au niveau local d'interconnexion obtenu selon les techniques classiques. It thus retains the bilayer cobalt / TiN 42 in the areas protected by the resin, and then obtains a low impedance electrical interconnection which functionally corresponds to the local interconnect level obtained according to conventional techniques.

Pour ce faire, le mode de réalisation met en oeuvre une photolitographie selon le principe présenté par référence à la figure 2. Dans le cas d'espèce, le retrait sélectif s'opère par voie humide. To do this, the embodiment implements a photolithography according to the principle presented with reference to Figure 2. In this case, the selective removal is carried out by wet process.

Comme le montre la figure 4d, on dépose sur la structure de la figure 4c une couche de résine photo résiste 26, sur laquelle on appose un masque de photolithographie 22, dont les parties masquées 22a se situent à l'aplomb des emplacements du circuit des lignes conductrices d'interconnexion à réaliser. As shown in Figure 4d, is deposited on the structure of Figure 4c a photo resist resin layer 26 on which is affixed a photolithography mask 22, the unmasked portions 22a are located at the plumb of the circuit locations of conductive interconnect lines to achieve. On note que cette étape de photolithographie correspond à l'inverse de celle utilisée classiquement pour la réalisation d'interconnexions locales, en ce sens que les ouvertures 24 définissent des lignes à la surface du substrat (et sur les éléments de faible relief, tels que les grilles, qui sont sensiblement dans le même plan focal), et non pas des tranchées et des trous. Note that the photolithography step is the inverse of that conventionally used for the realization of local interconnections in the sense that the openings 24 define rows to the substrate surface (and the low relief elements, such as grids, which are substantially in the same focal plane), not trenches and holes.

Comme le montre la figure 4e, à l'issu de l'exposition au rayonnement 30 à travers le masque de photolithographie 22, et du retrait sélectif de la résine 26, la résine restante définit un masque de gravure qui masque les emplacements destinés uniquement aux lignes d'interconnexion. As shown in Figure 4e, at the end of exposure to radiation 30 through the photolithography mask 22, and selectively removing the resin 26, the remaining resin defines an etch mask that masks the locations intended only for interconnection lines. On note que cette approche contraste avec le procédé conventionnel qui nécessite la réalisation de tranchées. Note that this approach contrasts with the conventional method which requires the completion of trenches.

Ensuite, on effectue un retrait chimique au moyen d'un bain humide qui est sélectif au CoSi, permettant de retirer, aux parties exposées par le masque de résine 26, le TiN et le cobalt n'ayant pas réagis lors du traitement thermique (ie se situant, dans le cas illustré, sur les espaceurs de nitrure 38 et sur les tranchées d'isolation STI 2). Then, a chemical removal is effected by means of a wet bath which is selective to the CoSi, for removing, the portions exposed by the resist mask 26, the TiN and cobalt have not reacted during the thermal treatment (ie lying, in the illustrated case, the nitride spacers 38 and the STI isolation trenches 2).

Comme le montre la figure 4f, ce retrait sélectif laisse ainsi des zones dites "siliciurées" 48, 50, dépourvues de TiN conducteur. As shown in Figure 4f, this selective removal and leaves said zones "silicided" 48, 50, devoid of conductive TiN.

Ensuite, on retire la résine du masque et on 35 effectue les opérations de déposition de diélectrique pré-métallique PMD et de formation des contacts sous forme de trous de contact 52 (plus connus par le terme anglais "plug") de la structure PMD, donnant le résultat illustré à la figure 4g. Then removed the resin mask and 35 performs the pre-metal PMD dielectric deposition operations and formation of contacts in the form of contact holes 52 (better known by the English term "plug") of the PMD structure, giving the result shown in Figure 4g. On note qu'un seul niveau de diélectrique pré-métallique PMD est nécessaire. Note that only one level of pre-metal dielectric PMD is required.

Plus particulièrement, ces opérations comprennent Il. In particular, these operations comprise it. Le dépôt de la couche unique de diélectrique pré-métallique PMD, comprenant: I1.1. The deposition of the single layer pre-metal dielectric PMD comprising: I1.1. la réalisation de plages de contact en nitrure, du type sans bordure (connu par le terme anglais de "borderless nitride"; I1.2. le dépôt d'oxyde de silicium SiO2, soit sans dopage, soit avec dopage. Dans ce dernier cas, on peut utiliser, entre autres, un dopage de bore et de phosphore pour obtenir du dioxyde de silicium dopé bore/phosphore, (connu par l'acronyme anglais BPSG, pour "Boron/Phosphorous-Doped Silicon Oxide"). Cela peut être obtenu en utilisant une technique de dépôt chimique subatmosphérique en phase vapeur (connu par l'acronyme anglais SACVD, pour "Sub-Atmospheric Chemical Vapour Deposition") ou par tout autre moyen adapté, comme le dépôt chimique en phase vapeur renforcé par plasma (connu par l'acronyme anglais PECVD, pour "Plasma-Enhanced Chemical Vapour Deposition), ou de dépôt en plasma à haute densité (connu par l'acronyme anglais HDP, pour "High-Density Plasma), etc. I1.3. une étape de densification de la couche unique de diélectrique pré-métalli achieving contact pads nitride, of the type without a border (known by the English term "borderless nitride";.. I1.2 the silicon oxide deposit SiO2 or without doping or with doping In the latter case can be used, among other things, doping of boron and phosphorus for silicon dioxide doped boron / phosphorus (known by the acronym BPSG, for "boron / phosphorous-doped silicon Oxide"). This can be obtained by using a chemical deposition technique subatmospheric vapor (known by the acronym SACVD to "Sub-Atmospheric chemical vapor deposition") or by any other suitable means, such as chemical vapor deposition, plasma enhanced (known by the acronym PECVD for "plasma-Enhanced Chemical Vapor deposition), or high density plasma deposition (known by the acronym HDP, for" high-density plasma), etc. I1.3. a step densification of the single layer of dielectric pre-METALLIC que ainsi formée, avec transformation du matériau CoSi en CoSi2. that thus formed, with transformation CoSi material CoSi2.

I2. I2. Photolithographie et gravure contact, comprenant: I2.1. Photolithography and etching contact comprising: I2.1. une photolithographie de type contact, I2.2. a contact type photolithography, I2.2. une gravure de type contact, et I2.3. a contact type etching, and I2.3. le retrait de la résine. removal of the resin.

De ce qui précède, on remarque que l'une des originalités du procédé réside dans le fait que l'on effectue un retrait sélectif du TiN et du cobalt, qui n'ont pas réagis lors du traitement thermique, en utilisant un retrait sélectif masqué, en l'occurrence par une étape de photolithographie. From the foregoing, it is noted that one of the original features of the method resides in the fact that one carries out the selective removal of the TiN and cobalt, which have not reacted during the thermal treatment, using a masked selective removal , in this case by a photolithography step.

Bien que le masque utilisé pour cette opération soit spécifique, il est moins critique que le masque utilisé classiquement pour obtenir les lignes locales d'interconnexion avec le tungstène. Although the mask used for this operation to be specific, it is less critical than the mask conventionally used for local interconnection lines with tungsten.

En effet, le masque pour le retrait sélectif utilisé conformément à l'invention n'a pas à définir à la fois des trous et des tranchés. Indeed, the mask for the selective removal used according to the invention need not define both holes and trenches. Ce masque ne définit que des lignes. This mask that defines the lines. Il n'y donc pas le problème lié à une profondeur de champ conséquente qui apparaît avec les reliefs constitués notamment par les trous. It is therefore no problem with the depth of field that appears consistent with the reliefs consist in particular through the holes.

L'invention peut être utilisée avec tout matériau pouvant former dusilicide. The invention may be used with any material capable of forming dusilicide. Le métal utilisé peut être, par exemple, du titane, du nickel, etc. The metal used may be, for example, titanium, nickel, etc. soit tout métal réfractaire qui entre la définition du siliciure. or any refractory metal silicide between the definition.

Par ailleurs, le siliciure peut être remplacé par d'autres compositions selon l'application envisagée, en apportant les adaptations qui s'imposent aux enseignements donnés dans le contexte de présente description donnée dans le cadre du siliciure. Furthermore, silicide may be replaced by other compositions depending on the intended application, by making the necessary adjustments to the teachings provided in the context of this description in the context of silicide.

Plus généralement, la technique venant d'être décrite peut être appliquée à tous les métaux réfractaires encapsulés (Ti, Ni, ....). More generally, the technique just described can be applied to all encapsulated refractory metals (Ti, Ni, ....).

Une application avantageuse de la technique conforme à l'invention est la fabrication de composant électroniques de faible consommation électrique, notamment pour véhiculer du signal. An advantageous application of the technique according to the invention is the electronic component manufacturing low power consumption, in particular to convey the signal.

Le procédé conforme à l'invention est remarquable en ce qu'il permet: - de passer d'un masque critique à décalage de phase à un masque critique standard (passage d'un masque où l'on défini des tranchées et des trous à un masque où l'on défini uniquement des lignes; - de supprimer la gravure du niveau local d'interconnexion, très critique au niveau des bords de zone d'oxyde de champ; - de réaliser le diélectrique pré-métallique en une seule fois, grâce à la suppression d'un niveau de diélectrique pré-métallique avec le dépôt de BPSG, dépôt espaceur, dépôt de tungstène et de tungstène avec polissage/planarisation chimico-mécanique. The process according to the invention is noteworthy in that it allows: - to move from a critical phase shift mask to a standard critical mask (passage of a mask which is defined trenches and holes a mask where only defined lines - to remove the etching of the local interconnect level, very critical at the field oxide region edge - to carry out the pre-metal dielectric in a single, by eliminating a level of pre-metal dielectric deposition with BPSG, spacer deposition, deposition of tungsten and tungsten with polishing / planarization chemical mechanical.

Claims (27)

Revendications claims
1. Procédé de réalisation d'au moins une connexion électriquement conductrice reliant sélectivement des éléments (2, 4, 10, 12) sur un substrat (28) de circuit intégré (8), caractérisé en ce qu'il comprend les étapes de: - réaliser lesdits éléments (2, 4, 10, 12) sur un substrat dont au moins une portion de la surface est constituée d'un premier matériau, déposer, sur le substrat et lesdits éléments, au moins un deuxième matériau, qui est conducteur (42, 44, 46) et susceptible de créer une réaction avec le premier matériau pour former un matériau conducteur à la surface du substrat, - traiter le substrat pour réaliser ladite réaction, - réaliser un retrait sélectif du deuxième matériau n'ayant pas réagi avec ledit premier matériau, pour laisser du deuxième matériau selon un motif qui correspond à au moins une partie de la connexion. 1. A method of making at least one electrically conductive connection selectively connecting the elements (2, 4, 10, 12) on a substrate (28) integrated circuit (8), characterized in that it comprises the steps of: - making said elements (2, 4, 10, 12) on a substrate at least a portion of the surface consists of a first material, depositing on the substrate and said elements, at least one second material, which is conductive (42, 44, 46) and adapted to create a reaction with the first material to form a conductive material to the substrate surface, - processing the substrate to carry out said reaction, - achieve selective removal of the second material unreacted with said first material, to leave the second material in a pattern corresponding to at least a portion of the connection.
2. Procédé selon la revendication 1, caractérisé en ce que le retrait sélectif du deuxième matériau n'ayant pas réagi est réalisé par au moins un masque (46) définissant ledit motif. 2. Method according to claim 1, characterized in that the selective removal of the second material unreacted is conducted by at least one mask (46) defining said pattern.
3. Procédé selon la revendication 1 ou 2, caractérisé en ce que le retrait sélectif du deuxième matériau n'ayant pas réagi est réalisé selon une technique de gravure par voie humide. 3. The method of claim 1 or 2, characterized in that the selective removal of the second material unreacted is produced using a technique of wet etching.
4. Procédé selon la revendication 3, caractérisé en ce que le retrait sélectif du deuxième matériau n'ayant pas réagi est réalisé par immersion du substrat (28) et de son masque (46) dans un bain. 4. A method according to claim 3, characterized in that the selective removal of the second material unreacted is conducted by immersing the substrate (28) and the mask (46) in a bath.
5. Procédé selon l'une quelconque des revendications 1 à 4, caractérisé en ce que au moins une connexion relie un desdits éléments (2, 4, 10, 12) à une aire du substrat rendue conductrice par ladite réaction entre le premier et le deuxième matériau. 5. A method according to any one of claims 1 to 4, characterized in that at least one connection connecting one of said members (2, 4, 10, 12) to an area of ​​the conductive substrate made by said reaction between the first and second material.
6. Procédé selon l'une quelconque des revendications 1 à 5, caractérisé en ce qu'au moins une aire du substrat rendue conductrice par ladite réaction entre le premier et le deuxième matériau est utilisée comme point de base pour un contact par trou, connu par le terme anglais de "plug", permettant une connexion vers un point de contact superposé. 6. A method according to any one of claims 1 to 5, characterized in that at least one area of ​​the conductive substrate made by said reaction between the first and the second material is used as a base point for a contact hole, known by the term "plug" allowing a connection to a bunk point of contact.
7. Procédé selon l'une quelconque des revendications 1 à 6, caractérisé en ce que le retrait sélectif réalise de multiples connexions. 7. A method according to any one of claims 1 to 6, characterized in that the selective removal takes multiple connections.
8. Procédé selon l'une quelconque des revendication 1 à 7, caractérisé en ce que la connexion est réalisée sous forme de ligne/les connexions sont réalisées uniquement sous forme de lignes. 8. A method according to any one of claims 1 to 7, characterized in that the connection is designed as a line / connections are made only in the form of lines.
9. Procédé selon l'une quelconque des revendications 2 à 8, caractérisé en ce que le masque (46) comporte un motif uniquement de ligne(s) pour 35 définir la ou chaque connexion. 9. A method according to any one of claims 2 to 8, characterized in that the mask (46) comprises a pattern only line (s) 35 to set the or each connection.
10. Procédé selon l'une quelconque des revendications 2 à 9, caractérisé en ce que le masque (46) est formé par une technique de photolithographie. 10. A method according to any one of claims 2 to 9, characterized in that the mask (46) is formed by a photolithography technique.
11. Procédé selon l'une quelconque des revendications 1 à 10, caractérisé en ce que ladite étape de traitement comprend un traitement thermique rapide, connu par l'acronyme anglais RTP, pour "Rapid Thermal Processing". 11. A method according to any one of claims 1 to 10, characterized in that said processing step comprises a rapid thermal treatment, known by the acronym RTP for "Rapid Thermal Processing".
12. Procédé selon l'une quelconque des revendications 1 à 11, caractérisé en ce que le deuxième matériau déposé (42, 44, 46), ou l'un au moins des matériaux déposés, est un métal. 12. A method according to any one of claims 1 to 11, characterized in that the second deposited material (42, 44, 46) or at least one of the deposited materials, is a metal.
13. Procédé selon l'une quelconque des 13. A method according to any one of
revendications 1 à 12, caractérisé en ce que le Claims 1 to 12, characterized in that the
deuxième matériau déposé (46) comprend un métal réfractaire. second deposited material (46) comprises a refractory metal.
14. Procédé selon l'une quelconque des 14. A method according to any one of
revendications 1 à 13, caractérisé en ce que le Claims 1 to 13, characterized in that the
deuxième matériau déposé (44) comprend au moins l'un parmi. second deposited material (44) comprises at least one.
- du cobalt, - du titane, - du nickel. - cobalt - titanium - nickel.
15. Procédé selon l'une quelconque des revendications 1 à 14, caractérisé en ce que l'étape de dépôt d'au moins un deuxième matériau consiste à déposer un bicouche (42) formé d'une première composante (44) qui est recouverte, ou encapsulée, par une deuxième composante (46), différente le la première. 15. A method according to any one of claims 1 to 14, characterized in that the step of depositing at least one second material comprises depositing a bilayer (42) formed of a first component (44) which is covered , or encapsulated by a second component (46), the different first.
16. Procédé selon la revendication 15, caractérisé en ce que la première composante (44) du bicouche comprend du cobalt, et en ce que la seconde composante, qui la recouvre ou l'encapsule, comprend du nitrure de titane (TiN), ladite première composante étant en contact avec le premier matériau. 16. The method of claim 15, characterized in that the first component (44) of the bilayer comprises cobalt, and in that the second component, which covers or encapsulates, comprises titanium nitride (TiN), said first component being in contact with the first material.
17. Procédé selon l'une quelconque de revendications 1 à 16, caractérisé en ce que ledit premier matériau formant au moins une portion de ladite surface exposée du substrat (28) est du silicium. 17. A method according to any one of claims 1 to 16, characterized in that said first material forming at least a portion of said exposed surface of the substrate (28) is silicon.
18. Procédé selon 1a revendication 17, caractérisé en ce que le matériau conducteur formé par ladite réaction est un siliciure. 18. The method 1a claim 17, characterized in that the conductive material formed by said reaction is a silicide.
19. Procédé selon la revendication 18, caractérisé en ce que ledit siliciure est au moins l'un parmi: - un siliciure de cobalt (CoSi), - un siliciure de titane, - un siliciure de nickel. 19. The method of claim 18, characterized in that said silicide is at least one of: - a cobalt silicide (CoSi), - a titanium silicide, - a nickel silicide.
20. Procédé selon l'une quelconque des 20. A method according to any one of
revendications 1 à 19, caractérisé en ce qu'il claims 1 to 19, characterized in that
comprend en outre la réalisation d'une structure dite diélectrique prémétallique (PMD) unique comprenant au moins un contact par trou, connu par le terme anglais de "plug", permettant une connexion vers un point de contact superposé (52) destiné à relier des points de ladite connexion électrique avec un niveau de métallisation (34). further comprises performing a premetal dielectric said structure (PMD) comprising at least a single contact hole, known by the English term "plug" allowing a connection to a superimposed point of contact (52) for connecting points of said electrical connection with a metallization level (34).
21. Procédé selon l'une quelconque des revendications 1 à 20, caractérisé en ce que la ou chaque connexion électrique ainsi réalisée est une connexion locale s'étendant sur de courtes distances à l'échelle du circuit intégré. 21. A method according to any one of claims 1 to 20, characterized in that the or each electrical connection is thus produced a local connection extending over short distances on the scale of the integrated circuit.
22. Circuit intégré (8) comprenant au moins une connexion électriquement conductrice reliant sélectivement des éléments (2, 4, 10, 12) sur son substrat (28), dont au moins une portion de la surface est constitué d'un premier matériau, caractérisé en ce que la connexion est réalisée par un motif formé par au moins un deuxième matériau qui est conducteur, ce deuxième matériau formant en outre au moins une région conductrice sur la substrat par réaction avec le premier matériau (28) de ce dernier. 22. An integrated circuit (8) comprising at least one electrically conductive connection selectively connecting the elements (2, 4, 10, 12) on the substrate (28), at least a portion of the surface consists of a first material, characterized in that the connection is made by a pattern formed by at least one second material which is conductive, said second material further forming at least one conductive region on the substrate by reacting with the first material (28) of the latter.
23. Circuit intégré selon la revendication 22, caractérisé en ce que le deuxième matériau (44) comprend du cobalt. 23. Integrated circuit according to Claim 22, characterized in that the second material (44) comprises cobalt.
24. Circuit intégré selon l'une quelconque des revendications 22 ou 23, caractérisé en ce que le deuxième matériau (46) comprend un métal réfractaire. 24. An integrated circuit according to any one of claims 22 or 23, characterized in that the second material (46) comprises a refractory metal.
25. Circuit intégré selon la revendication 24, caractérisé en ce que le deuxième matériau est du nitrure de titane (TiN). 25. Integrated circuit according to Claim 24, characterized in that the second material is titanium nitride (TiN).
26. Circuit intégré selon l'une quelconque des 26. An integrated circuit according to any one of
revendications 22 à 25, caractérisé en ce qu'il claims 22 to 25, characterized in that
comprend en outre une structure dite diélectrique pré-métallique (PMD) unique comprenant au moins un contact par trou, connu par le terme anglais de "plug", permettant une connexion vers un point de contact superposé (52) et destiné à relier des points de ladite connexion conductrice avec un niveau de métallisation (34). further comprises a dielectric pre-metal said structure (PMD) one comprising at least one contact hole, known by the English term "plug" allowing a connection to a superimposed point of contact (52) and for connecting points said conductive connection with a metallization level (34).
27. Circuit intégré selon l'une quelconque des revendications 22 à 26, caractérisé en ce que ladite connexion électrique est une connexion locales s'étendant sur de courtes distances à l'échelle du circuit intégré. 27. Integrated circuit according to any one of claims 22 to 26, characterized in that said electrical connection is a local connection extending over short distances on the scale of the integrated circuit.
FR0311987A 2003-10-14 2003-10-14 Multiple short local electrical connections for selective linkage of integrated circuit elements comprise masked selective humid attack of deposited metal Pending FR2860920A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR0311987A FR2860920A1 (en) 2003-10-14 2003-10-14 Multiple short local electrical connections for selective linkage of integrated circuit elements comprise masked selective humid attack of deposited metal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0311987A FR2860920A1 (en) 2003-10-14 2003-10-14 Multiple short local electrical connections for selective linkage of integrated circuit elements comprise masked selective humid attack of deposited metal

Publications (1)

Publication Number Publication Date
FR2860920A1 true FR2860920A1 (en) 2005-04-15

Family

ID=34355455

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0311987A Pending FR2860920A1 (en) 2003-10-14 2003-10-14 Multiple short local electrical connections for selective linkage of integrated circuit elements comprise masked selective humid attack of deposited metal

Country Status (1)

Country Link
FR (1) FR2860920A1 (en)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2206146A2 (en) * 2007-10-26 2010-07-14 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7932544B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US7943967B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8214778B2 (en) 2007-08-02 2012-07-03 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US8283701B2 (en) 2007-08-02 2012-10-09 Tela Innovations, Inc. Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008141A (en) * 1997-02-25 1999-12-28 Sanyo Electric Co., Ltd. Semiconductor device and fabrication method thereof
US20020102845A1 (en) * 2001-01-26 2002-08-01 Eric Lee Conformal surface silicide strap on spacer and method of making same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008141A (en) * 1997-02-25 1999-12-28 Sanyo Electric Co., Ltd. Semiconductor device and fabrication method thereof
US20020102845A1 (en) * 2001-01-26 2002-08-01 Eric Lee Conformal surface silicide strap on spacer and method of making same

Cited By (180)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9711495B2 (en) 2006-03-09 2017-07-18 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7932544B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US10217763B2 (en) 2006-03-09 2019-02-26 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid
US7943966B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Integrated circuit and associated layout with gate electrode level portion including at least two complimentary transistor forming linear conductive segments and at least one non-gate linear conductive segment
US7943967B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US7948012B2 (en) 2006-03-09 2011-05-24 Tela Innovations, Inc. Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment
US7948013B2 (en) 2006-03-09 2011-05-24 Tela Innovations, Inc. Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch
US7952119B2 (en) 2006-03-09 2011-05-31 Tela Innovations, Inc. Semiconductor device and associated layout having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch
US9673825B2 (en) 2006-03-09 2017-06-06 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7989847B2 (en) 2006-03-09 2011-08-02 Tela Innovations, Inc. Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths
US7989848B2 (en) 2006-03-09 2011-08-02 Tela Innovations, Inc. Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8022441B2 (en) * 2006-03-09 2011-09-20 Tela Innovations, Inc. Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level
US8030689B2 (en) 2006-03-09 2011-10-04 Tela Innovations, Inc. Integrated circuit device and associated layout including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear conductive segment
US8035133B2 (en) 2006-03-09 2011-10-11 Tela Innovations, Inc. Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch
US8058671B2 (en) * 2006-03-09 2011-11-15 Tela Innovations, Inc. Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch
US9589091B2 (en) 2006-03-09 2017-03-07 Tela Innovations, Inc. Scalable meta-data objects
US8072003B2 (en) 2006-03-09 2011-12-06 Tela Innovations, Inc. Integrated circuit device and associated layout including two pairs of co-aligned complementary gate electrodes with offset gate contact structures
US8089102B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Method for fabricating integrated circuit having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch
US8089103B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Integrated circuit device with gate level region including at least three linear-shaped conductive segments having offset line ends and forming three transistors of first type and one transistor of second type
US8089099B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc, Integrated circuit device and associated layout including gate electrode level region of 965 NM radius with linear-shaped conductive segments on fixed pitch
US8089098B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Integrated circuit device and associated layout including linear gate electrodes of different transistor types next to linear-shaped non-gate conductive segment
US8088681B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear condcutive segment
US8088680B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Method for fabricating integrated circuit having at least three linear-shaped gate electrode level conductive features of equal length positioned side-by-side at equal pitch
US8089100B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes
US8088679B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Method for fabricating integrated circuit with gate electrode level portion including at least two complementary transistor forming linear conductive segments and at least one non-gate linear conductive segment
US8089101B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Integrated circuit device with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level
US8088682B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level
US8089104B2 (en) 2006-03-09 2012-01-03 Tela Innovations, Inc. Integrated circuit with gate electrode level region including multiple linear-shaped conductive structures forming gate electrodes of transistors and including uniformity extending portions of different size
US8101975B2 (en) 2006-03-09 2012-01-24 Tela Innovations, Inc. Integrated circuit device with gate level region including non-gate linear conductive segment positioned within 965 nanometers of four transistors of first type and four transistors of second type
US8110854B2 (en) 2006-03-09 2012-02-07 Tela Innovations, Inc. Integrated circuit device with linearly defined gate electrode level region and shared diffusion region of first type connected to shared diffusion region of second type through at least two interconnect levels
US8129751B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes and including four conductive contacting structures having at least two different connection distances
US8129757B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length
US8129756B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two different extension distances beyond conductive contacting structures
US8129755B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit with gate electrode level including at least four linear-shaped conductive structures of equal length and equal pitch with linear-shaped conductive structure forming one transistor
US8129819B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Method of fabricating integrated circuit including at least six linear-shaped conductive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length
US8129754B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends
US8129753B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate portion
US8129750B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different length
US8129752B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit including a linear-shaped conductive structure forming one gate electrode and having length greater than or equal to one-half the length of linear-shaped conductive structure forming two gate electrodes
US8134184B2 (en) 2006-03-09 2012-03-13 Tela Innovations, Inc. Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion
US8134183B2 (en) 2006-03-09 2012-03-13 Tela Innovations, Inc. Integrated circuit including linear-shaped conductive structures that have gate portions and extending portions of different size
US10230377B2 (en) 2006-03-09 2019-03-12 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8134186B2 (en) 2006-03-09 2012-03-13 Tela Innovations, Inc. Integrated circuit including at least three linear-shaped conductive structures at equal pitch including linear-shaped conductive structure having non-gate portion length greater than gate portion length
US8138525B2 (en) 2006-03-09 2012-03-20 Tela Innovations, Inc. Integrated circuit including at least three linear-shaped conductive structures of different length each forming gate of different transistor
US8198656B2 (en) 2006-03-09 2012-06-12 Tela Innovations, Inc. Integrated circuit including gate electrode level region including at least four linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type
US8207053B2 (en) 2006-03-09 2012-06-26 Tela Innovations, Inc. Electrodes of transistors with at least two linear-shaped conductive structures of different length
US9859277B2 (en) 2006-03-09 2018-01-02 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8217428B2 (en) 2006-03-09 2012-07-10 Tela Innovations, Inc. Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8253172B2 (en) 2006-03-09 2012-08-28 Tela Innovations, Inc. Semiconductor device with linearly restricted gate level region including four serially connected transistors of first type and four serially connected transistors of second type separated by non-diffusion region
US8253173B2 (en) 2006-03-09 2012-08-28 Tela Innovations, Inc. Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region
US8258549B2 (en) 2006-03-09 2012-09-04 Tela Innovations, Inc. Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length
US8258551B2 (en) 2006-03-09 2012-09-04 Tela Innovations, Inc. Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction
US8258547B2 (en) 2006-03-09 2012-09-04 Tela Innovations, Inc. Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts
US8258548B2 (en) 2006-03-09 2012-09-04 Tela Innovations, Inc. Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region
US8258552B2 (en) 2006-03-09 2012-09-04 Tela Innovations, Inc. Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends
US8258550B2 (en) 2006-03-09 2012-09-04 Tela Innovations, Inc. Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact
US9443947B2 (en) 2006-03-09 2016-09-13 Tela Innovations, Inc. Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same
US9425272B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same
US8264008B2 (en) 2006-03-09 2012-09-11 Tela Innovations, Inc. Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size
US8264007B2 (en) 2006-03-09 2012-09-11 Tela Innovations, Inc. Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances
US9425145B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8264009B2 (en) 2006-03-09 2012-09-11 Tela Innovations, Inc. Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length
US9425273B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same
US8134185B2 (en) 2006-03-09 2012-03-13 Tela Innovations, Inc. Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends
US9336344B2 (en) 2006-03-09 2016-05-10 Tela Innovations, Inc. Coarse grid design methods and structures
US9905576B2 (en) 2006-03-09 2018-02-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first metal structures
US9741719B2 (en) 2006-03-09 2017-08-22 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9240413B2 (en) 2006-03-09 2016-01-19 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8436400B2 (en) 2006-03-09 2013-05-07 Tela Innovations, Inc. Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length
US9917056B2 (en) 2006-03-09 2018-03-13 Tela Innovations, Inc. Coarse grid design methods and structures
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US10186523B2 (en) 2006-03-09 2019-01-22 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US8952425B2 (en) 2006-03-09 2015-02-10 Tela Innovations, Inc. Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length
US8946781B2 (en) 2006-03-09 2015-02-03 Tela Innovations, Inc. Integrated circuit including gate electrode conductive structures with different extension distances beyond contact
US8921896B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit including linear gate electrode structures having different extension distances beyond contact
US8921897B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit with gate electrode conductive structures having offset ends
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8823062B2 (en) 2006-03-09 2014-09-02 Tela Innovations, Inc. Integrated circuit with offset line end spacings in linear gate electrode level
US10141335B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures
US10141334B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US9633987B2 (en) 2007-03-05 2017-04-25 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US10074640B2 (en) 2007-03-05 2018-09-11 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US9595515B2 (en) 2007-03-07 2017-03-14 Tela Innovations, Inc. Semiconductor chip including integrated circuit defined within dynamic array section
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9424387B2 (en) 2007-03-07 2016-08-23 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9910950B2 (en) 2007-03-07 2018-03-06 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8356268B2 (en) 2007-08-02 2013-01-15 Tela Innovations, Inc. Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings
US8549455B2 (en) 2007-08-02 2013-10-01 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8759882B2 (en) 2007-08-02 2014-06-24 Tela Innovations, Inc. Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
US8214778B2 (en) 2007-08-02 2012-07-03 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8283701B2 (en) 2007-08-02 2012-10-09 Tela Innovations, Inc. Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
US8756551B2 (en) 2007-08-02 2014-06-17 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8680626B2 (en) 2007-10-26 2014-03-25 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
EP2206146A2 (en) * 2007-10-26 2010-07-14 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
EP2206146A4 (en) * 2007-10-26 2011-01-05 Tela Innovations Inc Methods, structures and designs for self-aligning local interconnects used in integrated circuits
EP2592648A1 (en) * 2007-10-26 2013-05-15 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
EP2592649A1 (en) * 2007-10-26 2013-05-15 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7994545B2 (en) 2007-10-26 2011-08-09 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9281371B2 (en) 2007-12-13 2016-03-08 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9818747B2 (en) 2007-12-13 2017-11-14 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9530734B2 (en) 2008-01-31 2016-12-27 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8701071B2 (en) 2008-01-31 2014-04-15 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9202779B2 (en) 2008-01-31 2015-12-01 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8729606B2 (en) 2008-03-13 2014-05-20 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels
US8847329B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts
US8847331B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
US8836045B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
US8853793B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
US9245081B2 (en) 2008-03-13 2016-01-26 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US8866197B2 (en) 2008-03-13 2014-10-21 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature
US8872283B2 (en) 2008-03-13 2014-10-28 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
US8558322B2 (en) 2008-03-13 2013-10-15 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature
US8552508B2 (en) 2008-03-13 2013-10-08 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8552509B2 (en) 2008-03-13 2013-10-08 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors
US8564071B2 (en) 2008-03-13 2013-10-22 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact
US8835989B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications
US8569841B2 (en) 2008-03-13 2013-10-29 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel
US8816402B2 (en) 2008-03-13 2014-08-26 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor
US8785978B2 (en) 2008-03-13 2014-07-22 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer
US10020321B2 (en) 2008-03-13 2018-07-10 Tela Innovations, Inc. Cross-coupled transistor circuit defined on two gate electrode tracks
US9117050B2 (en) 2008-03-13 2015-08-25 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
US8785979B2 (en) 2008-03-13 2014-07-22 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer
US8853794B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit within semiconductor chip including cross-coupled transistor configuration
US8772839B2 (en) 2008-03-13 2014-07-08 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US9208279B2 (en) 2008-03-13 2015-12-08 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods
US9213792B2 (en) 2008-03-13 2015-12-15 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US8405162B2 (en) 2008-03-13 2013-03-26 Tela Innovations, Inc. Integrated circuit including gate electrode level region including cross-coupled transistors having at least one gate contact located over outer portion of gate electrode level region
US8405163B2 (en) 2008-03-13 2013-03-26 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
US8395224B2 (en) 2008-03-13 2013-03-12 Tela Innovations, Inc. Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes
US8592872B2 (en) 2008-03-13 2013-11-26 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
US8575706B2 (en) 2008-03-13 2013-11-05 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode
US8742463B2 (en) 2008-03-13 2014-06-03 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts
US9871056B2 (en) 2008-03-13 2018-01-16 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US8274099B2 (en) 2008-03-13 2012-09-25 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
US8264049B2 (en) 2008-03-13 2012-09-11 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
US8264044B2 (en) 2008-03-13 2012-09-11 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having two complementary pairs of co-aligned gate electrodes with offset contacting structures positioned between transistors of different type
US8742462B2 (en) 2008-03-13 2014-06-03 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications
US8258581B2 (en) 2008-03-13 2012-09-04 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors with two transistors of different type formed by same gate level structure and two transistors of different type formed by separate gate level structures
US8735944B2 (en) 2008-03-13 2014-05-27 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors
US8735995B2 (en) 2008-03-13 2014-05-27 Tela Innovations, Inc. Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track
US8729643B2 (en) 2008-03-13 2014-05-20 Tela Innovations, Inc. Cross-coupled transistor circuit including offset inner gate contacts
US8680583B2 (en) 2008-03-13 2014-03-25 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels
US8058691B2 (en) 2008-03-13 2011-11-15 Tela Innovations, Inc. Semiconductor device including cross-coupled transistors formed from linear-shaped gate level features
US8669594B2 (en) 2008-03-13 2014-03-11 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels
US8669595B2 (en) 2008-03-13 2014-03-11 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8581303B2 (en) 2008-03-13 2013-11-12 Tela Innovations, Inc. Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer
US8587034B2 (en) 2008-03-13 2013-11-19 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US9536899B2 (en) 2008-03-13 2017-01-03 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US8581304B2 (en) 2008-03-13 2013-11-12 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships
US9081931B2 (en) 2008-03-13 2015-07-14 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
US9779200B2 (en) 2008-03-27 2017-10-03 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9390215B2 (en) 2008-03-27 2016-07-12 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8471391B2 (en) 2008-03-27 2013-06-25 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8759985B2 (en) 2008-03-27 2014-06-24 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9269702B2 (en) 2009-10-13 2016-02-23 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the same
US9530795B2 (en) 2009-10-13 2016-12-27 Tela Innovations, Inc. Methods for cell boundary encroachment and semiconductor devices implementing the same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9704845B2 (en) 2010-11-12 2017-07-11 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same

Similar Documents

Publication Publication Date Title
US6720262B2 (en) Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst
EP1812977B1 (en) Electroless plating of metal caps for chalcogenide-based memory devices
JP2996946B2 (en) A method of forming a self-aligned copper diffusion barrier in vias
JP4117672B2 (en) A solid-state imaging device and a solid-state imaging device, and a method for their preparation
JP5430946B2 (en) Interconnect structure forming method
JP4123060B2 (en) A solid-state imaging device and a manufacturing method thereof
US6910907B2 (en) Contact for use in an integrated circuit and a method of manufacture therefor
US6534361B2 (en) Method of manufacturing a semiconductor device including metal contact and capacitor
US5514622A (en) Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole
JP3540302B2 (en) Semiconductor device and manufacturing method thereof
US9859818B2 (en) Micro-device with a cavity
EP0848419A1 (en) Method of making an aluminum contact
CN101582390B (en) The method of forming an integrated circuit structure
US6171951B1 (en) Dual damascene method comprising ion implanting to densify dielectric layer and forming a hard mask layer with a tapered opening
US7051934B2 (en) Methods of forming metal layers in integrated circuit devices using selective deposition on edges of recesses
US6221754B1 (en) Method of fabricating a plug
US7745282B2 (en) Interconnect structure with bi-layer metal cap
US6265313B1 (en) Method of manufacturing copper interconnect
EP1018152A1 (en) Borderless vias with cvd barrier layer
KR100366625B1 (en) Semiconductor device having dual damascen pattern structure and fabricating method thereof
JP3708732B2 (en) A method of manufacturing a semiconductor device
JP3184159B2 (en) Barrier layer and manufacturing method thereof
JP2005072384A (en) Method for manufacturing electronic device
FR2812764A1 (en) Fabrication of a Silicon-on-Insulator or Silicon-on-Nothing substrate for a semiconductor device involves forming a tunnel between a silicon layer and an initial substrate after defining and masking active zones and forming trenches
FR2734664A1 (en) Method to achieve vertical integration systems for microelectronics