FR2860920A1 - Multiple short local electrical connections for selective linkage of integrated circuit elements comprise masked selective humid attack of deposited metal - Google Patents

Abstract

An electric connection selectively linking elements (10, 12) on an integrated circuit substrate (28) comprises: (a) realizing the elements on a substrate of which a part of the surface is made of a first material, depositing, on the substrate and the elements, a second conducting material (44, 46) that is able to create a reaction with the first material to form a conducting material on the substrate surface; (b) treating the substrate to produce the reaction; and (c) realizing a selective withdrawal of the second material that has not reacted with the first material, in order to leave some of the second material according to a pattern that corresponds with at least a part of the connection. An independent claim is also included for an integrated circuit incorporating the above electrical connections.

Description

METHOD FOR MAKING CONDUCTIVE CONNECTIONS OF

  INTEGRATED CIRCUITS, AND INTEGRATED CIRCUIT USING SUCH CONNECTIONS.

  The invention relates to the production of integrated circuits, and more particularly to a technique of selective electrical connection between elements of the integrated circuit, especially when the latter are relatively close to one another. As such, the invention makes it possible to achieve so-called local interconnections over short distances on the scale of the integrated circuit.

  In the state of the art, these local connections are made by techniques called local interconnection level (known by the acronym LIL for "Local Interconnect Level"). In general, these interconnections are made with metallization levels on the silicon in a pre-metallic dielectric structure. Such interconnections are typically made by depositing tungsten directly on the silicon.

  FIG. 1 illustrates an example, seen from above, of a local level interconnection topography (hereinafter abbreviated to "local interconnection"), in which two active zones 2 and 4 are represented, each forming an island in a silicon substrate 6 of the integrated circuit 8. The insulation of the two active zones is obtained by forming a field oxide of the type said trench isolation of shallow depth 3 (known by the acronym STI, for "Shallow Trench Isolation ").

  A first active zone 2 shown comprises two MOS transistors, whose respective gates 10 and 12 are electrically connected by a first local interconnection 14.

  Moreover, the two active zones 2 and 4 are electrically connected to each other on either side of the trench 3 by a second local interconnection 16.

  Finally, the second active zone 4 comprises a third local interconnection 18, which is vertical in order to connect two superimposed conductive levels, in this case in the vicinity of the control gate 20 of a MOS transistor.

  The local interconnections are made at the silicon level for the purpose of interconnecting polycrystalline silicon lines and active zone lines.

  According to conventional manufacturing techniques, the local interconnections 14, 16, 18 are made of metal, typically tungsten (W). Local interconnections that are lateral relative to the plane of the integrated circuit, such as the first and second interconnections 14, 16, are each in trench form. The vertical interconnections, for example the third interconnection 18, are in the form of a hole filled with a conductive material forming a contact known by the English term "plug".

  More generally, local interconnections are divided into two types of trenches and holes, filled with conductive material.

  The trenches serve to connect in particular two zones of the circuit, for example two active zones, two polysilicon lines, or an active zone and a polysilicon line. The holes are used to connect just one particular point to another.

  The realization of local interconnections involves an additional level of photolithography and etching.

  For the record, Figures 2a to 2d show schematically the main steps in the formation of a pattern in relief on a silicon wafer by a photolithography and etching technique.

  At an initial stage (FIG. 2a), a mask 22 comprising, in the form of blanks 24, a pattern of material to be removed is affixed to a layer of photosensitive resin 26 uniformly deposited on the surface of the silicon wafer 28. A radiation 30 suitable for cause a reaction on the resin is applied through the mask.

  The assembly comprising the substrate 28 and the resin 26 is developed in a chemical bath so as to remove the exposed portions of the resin, made non-resistant to the bath. The pattern of the mask 22 reproduced in relief on the resin is then obtained, making it possible to expose the upper surface 28a of the substrate 28 at the places where the resin is removed (FIG. 2b).

  The aforementioned assembly is then subjected to etching, for example of the contact type, during which the exposed surface 28a of the silicon is machined chemically to form trenches 32, whose bottom surface 32a is substantially set back from the upper surface 28a. of the substrate (Figure 2c).

  Finally, the resin is completely removed from the silicon substrate 28 (Figure 2d).

  FIG. 3 illustrates, by a view along the line III-III 'of FIG. 1, the concrete embodiment of the local interconnections of FIG. 1 according to a state of the art.

  To define the trenches and holes ("plugs") to form the local interconnections of the circuit, it is expected the deposition, on the surface of the substrate 28, of two so-called pre-metallic dielectric levels (better known by the acronym PMD) , for "Pre-Metal Dielectric"), each comprising the conductive elements 14, 16 which constitute the local interconnections. (The term "pre-metal comes from the fact that these levels are located between the substrate 28 and a first level of metallization 34, called" metal 1 "of the integrated circuit.) In the figure, the first and second levels of the structure, counted from the substrate 28 are respectively designated PMD1 and PMD2.

  It is observed that the elements on which the local interconnections, ie the control grid contacts 10, 12, and the contact zones for the second and third local interconnections 16, 20 mentioned above, must be formed are covered with CoSi 2 (these parts are marked with hatching). CoSi2 also covers other elements, in particular the control grid 20.

  The vertical reliefs on the surface of the substrate 28, constituted here by the control grids 10, 12, 20, are bordered on their flanks by so-called "spacer" elements (better known by the term "spacer") 38, of which the outer faces have slopes. The spacers are here formed by an oxide-nitride bilayer etched anisotropically.

  Initially, the first level PMD1 is formed according to the following steps: A1. Prior formation of a cobalt silicide layer (CoSi2), comprising: A1.1. depositing a layer of cobalt, or other equivalent conductor, over the entire exposed portion of the semiconductor substrate 6, after cleaning thereof; A1.2. rapid annealing of this coated layer, (known by the acronym RTP, for "Rapid Thermal Processing"); A1.3. selective wet removal of part of the layer, either unreacted cobalt and TiN.

  A2. Deposition of the PMD1 layer, comprising: A2.1. the deposition of a nitride layer, of the type known by the term "borderless nitride" (literal translation: "nitride without border"); A2.2. the deposition of silicon oxide SiO 2 using, for example, a sub-atmospheric chemical vapor deposition technique (known by the acronym SACVD, for "Sub-Atmospheric Chemical Vapor Deposition"), or chemical vapor deposition plasma enhanced (known by the acronym PECVD, for "Plasma-Enhanced Chemical Vapor Deposition), or deposition in high density plasma (known by the acronym HOP, for" High density plasma), etc. Depending on the application, this deposit may be either undoped or doped. In the latter case, the doping material may be, for example, boron and phosphorus forming a deposit known by the acronym BPSG, for "Boron / Phosphorous-Doped Silicon Glass"); and A2.3. a densification step of the PMD1 layer thus formed, with conversion of CoSi material to CoSi2.

  A.2.4. polishing or mechano-chemical planarization (known by the acronym CMP, for "Chemical-Mechanical Polishing / Planarization") of the oxide. This step makes it possible to obtain a flat PMD layer.

  A3. Photolithography and etching of the pattern of local interconnections with filling of the pattern with tungsten. This phase makes it possible to define, by an appropriate mask, the "plugs" and the trenches of the local interconnection. It includes the following steps.

  A3.1. photolithography for the formation of the photoresist pattern 26 (see Figures 2a and 2b); A3.2. dry etching (by plasma) of the local interconnections (see FIGS. 2c and 2d), with critical shutdown on the CoSi2 and / or on the insulation trench STI 3 serving to isolate the active zones from each other A3.3. removal of the resin; A3.4. the production of a barrier deposit (conductive layer) on the entire wafer, made bilayer, for example with Ti / TiN, entering the contacts (sliced or "plugs"). More particularly, this very thin layer, typically 200 Angstrom in total, is deposited at the bottom of the contacts and especially on the flanks of the latter; A3.5. the deposition of tungsten forming the conductive elements 14 and 20, as well as the portion of the "plug" 18 over the extent of the vertical section of the pre-metallic dielectric PMD1; and A3.6. mechanochemical polishing / planarization using a CMP technique as for step A.2.4 above. The purpose of this step is to mechanically remove the tungsten above the oxide to leave it only in plugs and trenches.

  At the end of these steps, only tungsten remains in the trenches 14 and in the "plugs" 18 of the local interconnection. From this preparation, the second dielectric level PMD2 is formed, consisting of a set of "plugs" intended for the selective connection of the tungsten parts of the first dielectric with the first metallization 34, designated metal 1.

  To do this, is deposited again a pre-metallic layer (or dielectric) used to define the connections. This second pre-metallic layer only defines "plugs". These are intended to connect the metal 1 with either the "plugs" of the PMD1 level, or the lines made by the first deposit of tungsten.

  The second level PMD2 is achieved by the following steps, consisting of forming the "plugs": 4.1. a silicon oxide SiO2 deposit which, as for the first level PMD1, may be undoped or doped, the doping in the latter case possibly being with boron and phosphorus to form the aforementioned BPSG composition; 4.2. if the deposit is doped, a densification of this deposit, for example BPSG; 4.3. a photolithography to define the holes for the "plugs"; 4.4. an engraving of "plugs"; and 4.5. the removal of the resin used during the etching.

  As regards the whole of this conventional process of manufacturing local connections, it should be noted that the photolithography step is very critical and requires an expensive mask, being a phase-shifted mask, specially designed to define very complex patterns. purposes.

  In the etching, a very high criticality point in the example of Figure 3 is indicated by the mark A, located at the edge of the trench 3 and the substrate 28, or at the end of the etching. Indeed, this mask must simultaneously define, for the same level and with the same mask, openings both trench-shaped and hole-shaped, for "plugs".

  The photolithography step is also very critical because it requires being highly selective, both: with respect to cobalt silicide (CoSi 2), this latter being in the form of a metal layer formed selectively on the active zones and on the polysilicon lines, in order to reduce the contact line resistances, and - with respect to the oxide of the insulation trench STI 3, being a field oxide used to isolate them the active zones 2, 4 (see reference A of FIG.

  In fact, an over-etching of cobalt or oxide at the edge of the aforementioned insulation slice can cause leakage currents, by junction leakage, which are destructive for the circuit.

  In addition, it is disadvantageous to use a second deposit of pre-metallic dielectric (see phase 4 above) in order to make it possible to establish a contact between the tungsten of the interconnection with the aluminum of the metal 1.

  In view of the foregoing, the invention proposes a new approach making it possible in particular to make conductive connections with a simplification compared to the state of the art, among other things at the level of the masks.

  In the embodiment to be described, the invention makes it possible to eliminate dry critical etching at the local interconnection lines, replacing it with a selective wet etching of the deposited metal, in this case cobalt in the example described.

  More particularly, according to a first aspect, the invention provides a method for producing at least one electrically conductive connection selectively connecting elements to an integrated circuit substrate, characterized in that it comprises the steps of: elements on a substrate of which at least a portion of the surface consists of a first material, - depositing, on the substrate and said elements, at least a second material, which is conductive and capable of creating a reaction with the first material for forming a conductive material on the surface of the substrate, - treating the substrate to carry out said reaction, - selectively removing the second material unreacted with said first material, to leave the second material in a pattern which corresponds to at least part of the connection.

  Advantageously, the selective removal of the unreacted second material is carried out by at least one mask defining said pattern, for example by using a wet etching technique. In this case, the selective shrinkage can be achieved by immersing the substrate and its mask in a bath.

  In the embodiment, at least one connection connects one of said elements to an area of the substrate made conductive by said reaction between the first and second material.

  At least one area of the substrate rendered conductive by said reaction between the first and the second material can be used as a base point for a hole contact, known as plug, allowing connection to a superimposed contact point. .

  Preferably, the selective removal performs multiple connections.

  Advantageously, the connection is made as a line / connections are made only in the form of lines.

  The mask can then comprise a pattern of only line (s) to define the or each connection.

  The mask can be formed by a photolithography technique.

  Said processing step may comprise a rapid thermal treatment, known by the acronym RTP, for "Rapid Thermal Processing".

  The second deposited material, or at least one of the deposited materials, may be a metal, for example a refractory metal. In the latter case, the refractory metal may be at least one of cobalt, titanium, nickel.

  The deposition step of at least one second material may, according to an advantageous option, consist in depositing a bilayer formed of a first component which is covered, or encapsulated, by a second component, different from the first one.

  If this option is used, the first component of the bilayer may comprise, inter alia, cobalt, and the second component, which covers or encapsulates it, may comprise, inter alia, titanium (Ti), the first component being in contact with the first material.

  Said first material forming at least a portion of said exposed surface of the substrate may be silicon. In this case, the conductive material formed by said reaction may be a silicide. In the latter case, the silicide may be at least one of: cobalt silicide (CoSi), titanium silicide, nickel silicide.

  The method may furthermore comprise the production of a single pre-metallic dielectric (PMD) structure comprising at least one hole contact, known by the English term "plug", allowing a connection to a superimposed contact point for connecting points of said electrical connection with a metallization level.

  The or each electrical connection thus formed may form a local connection extending over short distances on the scale of the integrated circuit.

  According to a second aspect, the invention furthermore relates to an integrated circuit comprising at least one electrically conductive connection selectively connecting elements to its substrate, at least a portion of the surface of which consists of a first material, characterized in that the connection is made by a pattern formed by at least a second material which is conductive, this second material further forming at least one conductive region on the substrate by reaction with the first material thereof. The second material may be titanium nitride.

  The optional aspects presented in the context of the method according to the first object, may apply mutatis mutandis to this integrated circuit according to the second object, and will not be repeated here for the sake of brevity.

  The invention and the advantages resulting therefrom will emerge more clearly on reading the preferred embodiments, given purely by way of non-limiting examples, with reference to the appended drawings, in which: FIG. 1, already described, is a plan view of an example of interconnections at a local level of a zone of an integrated circuit, FIGS. 2a to 2d, already described, are simplified sectional views showing the successive steps 0 occurring during a photolithography and etching operation on a silicon substrate, used in particular when making interconnections at a local level, Figure 3, already described, is a sectional view along line III-III 'of the circuit zone of FIG. 1, for the case of a structure of interconnections at a local level made according to a conventional two-level pre-metal dielectric technique, and FIGS. 4a to 4g are sectional views of a portion of plat silicon on which are formed local interconnections according to the preferred embodiment of the invention, showing the evolution of manufacture through successive steps.

  The preferred embodiment of the invention is described in the context of local connections on a silicon substrate, using the example of the topography of FIG. 1.

  In this context, the invention makes it possible to eliminate the critical level that constitutes the use of a particular type of mask conventionally used to achieve interconnection at the local level LIL, which before this, in the state of the art, defines both holes and trenches.

  In the example, this elimination is obtained, inter alla, by a judicious use of a material, here in the form of a bilayer, to make the conductive paths of the interconnections of local level. (By contrast, in the state of the art, when a bilayer is used, it only serves to form the contact points, which are covered by tungsten trenches forming the conductive paths of the interconnection) . Thus, the conductive property of a bilayer, in this case the cobalt / TiN couple, is used to suppress the local level of LIL interconnection.

  The bilayer thus used according to the embodiment serves to reduce the resistance of the contacts and the resistance of the lines, being an equipotential layer.

  The set of steps of the present embodiment of the invention is represented by FIGS. 4a to 4g, which take as a basic element the local interconnection structure shown in FIG. 1. The structural parts of these figures already described in FIG. the frame of the previous figures will not be repeated, and have the same references as the latter. For the same reasons, any manufacturing step also used in the embodiment of the state of the art and already described (see Figures 2a-2d, 3) will not be described again.

  FIG. 4a shows the configuration described in the context of FIG. 3, with regard to the silicon substrate 28 constituting the wafer, the STI 3 insulation trench constituting the field oxide, the control gates 10, 12, MOS transistors, and nitride spacers 38.

  This initial configuration is obtained according to conventional techniques.

  From this base, an appropriate cleaning of the surface of the wafer 28 is carried out.

  Then, as shown in Figure 4b, a bilayer 42 is deposited on the entire surface of the wafer (or at least on at least one area of its surface to receive local interconnections if possible). In the example, this bilayer 42 is made by depositing a thin layer of cobalt 44 with a layer of titanium nitride (TiN) 46. The latter constitutes a coating layer, or encapsulation, of the layer of cobalt 44.

  Rapid annealing (RTP) is then performed to react cobalt with silicon in contact with wafer 28 to form cobalt silicide (CoSi).

  As shown in FIG. 4c, the CoSi is therefore formed only at the places where the cobalt 44 has been in contact with the silicon. Thus, it does not form on the surfaces comprising oxide or nitride, in particular on the portions constituted by the spacers 38 and on the field oxide 3 constituted by the isolation trench (STI). In these portions, the unreacted cobalt remains in the pure metal state.

  Thus two CoSi formation zones are obtained - a first zone 48 on the raised silicon elements, in this case the top of the control gates 10, 12, 20, and a second zone 50 at the silicon level of the substrate. .

  These zones 48, 50 leave the TiN conductive layer exposed on the surface.

  Overall, the bilayer 42, having reacted or not, remains conductive.

  In this way, it is possible to form the topography of all the local interconnection lines by using the bilayer, by selective removal of the portions thereof that are not assigned to the conductive lines.

  According to the embodiment, this selective removal is performed not in full plate, but in masked plate. Remarkably, it is then enough to hide the areas that are to be electrically connected, then plunge the wafer in the selective removal bath. Cobalt and TiN will only be removed where the resin is open (exposed).

  The cobalt / TiN 42 bilayer is thus kept in the areas protected by the resin, and then obtains a low impedance electrical interconnection which corresponds functionally to the local level of interconnection obtained according to conventional techniques.

  To do this, the embodiment implements photolithography according to the principle presented with reference to FIG. 2. In the case in point, the selective shrinkage is carried out wet.

  As shown in FIG. 4d, a layer of resist photoresist 26 is deposited on the structure of FIG. 4c, on which a photolithography mask 22 is affixed, the masked portions 22a of which are in line with the locations of the circuit of FIG. conductive lines of interconnection to achieve. Note that this photolithography step corresponds to the inverse of that conventionally used for the realization of local interconnections, in that the openings 24 define lines on the surface of the substrate (and on the elements of low relief, such as the grids, which are substantially in the same focal plane), and not trenches and holes.

  As shown in FIG. 4e, at the end of the exposure to radiation 30 through the photolithography mask 22, and the selective removal of the resin 26, the remaining resin defines an etching mask that masks the locations intended solely for interconnection lines. It is noted that this approach contrasts with the conventional method which requires the realization of trenches.

  Then, a chemical shrinkage is carried out by means of a wet bath which is selective with CoSi, making it possible to remove, at the parts exposed by the resin mask 26, unreacted TiN and cobalt during the heat treatment (ie lying, in the illustrated case, on the nitride spacers 38 and on the insulation trenches STI 2).

  As shown in FIG. 4f, this selective shrinkage thus leaves so-called "silicide" zones 48, 50 devoid of conducting TiN.

  Subsequently, the resin is removed from the mask and PMD pre-metal dielectric deposition and contact formation operations in the form of contact holes 52 (better known by the English term "plug") of the PMD structure are performed. giving the result illustrated in Figure 4g. It is noted that only one level of pre-metallic dielectric PMD is necessary.

  More particularly, these operations include II. The deposition of the single layer of pre-metallic PMD dielectric, comprising: I1.1. the realization of nitride contact pads, of the type without border (known by the term "borderless nitride"), the deposit of silicon oxide SiO 2, either without doping or with doping, in the latter case it is possible, among other things, to use boron and phosphorus doping to obtain boron / phosphorus doped silicon dioxide (known by the acronym BPSG for "Boron / Phosphorous-Doped Silicon Oxide"). obtained using a subatmospheric chemical vapor deposition technique (known by the acronym SACVD, for "Sub-Atmospheric Chemical Vapor Deposition") or by any other suitable means, such as plasma-enhanced chemical vapor deposition (known by the acronym PECVD, for "Plasma-Enhanced Chemical Vapor Deposition", or deposition in high-density plasma (known by the acronym HDP, for "High-Density Plasma"), etc. I1.3. of densification of the single layer of pre-metallic dielectric thus formed, with conversion of CoSi material to CoSi2.

  I2. Photolithography and contact etching, comprising: I2.1. contact type photolithography, I2.2. an etching of the contact type, and I2.3. the removal of the resin.

  From the foregoing, it is noted that one of the original features of the process is that selective removal of TiN and cobalt, which have not reacted during the heat treatment, is carried out using masked selective shrinkage. , in this case by a photolithography step.

  Although the mask used for this operation is specific, it is less critical than the mask conventionally used to obtain the local interconnection lines with tungsten.

  Indeed, the mask for selective removal used in accordance with the invention does not have to define both holes and trenches. This mask only defines lines. There is therefore no problem associated with a substantial depth of field which appears with the reliefs formed in particular by the holes.

  The invention can be used with any material that can form a killing agent. The metal used may be, for example, titanium, nickel, etc. any refractory metal that enters the definition of silicide.

  Furthermore, the silicide can be replaced by other compositions depending on the intended application, making the necessary adaptations to the teachings given in the context of this description given in the context of silicide.

  More generally, the technique just described can be applied to all encapsulated refractory metals (Ti, Ni, ....).

  An advantageous application of the technique according to the invention is the manufacture of electronic components of low power consumption, in particular for conveying the signal.

  The process according to the invention is remarkable in that it makes it possible: to change from a phase shift critical mask to a standard critical mask (passage of a mask where trenches and holes are defined); a mask in which only lines are defined, - to eliminate the etching of the local interconnection level, which is very critical at the level of the field oxide zone edges, - to make the pre-metallic dielectric at once, thanks to the removal of a pre-metallic dielectric level with BPSG deposition, spacer deposit, tungsten and tungsten deposition with polishing / chemical mechanical planarization.

Claims (27)

claims   A method of producing at least one electrically conductive connection selectively connecting elements (2, 4, 10, 12) to an integrated circuit substrate (28), characterized in that it comprises the steps of: - Making said elements (2, 4, 10, 12) on a substrate of which at least a portion of the surface consists of a first material, depositing, on the substrate and said elements, at least a second material, which is conductive (42, 44, 46) and capable of creating a reaction with the first material to form a conductive material on the surface of the substrate, - treating the substrate to carry out said reaction, - selectively removing the second unreacted material with said first material, to leave second material in a pattern that corresponds to at least a portion of the connection.   2. Method according to claim 1, characterized in that the selective removal of the unreacted second material is performed by at least one mask (46) defining said pattern.   3. Method according to claim 1 or 2, characterized in that the selective removal of the unreacted second material is carried out according to a wet etching technique.   4. Method according to claim 3, characterized in that the selective removal of the unreacted second material is made by immersing the substrate (28) and its mask (46) in a bath.   5. Method according to any one of claims 1 to 4, characterized in that at least one connection connects one of said elements (2, 4, 10, 12) to an area of the substrate made conductive by said reaction between the first and the second material.   6. Method according to any one of claims 1 to 5, characterized in that at least one area of the substrate made conductive by said reaction between the first and second material is used as a base point for a contact hole, known by the English word "plug", allowing a connection to a superimposed point of contact.   7. Method according to any one of claims 1 to 6, characterized in that selective removal carries out multiple connections.   8. Method according to any one of claims 1 to 7, characterized in that the connection is made in the form of line / connections are made only in the form of lines.   9. Method according to any one of claims 2 to 8, characterized in that the mask (46) comprises a pattern of only line (s) to define the or each connection.   10. Method according to any one of claims 2 to 9, characterized in that the mask (46) is formed by a photolithography technique.   11. Method according to any one of claims 1 to 10, characterized in that said processing step comprises a rapid thermal treatment, known by the acronym RTP, for "Rapid Thermal Processing".   12. Method according to any one of claims 1 to 11, characterized in that the second deposited material (42, 44, 46), or at least one of the deposited materials, is a metal.   13. Process according to any one of   Claims 1 to 12, characterized in that the   second deposited material (46) comprises a refractory metal.   14. Process according to any one of   Claims 1 to 13, characterized in that the   second deposited material (44) comprises at least one of.   - cobalt, - titanium, - nickel.   15. Method according to any one of claims 1 to 14, characterized in that the deposition step of at least a second material consists of depositing a bilayer (42) formed of a first component (44) which is covered , or encapsulated, by a second component (46), different from the first one.   16. The method of claim 15, characterized in that the first component (44) of the bilayer comprises cobalt, and in that the second component, which covers or encapsulates, comprises titanium nitride (TiN), said first component being in contact with the first material.   17. Method according to any one of claims 1 to 16, characterized in that said first material forming at least a portion of said exposed surface of the substrate (28) is silicon.   18. The method of claim 17, characterized in that the conductive material formed by said reaction is a silicide.   19. The method of claim 18, characterized in that said silicide is at least one of: - a cobalt silicide (CoSi), a titanium silicide, a nickel silicide.   20. Process according to any one of   claims 1 to 19, characterized in that   further comprises producing a single pre-metal dielectric (PMD) structure comprising at least one hole contact, known by the English term "plug", allowing a connection to a superimposed contact point (52) for connecting points of said electrical connection with a metallization level (34).   21. Method according to any one of claims 1 to 20, characterized in that the or each electrical connection thus made is a local connection extending over short distances on the scale of the integrated circuit.   An integrated circuit (8) comprising at least one electrically conductive connection selectively connecting elements (2, 4, 10, 12) to its substrate (28), at least a portion of the surface of which is made of a first material, characterized in that the connection is made by a pattern formed by at least a second material which is conductive, this second material further forming at least one conductive region on the substrate by reaction with the first material (28) thereof.   23. Integrated circuit according to claim 22, characterized in that the second material (44) comprises cobalt.   24. Integrated circuit according to any one of claims 22 or 23, characterized in that the second material (46) comprises a refractory metal.   25. Integrated circuit according to claim 24, characterized in that the second material is titanium nitride (TiN).   26. Integrated circuit according to any of   claims 22 to 25, characterized in that   further comprises a single pre-metal dielectric (PMD) structure comprising at least one hole contact, known by the English term "plug", allowing a connection to a superimposed contact point (52) and for connecting points said conductive connection with a metallization level (34).   27. Integrated circuit according to any one of claims 22 to 26, characterized in that said electrical connection is a local connection extending over short distances on the scale of the integrated circuit.