JP2001068558A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device, in which fine patterning of elements, high reliability and high speed operation up to a low voltage are realized. SOLUTION: A first gate electrode is formed between source S and drain D regions on a semiconductor substrate via a gate insulating film and a second gate electrode is formed on the first gate electrode via an insulating film to constitute an MOSFET. When the MOSFET is turned on through a control circuit, a first voltage is applied to the first gate at a first timing, and a second voltage is applied to the second gate at a second timing delayed behind the first timing. Consequently, the voltage of the first gate has a level equal to the sum of the first and second voltages through capacitive coupling of the first and second gate electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a digital circuit technology using a MOSFET (insulated gate type field effect transistor). .

[0002]

2. Description of the Related Art To improve the driving force of an output circuit composed of MOSFETs or a driver for driving a heavy load, there are methods such as increasing the gate width W, reducing the gate length L, or decreasing the threshold voltage Vth. is there.

[0003]

The voltage of semiconductor integrated circuit devices such as memories and logic circuits composed of MOSFETs has been reduced. In a memory or a logic circuit operating at such a low voltage, reducing the threshold voltage Vth of the MOSFET is effective in increasing the driving capability and operating at high speed. However, the lowering of the threshold voltage of the MOSFET as described above, on the other hand, causes a problem that the leak current flowing in the source-drain path of the MOSFET in the off state increases or the breakdown voltage of the gate insulating film decreases. . The reduction in the gate insulating film leads to a reduction in the reliability of the element due to gate insulation breakdown particularly in an input circuit or an output circuit.

An object of the present invention is to provide a semiconductor integrated circuit device capable of miniaturization of elements, high reliability, and high-speed operation up to low voltage. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a first gate electrode is formed on a semiconductor substrate sandwiched between source and drain regions via a gate insulating film, and a second gate electrode is formed on the first gate electrode via an insulating film to form a MOSFET. When the MOSFET is turned on by the control circuit,
A first voltage is applied to the first gate at a first timing, and a second voltage is applied to the second gate at a second timing later than the first timing. The voltage of the first gate electrode is set to a voltage obtained by adding the first and second voltages due to the capacitive coupling between the first gate electrode and the second gate electrode.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing one embodiment of a MOSFET provided in a semiconductor integrated circuit device according to the present invention. FIG. 1A shows an element layout, FIG. 1B shows an AA ′ cross section thereof,
(C) shows the BB 'cross section, and (D) shows
The equivalent circuit is shown.

The MOSFET of this embodiment has a double structure in which a second-layer polysilicon SG is stacked on a first-layer polysilicon FG constituting a gate electrode with an insulating film interposed therebetween. Then, these two gate electrodes SG / F
G has input terminals INSG and INFG to which voltages can be independently applied as shown in the equivalent circuit of (D). In the operation of the MOSFET, the first-layer polysilicon FG functions as a gate electrode. However, when viewed from input signals supplied from the input terminals INSG and INFG, the second-layer polysilicon SG also functions as a control terminal. Performs the action of Therefore, the second-layer polysilicon SG can be regarded as a kind of the gate electrode.

In the above (A) to (C), the first gate electrode FG is formed between the source S and the drain D via a thin gate insulating film formed on the semiconductor substrate. On this gate electrode FG, an interlayer insulating film is provided, and a second gate electrode SG is formed. Although not particularly limited, the second gate electrode SG is connected to the first metal wiring layer M1 guided to the input terminal INSG at a position near the source S and the drain D by a contact CONT.

The first gate electrode FG is a second-layer polysilicon S formed simultaneously with the second gate electrode SG.
G and the source S and the drain D via the second-layer polysilicon SG.
The metal wiring layer M1 and the contact CONT which are guided to the input terminal INFG at a position relatively far from
Connected by Thereby, as shown in (D),
The MOSFET according to the present invention has a source S and a drain D
, A gate connected to the first input terminal INFG, and a capacitor C provided between the first input terminal INFG and the second input terminal INSG.

One electrode of the capacitor C is connected to the first electrode.
The gate electrode FG is the same as the gate electrode of the MOSFET. The other electrode of the capacitor C is the second gate electrode SG, and the dielectric of the capacitor C is formed of an interphase insulating film between the first gate electrode FG and the second gate electrode.

FIG. 2 is a circuit diagram showing an embodiment of an output circuit constituted by using MOSFETs according to the present invention. The output MOSFET is an N-channel type MOSF
It is composed of a series circuit of an ETQ1 and a P-channel MOSFET Q3. The ground potential VSS of the circuit is applied to the source of the N-channel MOSFET Q1, and the power supply voltage VCC is applied to the source of the P-channel MOSFET Q3. Then, the drains of the MOSFETs Q1 and Q3 are commonly connected to the output terminal OUT.

The source-drain path of the N-channel MOSFET Q2 is connected between the first gate (INFGN) of the N-channel MOSFET Q1 and the input terminal INFGN0. Power supply voltage VCC is constantly applied to the gate of MOSFET Q2. And
The second gate of the MOSFET Q1 is connected to the input terminal INSGN.
Connected to. As described above, when viewed as a circuit, the capacitor C1 including the first gate electrode and the second gate electrode is provided.

The source-drain path of the P-channel MOSFET Q4 is connected between the first gate (INFGP) of the P-channel MOSFET Q3 and the input terminal INFGP0. The ground potential VSS of the circuit is constantly applied to the gate of the MOSFET Q4. The second gate of the MOSFET Q3 is connected to the input terminal IN.
Connected to SGP. When viewed as a circuit in the same manner as described above, a capacitor C2 including the first gate electrode and the second gate electrode is provided.

FIG. 3 is a timing chart for explaining an example of the operation of the output circuit shown in FIG. Each of the input signals INFGP0, INSGP, INF
When GN0 and INSGN are low level (VSS),
The P-channel MOSFET Q4 is on, the low level of the input signal INFGP0 turns on the P-channel output MOSFET Q3, the N-channel MOSFET Q2 is on, and the input signal INFG.
N-channel output MOSF by low level of N0
Since the ETQ1 is turned off, the output terminal OUT is at a high level like the power supply voltage VCC. However, at this time, it is assumed that the potential at both ends of the capacitor C2 is VSS as an initial state.

The input signals INFGP0, INSGP, IN
FGN0 changes from low level (VSS) to high level (VC
C), the P-channel MOSFET Q
3 is turned off in response to the high level of the input signal INFGP0. Then, since the high level of the input signal INFGN0 is transmitted to the gate of the MOSFET Q1 through the MOSFET Q2, the MOSFET Q1 is turned on. At this time, the voltage supplied to the gate of MOSFET Q1 is limited to VCC-Vthn by threshold voltage Vthn of MOSFET Q2. Therefore,
Since the voltage between the gate and the source of the MOSFET Q1 is limited as described above, the output terminal OUT is pulled down to a low level by a current corresponding to the voltage.

Such an operation of the output MOSFET Q1 is useful for reducing noise due to a parasitic inductance component due to a bonding wire or the like at the output terminal. That is, when the MOSFET Q1 is turned on, a large change in the current means that a large noise is generated in the ground line VSS of the circuit due to the parasitic inductance component.
The gate of Q1 is supplied with a limited voltage obtained by subtracting the threshold voltage Vthn of the MOSFET Q2 from the high level of the input signal INFGN0, so that the change in the current is limited and the generation of noise is suppressed. it can.

In a semiconductor integrated circuit device constituting a semiconductor memory or a logic circuit, data is input / output in units of a plurality of bits, and a plurality of output circuits similar to the above are provided. It works all at once. Therefore, when the output signals of the plurality of output circuits change as described above, in the worst case, all the output circuits simultaneously change from the high level to the low level, which is superimposed and generates noise on the ground line. Therefore, it is extremely useful that the noise in the output circuit can be reduced as described above. Since the input signal INSGN is still at the low level together with the output operation as described above, the voltage VCC-Vthn is charged in the capacitor C1.

The input signals INFGP0, IN as described above
The input signal INSG is delayed with respect to SGP and INFGN0.
When N changes to a high level (VCC), the capacitor C
1, the MOSFET Q
One first gate voltage is a boosted voltage such as 2VV-Vthn. In response to the step-up of the first gate voltage, MOSFET Q2 is turned off. That is, the boosted voltage 2VCC-Vthn as described above
In contrast, the gate of the MOSFET Q2 and the input terminal INFG
Since both N0 are set to a low voltage such as the power supply voltage VCC, the node connected to the input terminal INFGN0 acts as a source, and the MOSFET Q2 is turned off.
Thereby, the boosted voltage 2VCC-Vthn as described above is obtained.
To the input terminal INFGN0.

Since the boosted voltage 2VCC-Vthn is supplied to the gate electrode of the output MOSFET Q1 as described above, a large current flows in the drain-source path of the MOSFET Q1, and the output signal OUT is rapidly pulled to the low level VSS. Can be. As a result, as a result, an input signal having a larger voltage width than the conventional one is supplied to the gate and switching is performed, so that the driving force of the MOSFET Q1 can be increased.

Next, the input signals INFGP0, INFGN
0 and INSGN are changed from the high level to the low level, the MOS signal is changed by the low level of the input signal INFGN0.
The FET Q2 is turned on, and the gate electrode of the N-channel type output MOSFET Q1 is set to a low level while the capacitor C1 is discharged, so that the FET C2 is turned off. And
When the low level of the input signal INFGP0 is the MOSFET Q4
To the gate of the P-channel type output MOSFET Q3, so that the MOSFET Q3 is turned on.

At this time, the voltage supplied to the gate of MOSFET Q3 is limited to VSS + Vthp by threshold voltage Vthp of MOSFET Q4. Therefore, since the voltage between the gate and the source of the MOSFET Q3 is limited as described above, the output terminal OUT is raised to a high level by the limited current corresponding to the voltage, and the case of the low-level output operation is different from that in the case of the low-level output operation. Similarly, noise generated in the power supply voltage VCC is reduced.

The input signals INFGP0, IN as described above
The input signal INSG is delayed with respect to FGN0 and INSGN.
When P changes to low level (VSS), the capacitor C
2, the MOSFET Q
The first gate voltage of No. 3 is a negative voltage such as -VV + Vthp (Vthp is a negative voltage). As described above, in response to the first gate voltage being increased in the negative direction,
Increase the driving force of MOSFET Q3 and
4, the negative voltage −VCC + V as described above.
thp is prevented from falling into the input terminal INFGP0.

Including the MOSFETs Q2 and Q4,
The input signals INFGP0, INFGN0,
A circuit forming INSGN and INSGP is an output MOSF
It constitutes a control circuit for ETQ1 and ETQ2. Of the above input signals, the input signal INSGN or I
NSGP can be formed by a combination of a delay circuit such as an inverter circuit and a logic gate circuit. For example, when delaying the rise of a signal that changes to a high level (logic 0 to logic 1) like the input signal INSGN, the input signal INFGN0 and its delay signal are supplied to the AND gate circuit, and the output signal You can use.
When delaying the fall of a signal that changes to low level (from logic 1 to logic 0) like the input signal INSGP, the input signal INFGP0 is supplied to the OR gate circuit.
And its delay signal, and use the output signal. The gate circuit can be replaced with a NAND or NOR gate circuit.

When applied to the above-described CMOS output circuit, even when the power supply voltage VCC is lowered to 3.3 V, 2.5 V, or lower, the output MOSFET Q1
And the voltage applied between the gate and the source of Q3 can be higher than the voltage between the power supply voltage VCC and the ground potential VSS of the circuit. Therefore, it is not necessary to increase the channel width of the MOSFET in order to obtain a large drive current. As a result, the element can be miniaturized, and high integration can be realized.

For example, in a normal output circuit, the signal amplitude between the gate and the source is VCC / VSS. Power supply voltage VC
When C = 1.8 V and the threshold voltage Vthn = 0.4 V, the signal amplitude between the gate and the source is 1.8 V in the conventional CMOS circuit and up to 3.2 V in the output circuit according to the present invention. It can be seen that the driving force can be increased and the driving force can be improved.

In the output circuit of this embodiment, it is not necessary to reduce the threshold voltage of the MOSFET in order to obtain a large drive current. As a result, a leakage current flowing when the MOSFET is turned off can be reduced.
The current consumption of the CMOS circuit can be reduced. Since it is not necessary to reduce the thickness of the gate insulating film in order to reduce the threshold voltage, it is possible to increase the gate withstand voltage. In particular, in a circuit having a node connected to an output terminal, such as an output circuit, a margin against breakdown of the element due to static electricity generated in an external terminal during transportation or handling of the semiconductor integrated circuit device can be increased, and reliability can be improved. Can be.

FIG. 4 is a circuit diagram showing another embodiment of the output circuit constituted by using the MOSFET according to the present invention. The output MOSFET is composed of a series circuit of two N-channel MOSFETs Q1 and Q3.
That is, the P-channel MOSFE of the embodiment of FIG.
TQ3 is replaced with an N-channel MOSFET. Accordingly, MOSFET Q4 is also replaced with an N-channel type, and the voltage applied to the gate is also set to VCC.
It is said. The rest is the same as the above-described embodiment circuit.

FIG. 5 is a timing chart for explaining an example of the operation of the output circuit shown in FIG. When the output MOSFETs Q1 and Q3 are N-channel MOSFETs as described above,
Unlike the S configuration, the output MOSFE on the power supply voltage VCC side
Input signals INFGH0 and INSGH for TQ3;
The input signals INFGL0 and INSGL to the output MOSFET Q1 on the ground potential VSS side of the circuit are basically signals having a complementary relationship in order to switch-control the MOSFETs Q3 and Q1 in a complementary manner. Then, the input terminal INFGH0 (INFGL0) corresponding to the first gate electrode is first set to the high level, and the capacitor C1 (C2) is connected to VCC.
After the precharge of −Vthn, the input terminal INSGH (INSGL) corresponding to the second gate electrode is set to a high level.

In the output circuit as in this embodiment,
Capacitors C1 and C2 composed of first and second gate electrodes of the gates of output MOSFETs Q1 and Q3
When turning it on, an effective gate voltage is driven at a first stage level such as VCC-Vthn and a boosted second stage level such as 2VCC-Vthn. As a result, even when the power supply voltage VCC is reduced to 3.3 V or 2.5 V or lower, the driving capability of the output MOSFETs Q1 and Q3 can be increased.

The output MOSFET on the power supply voltage VCC side is set to N
Even as a channel type MOSFET, its effective gate has a voltage of 2 VCC-
Vthn can be supplied to the output terminal OUT
High level of the output signal output from the power supply voltage VCC
A signal having a full amplitude as shown in FIG. As described above, when the output circuit connected to the output terminal OUT is configured by an N-channel MOSFET, it is necessary to electrically separate the two output MOSFETs as compared with the case where the CMOS circuit as described above is used. N-channel MOS to get the same current
The fact that the size of the FET can be made smaller and the like work synergistically, and high integration can be realized. Therefore, the present invention is suitable for a word driver as described below, in addition to the output circuit of the semiconductor integrated circuit device.

From the standpoint of reliability, CMOS output circuits require special care to prevent latch-up due to parasitic thyristor elements. Therefore, the output composed of N-channel MOSFETs as described above is required. Circuits are more advantageous. Of course, in the circuit of this embodiment, as in the case of the CMOS circuit,
The advantages of miniaturizing the element and increasing the gate insulation margin are directly retained.

As described above, the MOS according to the present invention
In the FET, the gate of the MOS driver can be boosted (increased) by capacitive coupling, and the driving force can be improved without significantly increasing the gate area (particularly, the gate width). In particular, a low power consumption system can be realized by high speed operation at a low voltage.

FIG. 6 is a block diagram showing one embodiment of the semiconductor memory device according to the present invention. In the memory array, the memory cells are arranged in a matrix at intersections of word lines and data lines or bit lines. The X decoder is for forming a word line selection signal of the memory array, and is composed of a decoder for decoding an address signal to form a word line selection signal and a word driver for driving the word line by the selection signal. You. The Y decoder is
A signal for selecting a data line or a bit line of the memory array is formed, and a Y selection driver is provided as needed.

Although the memory cell is not particularly limited,
The first formed by the same manufacturing process as the above MOSFET
The semiconductor device includes a gate electrode and a second gate electrode, and stores information charges using the first gate electrode as a floating gate. The second gate electrode is connected to the word line as a control gate. The accumulation and release of the electric charge to and from the floating hang gate correspond to writing and erasing, for example, using a tunnel current, or generating hot electrons near the drain, and causing the generated hot electrons to charge the floating gate. It is a non-volatile memory that is stored and released by a tunnel current.

In such a nonvolatile memory, the memory cell has a two-layer gate structure as described above, and the manufacturing process is diverted as it is to form the element shown in FIG. By using a circuit or the above-described word driver for a peripheral circuit or the like, the operation can be speeded up.

The input buffer is a circuit for inputting an address signal, a control signal, and a data signal for writing, and the output buffer performs an operation of outputting a read signal. In the above memory circuit, a large number of word lines are formed at a high density in order to increase the storage capacity of the word lines. Therefore, the word drivers also need to be formed at a high density in accordance with the pitch of the word lines. Therefore, as shown in the embodiment of FIG.
A circuit (driver) including an OSFET is suitable for the word driver as described above because it can obtain a large driving capability and can be mounted at a high density.

In this embodiment, the output buffer shown in FIG.
Alternatively, in addition to using the circuit of FIG. 3, a low VCC detection circuit is mounted. From this low VCC detection circuit, when the power supply voltage VCC is other than a preset low voltage, the control circuit switches the input signal to operate as a normal output buffer or input buffer that does not boost the gate. That is, in the present embodiment, when VCC is high, a normal output buffer operates, and the operation of the present invention as described above is performed only when the low VCC detection circuit detects low VCC. .

According to this configuration, the gate is boosted only at the low VCC where the driving power has been reduced in the past, and a high-speed operation with little dependence on VCC can be realized. In addition, when VCC is high, it is possible to avoid element degradation due to unnecessary gate boosting. The operation when the VCC is high is, for example, the first operation.
The INFG corresponding to the gate electrode and the INSG corresponding to the second gate electrode may always be changed at the same potential.

FIG. 7 is a block diagram showing another embodiment of the semiconductor memory device according to the present invention. In this embodiment, the low VCC operation is controlled by a command formed by the control chip. That is, it is composed of two chips, a memory chip and a controller chip, and has a low VCC.
The switching of the / high VCC operation is performed by switching a command from the controller chip.

The control chip has a low VCC detection circuit. When a system on which the control chip is mounted is operated at a low VCC, a microcomputer CPU is used.
, A command for low VCC is issued, and the operation mode is set through the input buffer of the memory chip. Also in this embodiment, high-speed operation with little dependence on VCC can be realized, and element degradation due to unnecessary gate boosting when VCC is high can be avoided. Further, by using commands as needed, even when VCC is high, a further high-speed operation can be realized by performing the gate boosting operation of the present invention.

FIG. 8 is a block diagram showing another embodiment of the MOSFET used in the semiconductor integrated circuit device according to the present invention. In the semiconductor integrated circuit device according to the present invention, when the MOSFET as shown in FIG. 1 is formed, a plurality of polysilicon gate forming processes are used similarly to a flash memory using a nonvolatile memory cell having a stacked gate structure. It is necessary to form an element. However, not all circuits mounted on the semiconductor integrated circuit device need to operate at high speed. That is, in a circuit portion which does not affect the operation speed, it is not necessary to supply an input signal with a time difference as a double gate structure as described above.

In such a low-speed circuit, it is conceivable to use a MOSFET having only the first gate electrode. However, this configuration requires that two types of MOSFETs be manufactured. MOSFET of this embodiment
As described above, the gate structure of the MOSFET is the same as the gate structure of FIG. 1, and a short circuit is provided by providing a contact portion between the first gate electrode FG and the second gate electrode SG. Thereby, the second gate electrode SG is connected to the input terminal IN.
Can be regarded as a part of a simple wiring path from the first gate electrode FG to the first gate electrode FG. As a result, both the high-speed circuit and the low-speed circuit can be formed by using the above-described two-layer polysilicon gate formation process for all the elements, and the manufacturing is simplified.

The operation and effect obtained from the above embodiment are as follows. (1) A first gate electrode is formed on a semiconductor substrate sandwiched between source and drain regions via a gate insulating film, and a second gate electrode is formed on the first gate electrode via an insulating film. And the above-mentioned MO is controlled by the control circuit.
When the SFET is turned on, a first voltage is applied to the first gate at a first timing, and a second voltage is applied to the second gate at a second timing that is later than the first timing. And applying a voltage between the gate and the source by changing the voltage of the first gate electrode to a voltage obtained by adding the first and second voltages by capacitive coupling between the first and second gate electrodes. A high voltage equal to or higher than the voltage can be supplied, and the effect is obtained that the drive capability can be increased and the speed can be increased while miniaturization and high reliability of the element are achieved.

(2) The first gate electrode is formed of a first polysilicon layer, and the second gate electrode is formed of at least the first gate electrode on the channel region of the MOSFET.
The second polysilicon layer is formed so as to overlap with the second polysilicon layer with the insulating film interposed therebetween, so that it can be easily manufactured by a double gate manufacturing process established in a nonvolatile memory or the like. The effect is obtained.

(3) As the control circuit, a control MO in which an active level voltage is constantly applied to the gate is used.
A first input signal which is set to an active level at the first timing through the control MOSFET to a first gate of the MOSFET, and a first input signal to the second gate electrode; By supplying the second input signal which is set to the active level at the second timing delayed by the input signal, the effect that the drive capability can be increased and the speed can be increased can be obtained.

(4) A CMOS circuit composed of an N-channel MOSFET and a P-channel MOSFET is constructed as the MOSFET, and the N-channel MO is used.
By providing the control circuit for each of the SFET and the P-channel MOSFET, it is possible to obtain an effect that the drive capability can be increased and the speed can be increased while achieving miniaturization and high reliability of the device.

(5) By forming an output buffer for transmitting an output signal to an external terminal, the CMOS circuit can perform an output operation that operates at a high speed up to a low voltage.

(6) The MOSFET is a pair of N-channel MOSFETs connected in series between the power supply voltage and the ground potential of the circuit and operated in a complementary manner. By providing the control circuit, it is possible to obtain an effect that high integration and an output operation that operates at high speed up to low voltage can be performed.

(7) A memory array in which memory cells are provided at intersections of a plurality of word lines and a plurality of bit lines, wherein the pair of N-channel MOSFETs is used for a word line selection circuit of the memory array. By doing
An effect is obtained that high-speed operation can be performed up to a low voltage while achieving high integration of the memory circuit.

(8) As the memory cell, the MO
A first gate electrode and a second gate electrode formed by the same manufacturing process as the SFET; and the first gate electrode is used as a floating gate to store information charges. The second gate electrode is used as a control gate. By connecting to the word line, an effect is obtained that a non-volatile memory circuit that operates at high speed to a low voltage without increasing the number of processes can be realized.

(9) A first gate electrode and a second gate electrode formed by the same manufacturing process as the MOSFET are provided, and the first gate electrode and the second gate electrode are electrically connected to each other. MOS used as two gate electrodes
A circuit that performs high-speed operation by further providing an FET;
An effect is obtained in which circuits that do not require high-speed operation can be mixed and MOSFETs corresponding to each operation speed can be formed in the same process.

(10) An operation mode for preventing deterioration of elements in the same circuit by further providing a circuit for supplying the same input signal to the first gate and the second gate according to a predetermined control signal; An effect is obtained that a mode for performing a high-speed operation can be selected.

(11) By forming the predetermined control signal when the power supply voltage is equal to or higher than a predetermined voltage, deterioration of the element is prevented at a high power supply voltage, and high-speed operation is performed at a low power supply voltage. The effect that it can be realized is obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the two MOSFETs of the output buffer both have an element structure as shown in FIG. 1 according to the present invention.
Only one output MOSFET may be applied. For example,
In the circuit of FIG. 3, the output MOSF on the power supply voltage VCC side
The ETQ3 may use an element having a structure as shown in FIG. 1, and the output MOSFET Q1 on the ground potential VSS side may use an element having a structure as shown in FIG. In this case,
An output circuit or driver capable of receiving a high-level output signal corresponding to the power supply voltage VCC with a simple configuration can be obtained. INDUSTRIAL APPLICABILITY The present invention can be widely used for various semiconductor integrated circuit devices configured using MOSFETs.

[0055]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a first gate electrode is formed on a semiconductor substrate sandwiched between source and drain regions via a gate insulating film, and a second gate electrode is formed on the first gate electrode via an insulating film to form a MOSFET. When the MOSFET is turned on by the control circuit,
A first voltage is applied to the first gate at a first timing, and a second voltage is applied to the second gate at a second timing that is later than the first timing.
A large voltage equal to or higher than the power supply voltage is supplied between the gate and the source by setting the voltage of the first gate electrode to a voltage obtained by adding the first and second voltages by capacitive coupling between the gate and the second gate electrode. It is possible to increase the drive capability and increase the speed while miniaturizing the element and achieving high reliability.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a MOSFET provided in a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a circuit diagram showing one embodiment of an output circuit configured using a MOSFET according to the present invention.

FIG. 3 is a waveform chart for explaining an example of the operation of the output circuit of FIG. 2;

FIG. 4 is a circuit diagram showing another embodiment of an output circuit configured using the MOSFET according to the present invention.

FIG. 5 is a waveform chart for explaining an example of the operation of the output circuit of FIG. 3;

FIG. 6 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 7 is a block diagram showing another embodiment of the semiconductor memory device according to the present invention.

FIG. 8 is a configuration diagram showing another embodiment of the MOSFET used in the semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

Q1 to Q4: MOSFET, S: source, D: drain, FG: first layer polysilicon, SG: second layer polysilicon.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 27/10 481 H01L 27/08 321K 491 27/10 434 29/78 29/78 301G 21/8247 371 29/788 H03K 19/094 A 29/792 H03K 19/0944 (72) Inventor Masato Takahashi 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in the Semiconductor Group, Hitachi, Ltd. 5F001 AA02 AB08 AD12 AG40 5F040 DB03 EA08 EC00 EC07 EC19 EC26 5F048 AA01 AA03 AA08 AB01 AB03 AB04 AB07 AC03 BB01 BB05 5F083 EP02 EP23 GA12 GA23 KA01 LA07 LA10 PR43 PR44 PR53 PR54 5J056 AA03 BB02 BB46 DD13 DD28 DD51 EE03 EK06 FF07 KK

Claims (11)

[Claims] A first gate electrode formed on a semiconductor substrate sandwiched between a pair of source and drain regions via a gate insulating film; and a first gate electrode formed on the first gate electrode via an insulating film. A MOSFET having two gate electrodes; and when the MOSFET is turned on, applying a first voltage to the first gate at a first timing, and applying a first voltage to the first gate at a second timing later than the first timing. Second
A second voltage is applied to the gate of the first gate electrode, and the voltage of the first gate electrode is set to a voltage obtained by adding the first and second voltages by capacitive coupling between the first and second gate electrodes. A semiconductor integrated circuit device comprising a circuit. 2. The first gate electrode according to claim 1, wherein the first gate electrode is formed of a first polysilicon layer, and the second gate electrode is at least a first polysilicon layer on a channel region of the MOSFET. A second layer formed so as to overlap the layer with the insulating film interposed therebetween.
A semiconductor integrated circuit device comprising a polysilicon layer. 3. The control circuit according to claim 1, wherein the control circuit includes a control MOSFET having a gate to which an active-level voltage is constantly applied.
A first input signal that is set to an active level at the first timing is supplied via ET, and the second gate electrode is set to an active level at a second timing that is delayed by the first input signal. A second input signal supplied thereto. 4. The device according to claim 1, wherein the MOSFET is an N-channel MOSFET and a P-channel MOSFET.
The N-channel MOSFET and the P-channel MOSFET constitute a CMOS circuit composed of a channel MOSFET.
A semiconductor integrated circuit device, wherein each of the SFETs is provided with the control circuit. 5. The semiconductor integrated circuit device according to claim 4, wherein said CMOS circuit forms an output buffer for transmitting an output signal to an external terminal. 6. The MOSFET according to claim 1, wherein the MOSFET comprises a pair of N-channel MOSFETs connected in series between a power supply voltage and a ground potential of the circuit and operated complementarily. A semiconductor integrated circuit device, wherein the control circuit is provided for each of a pair of N-channel MOSFETs. 7. The memory array according to claim 6, further comprising a memory array provided with a memory cell at an intersection of a plurality of word lines and a plurality of bit lines, wherein the pair of N-channel MOSFETs is connected to a word line of the memory array. A semiconductor integrated circuit device comprising a selection circuit. 8. The memory cell according to claim 7, wherein the memory cell includes a first gate electrode and a second gate electrode formed by the same manufacturing process as the MOSFET, and stores the information charge using the first gate electrode as a floating gate. A semiconductor integrated circuit device for accumulating data, wherein the second gate electrode is connected to the word line as a control gate. 9. The method according to claim 1, wherein the first MOSFET is formed by the same manufacturing process as the MOSFET.
A gate electrode and a second gate electrode;
A semiconductor integrated circuit device, further comprising a MOSFET electrically connected to a gate electrode and a second gate electrode and used as one gate electrode. 10. The semiconductor integrated circuit device according to claim 1, further comprising a circuit for supplying the same input signal to the first gate and the second gate according to a predetermined control signal. 11. The semiconductor integrated circuit device according to claim 10, wherein the predetermined control signal is formed when a power supply voltage is equal to or higher than a predetermined voltage.