JP2007013060A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007013060A
JP2007013060A JP2005195264A JP2005195264A JP2007013060A JP 2007013060 A JP2007013060 A JP 2007013060A JP 2005195264 A JP2005195264 A JP 2005195264A JP 2005195264 A JP2005195264 A JP 2005195264A JP 2007013060 A JP2007013060 A JP 2007013060A
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cell
grid
wiring
macrocell
chip
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Atsuhiro Morita
Yasuyuki Okada
康幸 岡田
篤弘 森田
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Matsushita Electric Ind Co Ltd
松下電器産業株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing wiring resistance caused by wasteful wiring and via-hole while avoiding tangled wiring, without enlarging the macro cell size, more than necessary.
SOLUTION: A semiconductor device comprises macro cells 1, each having a plurality of input/output parts (t) disposed on a cell grid (g) in a cell boundary CB; and a semiconductor chip 2, on which the macro cells 1 are mounted in the state of making the cell grid (g) parallel with a chip grid G in a cell arrangement wiring area, and wiring R formed along with the chip grid G is connected to the input/output parts (t) of the macro cells 1. Each of the input/output parts (t) in the macro cells 1 is elongated vertically in the lengthwise direction of the cell grid (g) in an attitude, along with the cell boundary CB of the macro cells 1. Thus, tangled wiring is avoided and wiring resistance caused by wasteful wirings are avoided, and via-hole is reduced.
COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、複数の入出力部がセルバウンダリにおいて配置されたマクロセル(SRAM等メモリセル、IOセルなど)と、前記マクロセルを搭載し、チップグリッドに沿って形成した配線がマクロセルの入出力部に接続された半導体チップとからなる半導体装置に関する。 The present invention includes a plurality of input and output portions arranged macrocells (SRAM such as a memory cell, IO cell, etc.) in the cell boundary and, mounting the macrocell, wiring formed along the chip grid to the input and output of the macrocell a semiconductor device comprising a connected semiconductor chip.

図3は従来のマクロセルの概略構成を示す平面図である。 Figure 3 is a plan view showing a schematic configuration of a conventional macrocell. 図3において、1aはSRAM(StaticRandom Access Memory)、IOセルなどのマクロセル、CBはマクロセル1aにおけるセルバウンダリ、g1〜g11はマクロセル1aにおいて互いに平行に形成された複数のセルグリッド、t11,t12,t13はマクロセル1aのセルバウンダリCBの下辺部に配置された入出力部である。 In FIG. 3, 1a are SRAM (StaticRandom Access Memory), a macro cell, such as IO cells, CB cell boundary in the macro cell 1a, g1~g11 the plurality of cells grids which are parallel to each other in the macro cell 1a, t11, t12, t13 are output portion disposed in the lower side of the cell boundary CB macrocell 1a. セルグリッドg1〜g11は、レイアウト設計ツールを用いてマクロセル1aに形成される配線経路の基準ラインである。 Cell grid g1~g11 is a reference line of the wiring path formed macrocell 1a by using the layout design tool.

マクロセル設計時にレイアウト設計ツールを用いて最小線幅で配線を行う。 Performing wiring minimum line width by using a layout design tool during macrocell design. このとき、配線の中心線がセルグリッドg1〜g11に沿うようにする。 At this time, the center line of the wiring is set along the cell grid G1~g11. このように配線を行うことにより、デザインエラーを発生させることなく、配線を効率的に行うことができる。 By performing such wiring, without generating design error, it is possible to perform wiring efficiently.

レイアウト設計ツールによるセルグリッドg1〜g11の生成は、通常、次のように行われる。 Generating a grid of cells g1~g11 by the layout design tool is usually performed as follows. まず、マクロセル1aの中央に最初のセルグリッドg6が形成される。 First, the first cell grid g6 in the center of the macrocell 1a is formed. 次いで、中央のセルグリッドg6から両端に向かってセルグリッドg5〜g1,g7〜g11が生成される。 Then, the cell grid g5~g1 toward the center of the cell grid g6 across, G7~g11 is generated. 両端のセルグリッドg1,g11は必ずしもセルバウンダリCBの縦辺部に一致しない。 Cell grid g1 ends, g11 does not necessarily coincide with the vertical side portion of the cell boundary CB. 半導体チップ2のレイアウト設計でも同様である。 The same applies to the layout design of the semiconductor chip 2. 入出力部t11,t12,t13は、セルバウンダリCBの下辺部において、セルグリッドg2,g5,g9上(一例)に配置されている。 Output unit t11, t12, t13, at the lower side of the cell boundary CB, is located in the cell grid g2, g5, g9 upper (one example).

図4はマクロセル1aを半導体チップ2上で配置配線したときのレイアウトを示す。 Figure 4 shows the layout when the placement and routing of the macro cell 1a on the semiconductor chip 2. G1〜G11は半導体チップ2のセル配置配線領域において形成された互いに平行な複数のチップグリッドである。 G1~G11 are a plurality of chips grid parallel to each other are formed in the cell placement and routing area of ​​the semiconductor chip 2. 半導体チップ2のレイアウト設計時には、マクロセル1aはそのセルバウンダリCBを基準にして配置される。 When layout design of the semiconductor chip 2, the macro cell 1a are arranged with respect the cell boundary CB. セルバウンダリCBがセルグリッドgに対して位置ずれを生じていることから、セルグリッドgはチップグリッドGに対して位置ずれを生じる。 Since the cell boundary CB is misaligned with respect to the cell grid g, the cell grid g produces a positional deviation with respect to the chip grid G. したがって、セルグリッドg上の入出力部t11,t12,t13もチップグリッドGに対して位置ずれを生じる。 Therefore, input and output portion t11 on cell grid g, t12, t13 also cause positional deviation relative to the tip grid G. 半導体チップ2上での配線R11,R12,R13は、マクロセル1aの入出力部t11,t12,t13に至る途中まではチップグリッドGを通って配線されるが、マクロセル1aの近傍では、チップグリッドGを外れ、折れ曲がった状態でマクロセル1aの入出力部t11,t12,t13へ接続される(JOG配線)。 Wiring R11, R12 of on the semiconductor chip 2, R13 is halfway to reach the output section t11, t12, t13 macrocell 1a are wired through the chip grid G, in the vicinity of the macro cell 1a, the chip grid G the off, is connected to the input-output section t11, t12, t13 of the macro cell 1a in a bent state (JOG wiring).
なお、特許文献1のような先行技術もある。 Incidentally, there is also a prior art as disclosed in Patent Document 1.
特開平6−188314号公報(第1頁、第1図) JP-6-188314 discloses (page 1, FIG. 1)

上記の従来の技術においては、マクロセル1aの近傍で折れ曲がった状態で配線を行うため、配線リソースを効率良く使用できず、配線混雑を起こし、無駄な配線とヴィアに起因して不必要な配線抵抗増大を招くことになる。 In the conventional techniques described above, for performing the wiring in a state which is bent in the vicinity of the macro cell 1a, it can not efficiently use the routing resources, cause routing congestion, unnecessary due to the wasteful wiring and the via wiring resistance It leads to an increase.

これの対策として、半導体チップ2上のレイアウト設計に合わせてマクロセル設計を行い、マクロセル1aの半導体チップ2への位置合わせにおいて両端のセルグリッドgをセルバウンダリCBの縦辺部に一致させるということが考えられる。 As this countermeasure, performs macrocell designed according to the layout design of the semiconductor chip 2, is that the match cell grid g across the vertical side portions of the cell boundary CB in alignment to the semiconductor chip 2 of the macro cell 1a Conceivable. しかし、この場合、マクロセル1aのサイズが不必要に大きくなってしまう。 However, in this case, the size of the macro cell 1a is increased unnecessarily. 一般に、SRAM設計等においては、メモリアレイを基準にレイアウト設計を行い、セルサイズが設計目標を満たすようにする。 Generally, in the SRAM design, etc., it performs a layout design based on the memory array, cell size to satisfy the design goals.

本発明は、このような事情に鑑みて創作したものであり、マクロセルサイズを不必要に大きくすることなく、配線混雑を回避し、無駄な配線とヴィアに起因する配線抵抗を低減できる半導体装置を提供することを目的としている。 The present invention has been made in view of such circumstances, without increasing the macro cell size unnecessarily, to avoid routing congestion, the semiconductor device capable of reducing the wiring resistance due to wasteful wiring and via It is an object of the present invention to provide.

本発明による半導体装置は、 The semiconductor device according to the invention,
複数の入出力部がセルバウンダリにおいてセルグリッド上に配置されたマクロセルと、 And the macrocell arranged on the cell grid in a plurality of input-output unit cell boundary,
前記セルグリッドをセル配置配線領域のチップグリッドに平行とする状態で前記マクロセルを搭載し、前記チップグリッドに沿って形成した配線が前記マクロセルの前記入出力部に接続された半導体チップとからなり、 Wherein the macro cell mounted in a state of parallel cell grid chip grid cell placement and routing area, wiring formed along the chip grid consists of a connected semiconductor chip to the output unit of the macro cell,
前記マクロセルにおける前記入出力部が、当該マクロセルのセルバウンダリに沿う姿勢で、かつ、前記セルグリッドの長さ方向に対する垂直方向に長い形状に構成されていることを特徴するものである。 The input-output unit in the macrocell, a posture along the cell boundary of the macrocell, and is intended to, characterized in that it is configured in a long shape in the direction perpendicular to the length direction of the cell grid.

上記構成において、前記入出力部の長さについては、隣接する少なくとも2つの前記セルグリッドにまたがる長さを有していることが好ましい。 In the above configuration, the length of the input portion, preferably has a length spanning at least two adjacent of said cell grid.

上記の構成によれば、セルバウンダリがセルグリッドと一致していないマクロセルを用いて、セルバウンダリを基準にチップグリッドに位置合わせしてマクロセルを半導体チップに搭載しても、マクロセルの入出力部に対して、半導体チップの少なくとも1本のチップグリッドが交差する。 According to the above configuration, by using the macro cell cell boundary does not match the cell grid, also equipped with a macrocell on a semiconductor chip are aligned to the chip grid cell boundary as a reference, the output of the macrocell in contrast, at least one chip grid of semiconductor chips intersect. すなわち、チップグリッドに沿って行われるマクロセルへの接続配線を入出力部に至るまで直線的なものにすることが可能となる。 That is, it is possible to make them a straight up a connection wiring to the macrocell is performed along the chip grid output unit.

本発明によれば、半導体チップのレイアウト設計において、チップグリッドに沿って行われるマクロセルへの接続配線を入出力部に至るまで直線的なものにすることが可能となる(JOG配線の回避)。 According to the present invention, in the layout design of the semiconductor chip, it is possible to make them linear manner until a connection wiring to the macrocell is performed along the chip grid output unit (avoidance of JOG wiring). その結果、マクロセルサイズを不必要に大きくすることなく、配線混雑を解消し、無駄な配線とヴィアに起因する配線抵抗を低減することができる。 As a result, without increasing the macro cell size unnecessarily, to eliminate wiring congestion, it is possible to reduce the wiring resistance due to wasteful wiring and the via.

以下、本発明にかかわる半導体装置の実施の形態を図面に基づいて詳細に説明する。 It will be described in detail with reference to embodiments of a semiconductor device according to the present invention with reference to the drawings.

図1は、本発明の実施の形態におけるマクロセルの概略を示す平面図である。 Figure 1 is a plan view schematically showing a macro cell in the embodiment of the present invention. 図1において、1はSRAM、IOセルなどのマクロセル、CBはマクロセル1におけるセルバウンダリ、g1〜g11はマクロセル1において互いに平行に形成された複数のセルグリッド、t1,t2,t3はマクロセル1のセルバウンダリCBの下辺部に配置された入出力部である。 In Figure 1, 1 is SRAM, macro cell, such as IO cells, CB cell boundary in the macro cell 1, G1~g11 the plurality of cells grids which are parallel to each other in the macro cell 1, t1, t2, t3 cell of the macro cell 1 an input-output portion disposed in the lower side of the boundary CB.

レイアウト設計時に、マクロセル1に互いに平行で等間隔隔てた複数のセルグリッドg1〜g11が生成される。 During the layout design, a plurality of cells grids g1~g11 of spaced parallel equally spaced from each other to the macrocell 1 is generated. マクロセル1の中央のセルグリッドg6から両側に向けて順次に形成される。 They are sequentially formed toward the opposite sides from the cell grid g6 central macrocell 1. 両端のセルグリッドg1,g11は、セルバウンダリCBの縦辺部に一致していない。 Cell grid g1, g11 at both ends, does not coincide with the vertical side portion of the cell boundary CB. マクロセル1の内部の配線および入出力部t1,t2,t3の中心は、すべてセルグリッドに乗るように設計される。 Internal wiring and the center of the input and output section t1, t2, t3 of the macro cell 1 is designed all to ride in the cell grid.

入出力部t1,t2,t3は、セルグリッドg1〜g11のうちの隣接する少なくとも2つのセルグリッド間にまたがる長さを有し、セルグリッド長さ方向に対する垂直方向に長い形状となっている。 Output unit t1, t2, t3 has a length spanning between at least two adjacent cells grid of a grid of cells G1~g11, it has a long shape in the direction perpendicular to the cell grid length direction.

図2は、半導体チップ2上での配線レイアウト状態を示す。 Figure 2 shows a wiring layout state of on the semiconductor chip 2. 図2に示す半導体チップ2のセル配置配線領域において、図1のマクロセル1の入出力部t1,t2,t3への配線接続がなされている。 In the cell placement and routing area of ​​the semiconductor chip 2 shown in FIG. 2, the wiring connection to the output section t1, t2, t3 of the macrocell 1 Figure 1 it has been made.

マクロセル1を半導体チップ2に搭載する際に、マクロセル1のセルバウンダリCBの縦辺部が半導体チップ2のチップグリッドGに一致するように位置合わせする。 When mounting the macrocell 1 to the semiconductor chip 2, the vertical side portion of the cell boundary CB macrocell 1 is aligned so as to match the chip grid G ​​of the semiconductor chip 2. その結果、チップグリッドG1〜G11に対して、マクロセル1のセルグリッドg1〜g11がずれている。 As a result, the chip grid G1~G11, cell grid g1~g11 macrocell 1 is shifted. マクロセル1の入出力部t1,t2,t3は、マクロセル1のセルグリッドg1〜g11の2つのセルグリッド間にわたって延在した横長となっている。 Output unit t1, t2, t3 of the macro cell 1, has a horizontally long extending across between the two grid of cells of the cell grid g1~g11 macrocell 1. したがって、セルグリッドg1〜g11とチップグリッドG1〜G11の位置ずれを補う状態で、横長の入出力部t1,t2,t3はチップグリッドG1〜G11に対して交差する状態となる。 Accordingly, in a state to compensate for the positional deviation of the cell grid g1~g11 chip grid G1~G11, input-output unit t1, t2, t3 of the horizontal is in a state of crossing the chip grid G1~G11.

半導体チップ2における配線R1,R2,R3は、チップグリッドG1〜G11に沿って直線状に配置されている。 Wires R1, R2, R3 in the semiconductor chip 2 is arranged linearly along the chip grid G1~G11. 配線R1,R2,R3の中心線はチップグリッドG1〜G11とほぼ一致している。 Center line of the wiring R1, R2, R3 are substantially matches the chip grid G1~G11. したがって、配線R1,R2,R3をチップグリッドG1〜G11上に直線的に沿わせても、入出力部t1,t2,t3に到達するように配線することが可能となる。 Therefore, the wiring R1, R2, even the R3 thereby linearly along on the chip grid G1~G11, it is possible to wire so as to reach the output section t1, t2, t3. 以上の結果として、セルグリッドを効率良く使用して、マクロセルサイズを不必要に大きくすることなく、マクロセル1の周りの配線混雑を緩和し、無駄な配線とヴィアに起因する配線抵抗を低減することができる。 As a result of the above, it uses the cell grid efficiently, without increasing the macro cell size unnecessarily, relieve routing congestion around the macro cell 1, to reduce the wiring resistance due to wasteful wiring and via can.

本発明の半導体装置の技術は、半導体開発のセル設計の対象となる任意のマクロセルについて有用である。 Technology of a semiconductor device of the present invention is useful for any macrocell to be cell design of semiconductor development.

本発明の実施の形態におけるマクロセルの概略を示す平面図 Plan view showing the outline of a macro cell in the embodiment of the present invention 本発明の実施の形態におけるマクロセルの半導体チップ上での配線レイアウト図 Wiring layout on the macrocell of the semiconductor chip in the embodiment of the present invention 従来の技術におけるマクロセルの概略を示す平面図 Plan view showing the outline of a macro cell in the prior art 従来の技術におけるマクロセルの半導体チップ上での配線レイアウト図 Wiring layout on the macrocell of the semiconductor chip in the prior art

符号の説明 DESCRIPTION OF SYMBOLS

1 マクロセル 2 半導体チップ g1〜g11 セルグリッド G1〜G11 チップグリッド R1,R2,R3 配線 CB セルバウンダリ t1,t2,t3 入出力部 1 macrocell 2 semiconductor chip g1~g11 cell grid G1~G11 chip grid R1, R2, R3 wiring CB cell boundary t1, t2, t3 input unit

Claims (2)

  1. 複数の入出力部がセルバウンダリにおいてセルグリッド上に配置されたマクロセルと、 And the macrocell arranged on the cell grid in a plurality of input-output unit cell boundary,
    前記セルグリッドをセル配置配線領域のチップグリッドに平行とする状態で前記マクロセルを搭載し、前記チップグリッドに沿って形成した配線が前記マクロセルの前記入出力部に接続された半導体チップとからなる半導体装置であって、 Mounting the macrocell in a state of parallel said cell grid chip grid cell placement and routing area, semiconductor wiring formed along the chip grid consisting of connected semiconductor chip to the output unit of the macrocell an apparatus,
    前記マクロセルにおける前記入出力部が、当該マクロセルのセルバウンダリに沿う姿勢で、かつ、前記セルグリッドの長さ方向に対する垂直方向に長い形状に構成されている半導体装置。 The input-output unit in the macrocell, a posture along the cell boundary of the macrocell, and a semiconductor device configured in a long shape in the direction perpendicular to the length direction of the cell grid.
  2. 前記入出力部は、隣接する少なくとも2つの前記セルグリッドにまたがる長さを有している請求項1に記載の半導体装置。 The output unit includes a semiconductor device according to claim 1 which has a length that span adjacent at least two of said cell grid.
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