JP5827166B2 - 配線基板及び配線基板の製造方法 - Google Patents

配線基板及び配線基板の製造方法 Download PDF

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Publication number
JP5827166B2
JP5827166B2 JP2012088642A JP2012088642A JP5827166B2 JP 5827166 B2 JP5827166 B2 JP 5827166B2 JP 2012088642 A JP2012088642 A JP 2012088642A JP 2012088642 A JP2012088642 A JP 2012088642A JP 5827166 B2 JP5827166 B2 JP 5827166B2
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JP
Japan
Prior art keywords
core substrate
substrate
electrode
core
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012088642A
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English (en)
Japanese (ja)
Other versions
JP2013219191A (ja
JP2013219191A5 (OSRAM
Inventor
潤 古市
古市　　潤
立岩　昭彦
昭彦 立岩
小泉　直幸
直幸 小泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012088642A priority Critical patent/JP5827166B2/ja
Priority to US13/855,762 priority patent/US9386695B2/en
Publication of JP2013219191A publication Critical patent/JP2013219191A/ja
Publication of JP2013219191A5 publication Critical patent/JP2013219191A5/ja
Application granted granted Critical
Publication of JP5827166B2 publication Critical patent/JP5827166B2/ja
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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2012088642A 2012-04-09 2012-04-09 配線基板及び配線基板の製造方法 Active JP5827166B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012088642A JP5827166B2 (ja) 2012-04-09 2012-04-09 配線基板及び配線基板の製造方法
US13/855,762 US9386695B2 (en) 2012-04-09 2013-04-03 Wiring substrate having multiple core substrates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012088642A JP5827166B2 (ja) 2012-04-09 2012-04-09 配線基板及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2013219191A JP2013219191A (ja) 2013-10-24
JP2013219191A5 JP2013219191A5 (OSRAM) 2015-02-19
JP5827166B2 true JP5827166B2 (ja) 2015-12-02

Family

ID=49291408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012088642A Active JP5827166B2 (ja) 2012-04-09 2012-04-09 配線基板及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US9386695B2 (OSRAM)
JP (1) JP5827166B2 (OSRAM)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101548816B1 (ko) * 2013-11-11 2015-08-31 삼성전기주식회사 인쇄회로기판 및 그 제조방법
CN105746004B (zh) * 2013-11-22 2019-06-07 三井金属矿业株式会社 带有电路形成层的支持基板、两面带有电路形成层的支持基板、多层层压板、多层印刷线路板的制造方法及多层印刷线路板
JP2015146401A (ja) * 2014-02-04 2015-08-13 大日本印刷株式会社 ガラスインターポーザー
JP6361179B2 (ja) * 2014-03-10 2018-07-25 大日本印刷株式会社 配線板、配線板の製造方法
KR101580287B1 (ko) * 2014-05-02 2015-12-24 삼성전기주식회사 인쇄회로기판, 인쇄회로기판 스트립 및 그 제조방법
JP6600573B2 (ja) * 2015-03-31 2019-10-30 新光電気工業株式会社 配線基板及び半導体パッケージ
US9960120B2 (en) * 2015-03-31 2018-05-01 Shinko Electric Industries Co., Ltd. Wiring substrate with buried substrate having linear conductors
KR101795480B1 (ko) * 2015-04-06 2017-11-10 코닝정밀소재 주식회사 집적회로 패키지용 기판
JP6661232B2 (ja) * 2016-03-01 2020-03-11 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法及び半導体装置の製造方法
TWI705536B (zh) * 2018-11-16 2020-09-21 欣興電子股份有限公司 載板結構及其製作方法
WO2020129553A1 (ja) * 2018-12-19 2020-06-25 日本板硝子株式会社 微細構造付ガラス基板及び微細構造付ガラス基板の製造方法
JP7184679B2 (ja) * 2019-03-13 2022-12-06 イビデン株式会社 プリント配線板およびその製造方法
CN113013125B (zh) * 2019-12-20 2024-07-09 奥特斯奥地利科技与系统技术有限公司 嵌入有在侧向上位于堆叠体的导电结构之间的内插件的部件承载件
JP2021108317A (ja) * 2019-12-27 2021-07-29 イビデン株式会社 プリント配線板およびその製造方法
KR20230018242A (ko) * 2021-07-29 2023-02-07 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3761862B2 (ja) 1999-05-27 2006-03-29 Ｈｏｙａ株式会社 両面配線板の製造方法
WO2011004706A1 (ja) * 2009-07-10 2011-01-13 東レ株式会社 接着組成物、接着シート、それらを用いた回路基板および半導体装置ならびにそれらの製造方法
US8584354B2 (en) * 2010-08-26 2013-11-19 Corning Incorporated Method for making glass interposer panels

Also Published As

Publication number Publication date
JP2013219191A (ja) 2013-10-24
US9386695B2 (en) 2016-07-05
US20130264101A1 (en) 2013-10-10

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