JP5689470B2 - 埋め込みストレッサを有する高性能ｆｅｔを形成するための方法および構造 - Google Patents

埋め込みストレッサを有する高性能ｆｅｔを形成するための方法および構造 Download PDF

Info

Publication number
JP5689470B2
JP5689470B2 JP2012530914A JP2012530914A JP5689470B2 JP 5689470 B2 JP5689470 B2 JP 5689470B2 JP 2012530914 A JP2012530914 A JP 2012530914A JP 2012530914 A JP2012530914 A JP 2012530914A JP 5689470 B2 JP5689470 B2 JP 5689470B2
Authority
JP
Japan
Prior art keywords
semiconductor material
semiconductor
epitaxy
region
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012530914A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013506291A5 (https=
JP2013506291A (ja
Inventor
チェン・カングォ
カキフィルズ・アリ
ドリス・ブルース・ビー
シャヒディ・ガヴァム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2013506291A publication Critical patent/JP2013506291A/ja
Publication of JP2013506291A5 publication Critical patent/JP2013506291A5/ja
Application granted granted Critical
Publication of JP5689470B2 publication Critical patent/JP5689470B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
JP2012530914A 2009-09-24 2010-09-08 埋め込みストレッサを有する高性能ｆｅｔを形成するための方法および構造 Expired - Fee Related JP5689470B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/566,004 2009-09-24
US12/566,004 US8022488B2 (en) 2009-09-24 2009-09-24 High-performance FETs with embedded stressors
PCT/US2010/048039 WO2011037743A2 (en) 2009-09-24 2010-09-08 Method and structure for forming high-performance fets with embedded stressors

Publications (3)

Publication Number Publication Date
JP2013506291A JP2013506291A (ja) 2013-02-21
JP2013506291A5 JP2013506291A5 (https=) 2014-08-14
JP5689470B2 true JP5689470B2 (ja) 2015-03-25

Family

ID=43755874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012530914A Expired - Fee Related JP5689470B2 (ja) 2009-09-24 2010-09-08 埋め込みストレッサを有する高性能ｆｅｔを形成するための方法および構造

Country Status (7)

Country Link
US (1) US8022488B2 (https=)
JP (1) JP5689470B2 (https=)
CN (1) CN102511081B (https=)
DE (1) DE112010002895B4 (https=)
GB (1) GB2486839B (https=)
TW (1) TW201125124A (https=)
WO (1) WO2011037743A2 (https=)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011086728A (ja) * 2009-10-14 2011-04-28 Renesas Electronics Corp 半導体装置およびその製造方法
US8236660B2 (en) 2010-04-21 2012-08-07 International Business Machines Corporation Monolayer dopant embedded stressor for advanced CMOS
US8299535B2 (en) * 2010-06-25 2012-10-30 International Business Machines Corporation Delta monolayer dopants epitaxy for embedded source/drain silicide
KR101721036B1 (ko) 2010-09-02 2017-03-29 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9698054B2 (en) * 2010-10-19 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of a p-type field effect transistor
US8946064B2 (en) * 2011-06-16 2015-02-03 International Business Machines Corporation Transistor with buried silicon germanium for improved proximity control and optimized recess shape
DE102011080438B3 (de) * 2011-08-04 2013-01-31 Globalfoundries Inc. Herstellverfahren für einen N-Kanaltransistor mit einer Metallgateelektrodenstruktur mit großem ε und einem reduzierten Reihenwiderstand durch epitaktisch hergestelltes Halbleitermaterial in den Drain- und Sourcebereichen und N-Kanaltransistor
US9064892B2 (en) * 2011-08-30 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices utilizing partially doped stressor film portions and methods for forming the same
CN102280379B (zh) * 2011-09-05 2016-06-01 上海集成电路研发中心有限公司 一种应变硅nmos器件的制造方法
CN103137480B (zh) * 2011-11-25 2015-07-08 中芯国际集成电路制造(上海)有限公司 Mos器件的形成方法及其形成的mos器件
US8658505B2 (en) * 2011-12-14 2014-02-25 International Business Machines Corporation Embedded stressors for multigate transistor devices
CN107068753B (zh) 2011-12-19 2020-09-04 英特尔公司 通过部分熔化升高的源极-漏极的晶体管的脉冲激光退火工艺
CN103187299B (zh) * 2011-12-31 2015-08-05 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
US9012277B2 (en) * 2012-01-09 2015-04-21 Globalfoundries Inc. In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices
US8828831B2 (en) 2012-01-23 2014-09-09 International Business Machines Corporation Epitaxial replacement of a raised source/drain
US9142642B2 (en) * 2012-02-10 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for doped SiGe source/drain stressor deposition
US8592916B2 (en) 2012-03-20 2013-11-26 International Business Machines Corporation Selectively raised source/drain transistor
CN103325684B (zh) * 2012-03-23 2016-03-02 中国科学院微电子研究所 一种半导体结构及其制造方法
US8674447B2 (en) * 2012-04-27 2014-03-18 International Business Machines Corporation Transistor with improved sigma-shaped embedded stressor and method of formation
US8853750B2 (en) 2012-04-27 2014-10-07 International Business Machines Corporation FinFET with enhanced embedded stressor
US8936977B2 (en) * 2012-05-29 2015-01-20 Globalfoundries Singapore Pte. Ltd. Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
US20130328135A1 (en) * 2012-06-12 2013-12-12 International Business Machines Corporation Preventing fully silicided formation in high-k metal gate processing
KR101909204B1 (ko) * 2012-06-25 2018-10-17 삼성전자 주식회사 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법
US9029208B2 (en) * 2012-11-30 2015-05-12 International Business Machines Corporation Semiconductor device with replacement metal gate and method for selective deposition of material for replacement metal gate
US9356136B2 (en) * 2013-03-07 2016-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Engineered source/drain region for n-Type MOSFET
DE102013105705B4 (de) * 2013-03-13 2020-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung und dessen Herstellung
US9691882B2 (en) * 2013-03-14 2017-06-27 International Business Machines Corporation Carbon-doped cap for a raised active semiconductor region
JP2014187238A (ja) * 2013-03-25 2014-10-02 Toyoda Gosei Co Ltd Ｍｉｓ型半導体装置の製造方法
US9059217B2 (en) 2013-03-28 2015-06-16 International Business Machines Corporation FET semiconductor device with low resistance and enhanced metal fill
US9252014B2 (en) 2013-09-04 2016-02-02 Globalfoundries Inc. Trench sidewall protection for selective epitaxial semiconductor material formation
CN104465383B (zh) * 2013-09-23 2018-03-06 中芯国际集成电路制造(上海)有限公司 降低mos晶体管短沟道效应的方法
US10090392B2 (en) * 2014-01-17 2018-10-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9324830B2 (en) * 2014-03-27 2016-04-26 International Business Machines Corporation Self-aligned contact process enabled by low temperature
JP6194516B2 (ja) * 2014-08-29 2017-09-13 豊田合成株式会社 Ｍｉｓ型半導体装置
US9543438B2 (en) 2014-10-15 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique
KR102152285B1 (ko) * 2014-12-08 2020-09-04 삼성전자주식회사 스트레서를 갖는 반도체 소자 및 그 형성 방법
US9991343B2 (en) * 2015-02-26 2018-06-05 Taiwan Semiconductor Manufacturing Company Ltd. LDD-free semiconductor structure and manufacturing method of the same
KR102326112B1 (ko) 2015-03-30 2021-11-15 삼성전자주식회사 반도체 소자
US9947755B2 (en) * 2015-09-30 2018-04-17 International Business Machines Corporation III-V MOSFET with self-aligned diffusion barrier
CN106960838B (zh) * 2016-01-11 2019-07-02 中芯国际集成电路制造(上海)有限公司 静电保护器件及其形成方法
US9997631B2 (en) * 2016-06-03 2018-06-12 Taiwan Semiconductor Manufacturing Company Methods for reducing contact resistance in semiconductors manufacturing process
JP6685870B2 (ja) 2016-09-15 2020-04-22 株式会社東芝 半導体装置
CN107958935B (zh) * 2016-10-18 2020-11-27 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
US10879354B2 (en) * 2016-11-28 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and forming method thereof
CN109300788A (zh) * 2017-07-25 2019-02-01 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
US10468530B2 (en) 2017-11-15 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with source/drain multi-layer structure and method for forming the same
US10510889B2 (en) 2017-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. P-type strained channel in a fin field effect transistor (FinFET) device
CN110838521B (zh) * 2019-11-19 2023-04-07 上海华力集成电路制造有限公司 P型半导体器件及其制造方法
CN117476646A (zh) * 2022-07-20 2024-01-30 上海华力集成电路制造有限公司 Fdsoi工艺中pmos的抬升式源漏结构的制造方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2839018B2 (ja) * 1996-07-31 1998-12-16 日本電気株式会社 半導体装置の製造方法
JP2001127291A (ja) * 1999-11-01 2001-05-11 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
KR100406537B1 (ko) * 2001-12-03 2003-11-20 주식회사 하이닉스반도체 반도체장치의 제조 방법
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US7166528B2 (en) * 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7023055B2 (en) * 2003-10-29 2006-04-04 International Business Machines Corporation CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
US20050116290A1 (en) * 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US6946350B2 (en) * 2003-12-31 2005-09-20 Intel Corporation Controlled faceting of source/drain regions
US7226842B2 (en) * 2004-02-17 2007-06-05 Intel Corporation Fabricating strained channel epitaxial source/drain transistors
KR100642747B1 (ko) * 2004-06-22 2006-11-10 삼성전자주식회사 Ｃｍｏｓ 트랜지스터의 제조방법 및 그에 의해 제조된ｃｍｏｓ 트랜지스터
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7438760B2 (en) * 2005-02-04 2008-10-21 Asm America, Inc. Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition
US7202513B1 (en) * 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
DE102006009226B9 (de) * 2006-02-28 2011-03-10 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Transistors mit einer erhöhten Schwellwertstabilität ohne Durchlass-Strombeeinträchtigung und Transistor
US7618866B2 (en) * 2006-06-09 2009-11-17 International Business Machines Corporation Structure and method to form multilayer embedded stressors
JP2008235568A (ja) * 2007-03-20 2008-10-02 Toshiba Corp 半導体装置およびその製造方法
US7745847B2 (en) * 2007-08-09 2010-06-29 United Microelectronics Corp. Metal oxide semiconductor transistor
US7759199B2 (en) * 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
US20090140351A1 (en) * 2007-11-30 2009-06-04 Hong-Nien Lin MOS Devices Having Elevated Source/Drain Regions

Also Published As

Publication number Publication date
CN102511081A (zh) 2012-06-20
US8022488B2 (en) 2011-09-20
DE112010002895T5 (de) 2012-06-21
US20110068396A1 (en) 2011-03-24
WO2011037743A2 (en) 2011-03-31
CN102511081B (zh) 2015-10-14
GB2486839B (en) 2013-09-04
GB2486839A (en) 2012-06-27
TW201125124A (en) 2011-07-16
JP2013506291A (ja) 2013-02-21
DE112010002895B4 (de) 2012-11-08
GB201204634D0 (en) 2012-05-02
WO2011037743A3 (en) 2011-07-07

Similar Documents

Publication Publication Date Title
JP5689470B2 (ja) 埋め込みストレッサを有する高性能ｆｅｔを形成するための方法および構造
CN102906880B (zh) 半导体结构及其制造方法
US8035141B2 (en) Bi-layer nFET embedded stressor element and integration to enhance drive current
US7176522B2 (en) Semiconductor device having high drive current and method of manufacturing thereof
JP5669954B2 (ja) 高Ｋ／金属ゲートＭＯＳＦＥＴを有するＶｔ調整及び短チャネル制御のための構造体及び方法。
US7358551B2 (en) Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions
US7545001B2 (en) Semiconductor device having high drive current and method of manufacture therefor
US7704844B2 (en) High performance MOSFET
CN103155123B (zh) 具有SiGe沟道的pFET结分布的结构和方法
US8421191B2 (en) Monolayer dopant embedded stressor for advanced CMOS
CN101743621B (zh) 具有不同掺杂的有应变的电流电极区域的晶体管
JP2010505267A (ja) 応力印加電界効果トランジスタおよびその製造方法
US8759168B2 (en) MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation and method of fabrication

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130604

RD12 Notification of acceptance of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7432

Effective date: 20140616

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140624

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20140624

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20140616

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140725

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20140725

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140805

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140929

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20141118

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141121

TRDD Decision of grant or rejection written
RD14 Notification of resignation of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7434

Effective date: 20150106

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150106

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150128

R150 Certificate of patent or registration of utility model

Ref document number: 5689470

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees