JP5612830B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5612830B2
JP5612830B2 JP2009119641A JP2009119641A JP5612830B2 JP 5612830 B2 JP5612830 B2 JP 5612830B2 JP 2009119641 A JP2009119641 A JP 2009119641A JP 2009119641 A JP2009119641 A JP 2009119641A JP 5612830 B2 JP5612830 B2 JP 5612830B2
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film
wafer
manufacturing
semiconductor device
barrier metal
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JP2009119641A
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Japanese (ja)
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JP2010267899A5 (enExample
JP2010267899A (ja
Inventor
辰彦 三浦
辰彦 三浦
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2009119641A priority Critical patent/JP5612830B2/ja
Priority to US12/727,337 priority patent/US9177813B2/en
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Publication of JP2010267899A5 publication Critical patent/JP2010267899A5/ja
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Publication of JP5612830B2 publication Critical patent/JP5612830B2/ja
Priority to US14/867,400 priority patent/US20160020107A1/en
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
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    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Electrodes Of Semiconductors (AREA)
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  • Composite Materials (AREA)
JP2009119641A 2009-05-18 2009-05-18 半導体装置の製造方法 Expired - Fee Related JP5612830B2 (ja)

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Application Number Priority Date Filing Date Title
JP2009119641A JP5612830B2 (ja) 2009-05-18 2009-05-18 半導体装置の製造方法
US12/727,337 US9177813B2 (en) 2009-05-18 2010-03-19 Manufacturing method of semiconductor device
US14/867,400 US20160020107A1 (en) 2009-05-18 2015-09-28 Manufacturing method of semiconductor device

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JP2009119641A JP5612830B2 (ja) 2009-05-18 2009-05-18 半導体装置の製造方法

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JP2010267899A JP2010267899A (ja) 2010-11-25
JP2010267899A5 JP2010267899A5 (enExample) 2012-04-19
JP5612830B2 true JP5612830B2 (ja) 2014-10-22

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JP5612830B2 (ja) * 2009-05-18 2014-10-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TWI469221B (zh) 2009-06-26 2015-01-11 Pfc Device Co 溝渠式蕭基二極體及其製作方法
KR101299255B1 (ko) * 2009-11-06 2013-08-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2012064849A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 半導体装置
JP6082577B2 (ja) * 2012-11-29 2017-02-15 株式会社アルバック タングステン配線層の形成方法
FR3000840A1 (fr) * 2013-01-04 2014-07-11 St Microelectronics Rousset Procede de realisation de contacts metalliques au sein d'un circuit integre, et circuit integre correspondant
CN103928513B (zh) * 2013-01-15 2017-03-29 无锡华润上华半导体有限公司 一种沟槽dmos器件及其制作方法
US8980713B2 (en) * 2013-05-31 2015-03-17 Sony Corporation Method for fabricating a metal high-k gate stack for a buried recessed access device
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