JP2010267899A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2010267899A JP2010267899A JP2009119641A JP2009119641A JP2010267899A JP 2010267899 A JP2010267899 A JP 2010267899A JP 2009119641 A JP2009119641 A JP 2009119641A JP 2009119641 A JP2009119641 A JP 2009119641A JP 2010267899 A JP2010267899 A JP 2010267899A
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- semiconductor device
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- tungsten
- barrier metal
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Abstract
【解決手段】本願発明は、アルミニウム系メタル層と下層のシリコン系半導体層の間のバリア・メタル層として、タングステン系バリア・メタル膜をスパッタリング成膜によって形成する際、その下層をウエハ側にバイアスを印加したイオン化スパッタにより成膜し、上層をウエハ側にバイアスを印加しないスパッタにより成膜するものである。
【選択図】図12
Description
先ず、本願において開示される発明の代表的な実施の形態について概要を説明する。
(a)半導体ウエハの第1の主面上の第1の絶縁膜の上面から下方に向けて、凹部を形成する工程;
(b)前記凹部の内面及び前記第1の絶縁膜の前記上面に、タングステン系バリア・メタル膜を形成する工程;
(c)前記工程(b)の後、前記凹部の内面および前記第1の絶縁膜の前記上面の前記タングステン系バリア・メタル膜を覆うように、アルミニウム系メタル層を形成する工程、
ここで、前記工程(b)は、以下の下位工程を含む:
(b1)前記半導体ウエハにバイアス電圧を印加しながらイオン化スパッタ成膜により、前記凹部の内面及び前記第1の絶縁膜の前記上面に、前記タングステン系バリア・メタル膜の内の第1層膜を形成する工程;
(b2)前記半導体ウエハにバイアス電圧を実質的に印加しないスパッタ成膜により、前記第1層膜上に、前記タングステン系バリア・メタル膜の内の第2層膜を形成する工程。
(a)半導体ウエハの第1の主面上の第1の絶縁膜の上面から下方に向けて、凹部を形成する工程;
(b)前記凹部の内面及び前記第1の絶縁膜の前記上面に、前記半導体ウエハにバイアス電圧を印加しながらイオン化スパッタ成膜により、前記凹部の内面及び前記第1の絶縁膜の前記上面に、タングステン系バリア・メタル膜を形成する工程;
(c)前記工程(b)の後、前記凹部の内面および前記第1の絶縁膜の前記上面の前記タングステン系バリア・メタル膜を覆うように、アルミニウム系メタル層を形成する工程。
1.本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクションに分けて記載する場合もあるが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しを省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
実施の形態について更に詳述する。各図中において、同一または同様の部分は同一または類似の記号または参照番号で示し、説明は原則として繰り返さない。
まず、本願の一実施の形態の半導体装置の製造方法に使用するメタル成膜装置等について、簡単に説明する。図1は、本願の一実施の形態の半導体装置の製造方法に使用するマルチ・チャンバ型(クラスタ型)のウエハ処理装置の平面構成図である。
図3は、本願の一実施の形態の半導体装置の製造方法により製造されたパワーMOSFETの一例を示すデバイス上面図である。図3に示すように、正方形又は長方形の板状のシリコン系半導体基板(個々のチップに分割する前はウエハである)上に素子を形成したパワーMOSFET素子チップ8(トレンチ・ゲート・パワーMOS型半導体装置)は中央部にあるソースパッド領域11(アルミニウム系パッド)が主要な面積を占めている。その下には、帯状SBD領域10を挟んで、帯状ゲート電極と帯状ソース・コンタクト領域が交互に多数形成された帯状繰り返しデバイス・パターン領域R(リニア・セル領域)がある。より正確には、リニア・セル領域Rは、ソースパッド領域11の下方のほぼ全体に広がっており、破線で囲った部分はその一部である。このリニア・セル領域Rの周辺には、ゲート電極を周辺から外部に引き出すゲートパッド領域13がある。更にその周りには、アルミニウム・ガードリング19が設けられている。そして、チップ8の最外周部はウエハをダイシング等により分割する際の領域、すなわち、スクライブ領域14である。
このセクションでは、0.15マイクロ・メートル・プロセスのリニア・トレンチ・ゲート型パワーMOSFETの例について、図4から図11に基づいて、セクション2における図3の帯状繰り返しデバイス・パターン領域切り出し部分Rのトレンチ・ゲート・セル部12に対応するデバイス断面等について、プロセス・フローを説明する。
なお、ソース電極材料としては、ここで説明するシリコン添加アルミニウム系メタル(AlSi)のほか、AlCu,純Al、銅系メタル部材等が使用可能である。
ここに説明する構造は、図12および図13に説明した2段バリア・メタル成膜プロセスに対する変形例によるデバイス構造である。
図18は図13に対応するSEM(Scanning Electron Microscope)写真である。すなわち、セクション3に説明した2段バリア・メタル成膜プロセスによるパワーMOSFETのセル領域(トレンチ・ゲート・セル部)12の断面形状を示す。溝底部分Bは、2段構造を呈する凹部(ソース・コンタクト溝)22の底部であり、ほぼ完全に埋め込まれていることがわかる。また、層間絶縁膜21(図13)上の上層バリア・メタル膜23bと下層バリア・メタル膜23aを比較すると、上層バリア・メタル膜23bの粒塊が柱状を呈していることがわかる。
以上本発明者によってなされた発明を実施形態に基づいて具体的に説明したが、本願の発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。
1a ウエハのデバイス面(第1の主面)
1b ウエハの裏面
1e エピタキシャル層(n型エピタキシャル層)
1s n+シリコン基板部
2 n型ドリフト領域
3 p型チャネル領域(p型ベース領域)
4 n+ソース領域
5 p+ボディ・コンタクト領域
6 トレンチ・ゲート電極(ポリシリコン電極)
6d ダミー・トレンチ・ゲート電極(ポリシリコン電極)
7 ゲート絶縁膜
8 チップ又はチップ領域
9 レジスト膜
10 SBD領域
10a SBD主要部
11 ソース・パッド
12 セル領域(トレンチ・ゲート・セル部)
13 ゲート・パッド
14 スクライブ領域(ダイシング領域)
15 p型ウエル領域
19 ガード・リング
20 ドレイン電極
21 層間絶縁膜
22 凹部(ソース・コンタクト溝)
23 バリア・メタル膜
23a 下層バリア・メタル膜(第1層膜)
23b 上層バリア・メタル膜(第2層膜)
24 アルミニウム系メタル膜(ソース電極)
24s シード・アルミニウム系メタル膜部
25 凹部底面上段
26 凹部底面下段
51 マルチ・チャンバ型ウエハ処理装置
52 ロード・ポート(または前室)
53 ウエハ搬送容器(ウエハ・カセット)
54 ロード・ロック室
55 真空搬送室
56 脱ガス・チャンバ
57 スパッタ・エッチング・チャンバ
58 TiW用PCMイオン化スパッタ成膜チャンバ
59 TiW用LTスパッタ成膜チャンバ
61 アルミニウム系メタル膜スパッタリング・チャンバ
62 下部電極(ウエハ・ステージ)
63 下部電極高周波バイアス電源(第2の高周波電力)
64 静電チャック制御系
65 静電チャック電極
66 上部電極(ターゲット・バッキング・プレート)
67 ターゲット
68 マグネット保持回転テーブル
71 マグネット(S極)
72 マグネット(N極)
73 回転軸
74 上部電極直流バイアス電源(直流バイアス)
75 上部電極高周波電源(第1の高周波電力)
76 プラズマ
77 ガス供給制御系
78 ガス供給経路
79 真空排気系
81 排気口
B 溝底部分
G セル繰り返し単位領域
R SBD部および帯状繰り返しデバイス・パターン領域切り出し部分
Claims (16)
- 以下の工程を含む半導体装置の製造方法:
(a)半導体ウエハの第1の主面上の第1の絶縁膜の上面から下方に向けて、凹部を形成する工程;
(b)前記凹部の内面及び前記第1の絶縁膜の前記上面に、タングステン系バリア・メタル膜を形成する工程;
(c)前記工程(b)の後、前記凹部の内面および前記第1の絶縁膜の前記上面の前記タングステン系バリア・メタル膜を覆うように、アルミニウム系メタル層を形成する工程、
ここで、前記工程(b)は、以下の下位工程を含む:
(b1)前記半導体ウエハにバイアス電圧を印加しながらイオン化スパッタ成膜により、前記凹部の内面及び前記第1の絶縁膜の前記上面に、前記タングステン系バリア・メタル膜の内の第1層膜を形成する工程;
(b2)前記半導体ウエハにバイアス電圧を実質的に印加しないスパッタ成膜により、前記第1層膜上に、前記タングステン系バリア・メタル膜の内の第2層膜を形成する工程。 - 前記1項の半導体装置の製造方法において、前記工程(b)において、前記タングステン系バリア・メタル膜は、タングステンを主要な成分として含み、チタンを副次的な成分として含む。
- 前記1項の半導体装置の製造方法において、前記第1層膜は、主にアモルファス構造を呈している。
- 前記3項の半導体装置の製造方法において、前記第2層膜は、主に柱状結晶構造を呈している。
- 前記1項の半導体装置の製造方法において、前記下位工程(b1)と(b2)は、同一の成膜チャンバ内で行われる。
- 前記1項の半導体装置の製造方法において、前記下位工程(b1)と(b2)は、それぞれ異なる成膜チャンバ内で行われる。
- 前記1項の半導体装置の製造方法において、前記下位工程(b2)は、スパッタ・ターゲットに高周波バイアス電圧を実質的に印加しないで実行される。
- 前記1項の半導体装置の製造方法において、前記半導体ウエハの前記第1の主面上には、多数の半導体チップ領域があり、各チップ領域には、ショットキ・バリア・ダイオードが形成される。
- 前記8項の半導体装置の製造方法において、各チップ領域には、パワーMOSFETが形成される。
- 前記1項の半導体装置の製造方法において、前記凹部は、2段構造を呈している。
- 以下の工程を含む半導体装置の製造方法:
(a)半導体ウエハの第1の主面上の第1の絶縁膜の上面から下方に向けて、凹部を形成する工程;
(b)前記凹部の内面及び前記第1の絶縁膜の前記上面に、前記半導体ウエハにバイアス電圧を印加しながらイオン化スパッタ成膜により、前記凹部の内面及び前記第1の絶縁膜の前記上面に、タングステン系バリア・メタル膜を形成する工程;
(c)前記工程(b)の後、前記凹部の内面および前記第1の絶縁膜の前記上面の前記タングステン系バリア・メタル膜を覆うように、アルミニウム系メタル層を形成する工程。 - 前記11項の半導体装置の製造方法において、前記工程(b)において、前記タングステン系バリア・メタル膜は、タングステンを主要な成分として含み、チタンを副次的な成分として含む。
- 前記11項の半導体装置の製造方法において、前記タングステン系バリア・メタル膜は、主にアモルファス構造を呈する層を有する。
- 前記11項の半導体装置の製造方法において、前記半導体ウエハの前記第1の主面上には、多数の半導体チップ領域があり、各チップ領域には、ショットキ・バリア・ダイオードが形成される。
- 前記14項の半導体装置の製造方法において、各チップ領域には、パワーMOSFETが形成される。
- 前記11項の半導体装置の製造方法において、前記凹部は、2段構造を呈している。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2009119641A JP5612830B2 (ja) | 2009-05-18 | 2009-05-18 | 半導体装置の製造方法 |
US12/727,337 US9177813B2 (en) | 2009-05-18 | 2010-03-19 | Manufacturing method of semiconductor device |
US14/867,400 US20160020107A1 (en) | 2009-05-18 | 2015-09-28 | Manufacturing method of semiconductor device |
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US9177813B2 (en) | 2015-11-03 |
US20160020107A1 (en) | 2016-01-21 |
JP5612830B2 (ja) | 2014-10-22 |
US20100291767A1 (en) | 2010-11-18 |
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