JP5596296B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5596296B2 JP5596296B2 JP2009062364A JP2009062364A JP5596296B2 JP 5596296 B2 JP5596296 B2 JP 5596296B2 JP 2009062364 A JP2009062364 A JP 2009062364A JP 2009062364 A JP2009062364 A JP 2009062364A JP 5596296 B2 JP5596296 B2 JP 5596296B2
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- field effect
- effect transistor
- power supply
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009062364A JP5596296B2 (ja) | 2008-03-17 | 2009-03-16 | 半導体装置 |
| KR1020090022250A KR101046556B1 (ko) | 2008-03-17 | 2009-03-16 | 단일 종단 감지 증폭기를 갖는 반도체 디바이스 |
| TW098108434A TWI399754B (zh) | 2008-03-17 | 2009-03-16 | 具有單端感測放大器之半導體裝置 |
| US12/382,495 US8045360B2 (en) | 2008-03-17 | 2009-03-17 | Semiconductor device having single-ended sensing amplifier |
| CN2009101289465A CN101540189B (zh) | 2008-03-17 | 2009-03-17 | 具有单端读出放大器的半导体器件 |
| US13/137,854 US8310887B2 (en) | 2008-03-17 | 2011-09-19 | Semiconductor device having single-ended sensing amplifier |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008068162 | 2008-03-17 | ||
| JP2008068162 | 2008-03-17 | ||
| JP2009062364A JP5596296B2 (ja) | 2008-03-17 | 2009-03-16 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009259379A JP2009259379A (ja) | 2009-11-05 |
| JP2009259379A5 JP2009259379A5 (enExample) | 2011-05-19 |
| JP5596296B2 true JP5596296B2 (ja) | 2014-09-24 |
Family
ID=41163854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009062364A Expired - Fee Related JP5596296B2 (ja) | 2008-03-17 | 2009-03-16 | 半導体装置 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US8045360B2 (enExample) |
| JP (1) | JP5596296B2 (enExample) |
| KR (1) | KR101046556B1 (enExample) |
| CN (1) | CN101540189B (enExample) |
| TW (1) | TWI399754B (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101046556B1 (ko) * | 2008-03-17 | 2011-07-05 | 엘피다 메모리 가부시키가이샤 | 단일 종단 감지 증폭기를 갖는 반도체 디바이스 |
| US8619483B2 (en) | 2009-08-27 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuits, systems, and methods for accessing the memory circuits |
| JP5451281B2 (ja) | 2009-09-16 | 2014-03-26 | ピーエスフォー ルクスコ エスエイアールエル | センスアンプ回路及びそれを備えた半導体装置 |
| JP2012104165A (ja) * | 2010-11-05 | 2012-05-31 | Elpida Memory Inc | 半導体装置 |
| KR20120101838A (ko) | 2011-03-07 | 2012-09-17 | 삼성전자주식회사 | 계층적 비트라인 구조를 갖는 반도체 메모리 장치 |
| US20140140124A1 (en) * | 2012-11-21 | 2014-05-22 | Dong-seok Kang | Resistive memory device having selective sensing operation and access control method thereof |
| US8934286B2 (en) | 2013-01-23 | 2015-01-13 | International Business Machines Corporation | Complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier |
| KR102003861B1 (ko) | 2013-02-28 | 2019-10-01 | 에스케이하이닉스 주식회사 | 반도체 장치, 프로세서 및 시스템 |
| US9093175B2 (en) | 2013-03-27 | 2015-07-28 | International Business Machines Corporation | Signal margin centering for single-ended eDRAM sense amplifier |
| JP2015222610A (ja) * | 2015-06-29 | 2015-12-10 | スパンション エルエルシー | 半導体メモリ |
| US9589604B1 (en) * | 2015-09-17 | 2017-03-07 | International Business Machines Corporation | Single ended bitline current sense amplifier for SRAM applications |
| DE102017204670A1 (de) * | 2017-03-21 | 2018-09-27 | Robert Bosch Gmbh | Sensoreinrichtung und Überwachungsverfahren |
| KR102755184B1 (ko) | 2017-06-27 | 2025-01-14 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 기억 장치 |
| WO2019073333A1 (ja) | 2017-10-13 | 2019-04-18 | 株式会社半導体エネルギー研究所 | 記憶装置、電子部品、及び電子機器 |
| TW202431270A (zh) * | 2019-03-29 | 2024-08-01 | 日商半導體能源研究所股份有限公司 | 半導體裝置 |
Family Cites Families (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5625602A (en) * | 1991-11-18 | 1997-04-29 | Kabushiki Kaisha Toshiba | NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines |
| US6411549B1 (en) * | 2000-06-21 | 2002-06-25 | Atmel Corporation | Reference cell for high speed sensing in non-volatile memories |
| US6822904B2 (en) * | 2001-01-03 | 2004-11-23 | Micron Technology, Inc. | Fast sensing scheme for floating-gate memory cells |
| ITRM20010001A1 (it) * | 2001-01-03 | 2002-07-03 | Micron Technology Inc | Circuiteria di rilevazione per memorie flash a bassa tensione. |
| US6697283B2 (en) * | 2001-01-03 | 2004-02-24 | Micron Technology, Inc. | Temperature and voltage compensated reference current generator |
| US6678198B2 (en) * | 2001-03-16 | 2004-01-13 | Broadcom Corporation | Pseudo differential sensing method and apparatus for DRAM cell |
| US6438051B1 (en) * | 2001-05-31 | 2002-08-20 | International Business Machines Corporation | Stabilized direct sensing memory architecture |
| JP4012151B2 (ja) * | 2002-02-28 | 2007-11-21 | 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置 |
| US6590804B1 (en) * | 2002-07-16 | 2003-07-08 | Hewlett-Packard Development Company, L.P. | Adjustable current mode differential amplifier |
| JP4154967B2 (ja) * | 2002-09-13 | 2008-09-24 | 松下電器産業株式会社 | 半導体記憶装置および駆動方法 |
| US6760268B2 (en) * | 2002-11-26 | 2004-07-06 | Freescale Semiconductor, Inc. | Method and apparatus for establishing a reference voltage in a memory |
| JP4219663B2 (ja) * | 2002-11-29 | 2009-02-04 | 株式会社ルネサステクノロジ | 半導体記憶装置及び半導体集積回路 |
| JP2004234791A (ja) * | 2003-01-31 | 2004-08-19 | Sony Corp | 半導体記憶装置 |
| JP4189269B2 (ja) * | 2003-05-27 | 2008-12-03 | シャープ株式会社 | 不揮発性半導体記憶装置、その書き込み・リセット方法、及び、その読み出し方法 |
| US7099216B2 (en) * | 2003-09-05 | 2006-08-29 | International Business Machines Corporation | Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing |
| US7027326B2 (en) * | 2004-01-05 | 2006-04-11 | International Business Machines Corporation | 3T1D memory cells using gated diodes and methods of use thereof |
| US7224635B2 (en) * | 2005-03-04 | 2007-05-29 | Atmel Corporation | Fast read port for register file |
| JP2007133987A (ja) * | 2005-11-11 | 2007-05-31 | Toshiba Corp | 半導体記憶装置および半導体記憶装置の駆動方法 |
| US7499344B2 (en) | 2006-01-05 | 2009-03-03 | Infineon Technologies Ag | Integrated circuit memory having a read circuit |
| JP2007334925A (ja) * | 2006-06-12 | 2007-12-27 | Nec Electronics Corp | 不揮発性半導体記憶装置 |
| US7433254B2 (en) * | 2006-07-26 | 2008-10-07 | Agere Systems Inc. | Accelerated single-ended sensing for a memory circuit |
| US7499312B2 (en) * | 2007-01-05 | 2009-03-03 | International Business Machines Corporation | Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line |
| JP5594927B2 (ja) * | 2007-04-11 | 2014-09-24 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置 |
| JP2008294310A (ja) * | 2007-05-25 | 2008-12-04 | Elpida Memory Inc | 半導体記憶装置 |
| US7813163B2 (en) * | 2007-09-05 | 2010-10-12 | International Business Machines Corporation | Single-ended read and differential write scheme |
| TWI360620B (en) * | 2007-11-30 | 2012-03-21 | Foxconn Tech Co Ltd | Led lamp |
| JP5490432B2 (ja) * | 2008-03-17 | 2014-05-14 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
| TWI398874B (zh) * | 2008-03-17 | 2013-06-11 | Elpida Memory Inc | 具有單端感測放大器之半導體裝置 |
| KR101046556B1 (ko) * | 2008-03-17 | 2011-07-05 | 엘피다 메모리 가부시키가이샤 | 단일 종단 감지 증폭기를 갖는 반도체 디바이스 |
| KR101050699B1 (ko) * | 2008-04-04 | 2011-07-20 | 엘피다 메모리 가부시키가이샤 | 반도체 메모리 디바이스 |
| JP5433187B2 (ja) * | 2008-08-28 | 2014-03-05 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置及びそのテスト方法 |
| JP5518313B2 (ja) * | 2008-08-29 | 2014-06-11 | ピーエスフォー ルクスコ エスエイアールエル | センスアンプ回路及び半導体記憶装置 |
| JP5680819B2 (ja) * | 2008-08-29 | 2015-03-04 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | センスアンプ回路及び半導体記憶装置 |
| JP5359804B2 (ja) * | 2009-11-16 | 2013-12-04 | ソニー株式会社 | 不揮発性半導体メモリデバイス |
-
2009
- 2009-03-16 KR KR1020090022250A patent/KR101046556B1/ko not_active Expired - Fee Related
- 2009-03-16 JP JP2009062364A patent/JP5596296B2/ja not_active Expired - Fee Related
- 2009-03-16 TW TW098108434A patent/TWI399754B/zh active
- 2009-03-17 CN CN2009101289465A patent/CN101540189B/zh not_active Expired - Fee Related
- 2009-03-17 US US12/382,495 patent/US8045360B2/en active Active
-
2011
- 2011-09-19 US US13/137,854 patent/US8310887B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR101046556B1 (ko) | 2011-07-05 |
| CN101540189B (zh) | 2013-08-14 |
| CN101540189A (zh) | 2009-09-23 |
| KR20090099490A (ko) | 2009-09-22 |
| TW201001433A (en) | 2010-01-01 |
| US20120008368A1 (en) | 2012-01-12 |
| US8045360B2 (en) | 2011-10-25 |
| TWI399754B (zh) | 2013-06-21 |
| US8310887B2 (en) | 2012-11-13 |
| JP2009259379A (ja) | 2009-11-05 |
| US20090257268A1 (en) | 2009-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5596296B2 (ja) | 半導体装置 | |
| JP5490432B2 (ja) | 半導体装置 | |
| JP5554935B2 (ja) | 半導体装置 | |
| US20090147596A1 (en) | Method to improve the write speed for memory products | |
| US20100195415A1 (en) | Semiconductor memory device and reading method therefor | |
| JP4994135B2 (ja) | センス増幅回路およびセンス増幅方法 | |
| US7965569B2 (en) | Semiconductor storage device | |
| JP2009266364A (ja) | 半導体記憶装置 | |
| CN102265396A (zh) | 电容隔离的失配补偿型读出放大器 | |
| KR20010029712A (ko) | 반도체 메모리 장치 | |
| JP2011103158A (ja) | 半導体不揮発記憶回路 | |
| US6185142B1 (en) | Apparatus for a semiconductor memory with independent reference voltage | |
| JP3904359B2 (ja) | 半導体mos/バイポーラ複合トランジスタを利用した半導体メモリ素子 | |
| WO2019087769A1 (ja) | 抵抗変化型メモリ装置の読み出し回路及びその読み出し方法 | |
| US7123529B1 (en) | Sense amplifier including multiple conduction state field effect transistor | |
| CN115527586B (zh) | 一种rram的读取电路及读取方法 | |
| JP3154502B2 (ja) | 信号増幅回路及びこれを用いた半導体メモリ装置 | |
| JP2014130676A (ja) | 半導体装置 | |
| JPH10241357A (ja) | 半導体装置 | |
| JPH05274882A (ja) | 半導体記憶装置 | |
| JP2000298989A (ja) | Sram読み出し回路およびsram読み出し方法 | |
| WO1992022070A1 (en) | Static memories and methods of reading static memories | |
| JP2014179161A (ja) | 半導体装置 | |
| JPH043597B2 (enExample) | ||
| JPH04212787A (ja) | メモリ装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110406 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120105 |
|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20130730 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130822 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20131121 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20131126 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20140214 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20140219 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140522 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140603 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140708 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140807 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5596296 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| LAPS | Cancellation because of no payment of annual fees |