JP5571693B2 - 歪誘起合金及び段階的なドーパントプロファイルを含むその場で形成されるドレイン及びソース領域 - Google Patents

歪誘起合金及び段階的なドーパントプロファイルを含むその場で形成されるドレイン及びソース領域 Download PDF

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JP5571693B2
JP5571693B2 JP2011546707A JP2011546707A JP5571693B2 JP 5571693 B2 JP5571693 B2 JP 5571693B2 JP 2011546707 A JP2011546707 A JP 2011546707A JP 2011546707 A JP2011546707 A JP 2011546707A JP 5571693 B2 JP5571693 B2 JP 5571693B2
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dopant
strain
forming
drain
source
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JP2012516557A (ja
JP2012516557A5 (enExample
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ホエンチェル ジャン
パパゲオルギウ ヴァシリオス
グリーベナウ ウべ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2011546707A 2009-01-30 2010-01-27 歪誘起合金及び段階的なドーパントプロファイルを含むその場で形成されるドレイン及びソース領域 Active JP5571693B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102009006884A DE102009006884B4 (de) 2009-01-30 2009-01-30 Verfahren zur Herstellung eines Transistorbauelementes mit In-Situ erzeugten Drain- und Source-Gebieten mit einer verformungsinduzierenden Legierung und einem graduell variierenden Dotierstoffprofil und entsprechendes Transistorbauelement
DE102009006884.8 2009-01-30
US12/688,999 US8278174B2 (en) 2009-01-30 2010-01-18 In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profile
US12/688,999 2010-01-18
PCT/EP2010/000492 WO2010086154A1 (en) 2009-01-30 2010-01-27 In situ formed drain and source regions including a strain inducing alloy and a graded dopant profile

Publications (3)

Publication Number Publication Date
JP2012516557A JP2012516557A (ja) 2012-07-19
JP2012516557A5 JP2012516557A5 (enExample) 2013-03-07
JP5571693B2 true JP5571693B2 (ja) 2014-08-13

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JP2011546707A Active JP5571693B2 (ja) 2009-01-30 2010-01-27 歪誘起合金及び段階的なドーパントプロファイルを含むその場で形成されるドレイン及びソース領域

Country Status (5)

Country Link
US (1) US8278174B2 (enExample)
JP (1) JP5571693B2 (enExample)
KR (1) KR101605150B1 (enExample)
CN (1) CN102388442A (enExample)
DE (1) DE102009006884B4 (enExample)

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Also Published As

Publication number Publication date
JP2012516557A (ja) 2012-07-19
KR101605150B1 (ko) 2016-03-21
KR20110113761A (ko) 2011-10-18
DE102009006884A1 (de) 2010-08-12
US8278174B2 (en) 2012-10-02
CN102388442A (zh) 2012-03-21
US20100193882A1 (en) 2010-08-05
DE102009006884B4 (de) 2011-06-30

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