JP5563785B2 - 半導体パッケージ及びその製造方法 - Google Patents

半導体パッケージ及びその製造方法 Download PDF

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JP5563785B2
JP5563785B2 JP2009117921A JP2009117921A JP5563785B2 JP 5563785 B2 JP5563785 B2 JP 5563785B2 JP 2009117921 A JP2009117921 A JP 2009117921A JP 2009117921 A JP2009117921 A JP 2009117921A JP 5563785 B2 JP5563785 B2 JP 5563785B2
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electrode
substrate
layer
semiconductor package
insulating film
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Japanese (ja)
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JP2010267805A (ja
JP2010267805A5 (enExample
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昌宏 春原
裕一 田口
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2009117921A priority Critical patent/JP5563785B2/ja
Priority to US12/760,419 priority patent/US8212355B2/en
Publication of JP2010267805A publication Critical patent/JP2010267805A/ja
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JP6035520B2 (ja) 2012-04-26 2016-11-30 パナソニックＩｐマネジメント株式会社 半導体装置およびその製造方法
US9627346B2 (en) * 2013-12-11 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill pattern with gap
JP2015159197A (ja) * 2014-02-24 2015-09-03 新光電気工業株式会社 配線基板及びその製造方法
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JP6557953B2 (ja) * 2014-09-09 2019-08-14 大日本印刷株式会社 構造体及びその製造方法
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US10131540B2 (en) * 2015-03-12 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method to mitigate soldering offset for wafer-level chip scale package (WLCSP) applications
JP6625491B2 (ja) * 2016-06-29 2019-12-25 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法
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