JP5563785B2 - 半導体パッケージ及びその製造方法 - Google Patents

半導体パッケージ及びその製造方法 Download PDF

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JP5563785B2
JP5563785B2 JP2009117921A JP2009117921A JP5563785B2 JP 5563785 B2 JP5563785 B2 JP 5563785B2 JP 2009117921 A JP2009117921 A JP 2009117921A JP 2009117921 A JP2009117921 A JP 2009117921A JP 5563785 B2 JP5563785 B2 JP 5563785B2
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electrode
substrate
layer
semiconductor package
insulating film
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Japanese (ja)
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JP2010267805A5 (enExample
JP2010267805A (ja
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昌宏 春原
裕一 田口
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2009117921A priority Critical patent/JP5563785B2/ja
Priority to US12/760,419 priority patent/US8212355B2/en
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    • H—ELECTRICITY
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
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    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
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    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
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    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
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    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
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    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
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    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
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    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7426—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
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    • H10W20/071—Manufacture or treatment of dielectric parts thereof
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    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/019—Manufacture or treatment of bond pads
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    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
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    • H10W72/221—Structures or relative sizes
    • H10W72/224—Bumps having multiple side-by-side cores
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    • H10W72/231—Shapes
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    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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JP2009117921A 2009-05-14 2009-05-14 半導体パッケージ及びその製造方法 Active JP5563785B2 (ja)

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JP2009117921A JP5563785B2 (ja) 2009-05-14 2009-05-14 半導体パッケージ及びその製造方法
US12/760,419 US8212355B2 (en) 2009-05-14 2010-04-14 Semiconductor package and manufacturing method of the semiconductor package

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JP2009117921A JP5563785B2 (ja) 2009-05-14 2009-05-14 半導体パッケージ及びその製造方法

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JP2010267805A JP2010267805A (ja) 2010-11-25
JP2010267805A5 JP2010267805A5 (enExample) 2012-04-26
JP5563785B2 true JP5563785B2 (ja) 2014-07-30

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JP2015159197A (ja) * 2014-02-24 2015-09-03 新光電気工業株式会社 配線基板及びその製造方法
JP2015173150A (ja) * 2014-03-11 2015-10-01 新光電気工業株式会社 半導体パッケージ
JP6557953B2 (ja) * 2014-09-09 2019-08-14 大日本印刷株式会社 構造体及びその製造方法
US9368442B1 (en) * 2014-12-28 2016-06-14 Unimicron Technology Corp. Method for manufacturing an interposer, interposer and chip package structure
US10131540B2 (en) * 2015-03-12 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method to mitigate soldering offset for wafer-level chip scale package (WLCSP) applications
JP6625491B2 (ja) * 2016-06-29 2019-12-25 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法
CN109378300B (zh) * 2016-11-27 2020-05-15 乐清市风杰电子科技有限公司 晶圆封装结构
KR102041599B1 (ko) * 2018-11-22 2019-11-06 삼성전기주식회사 패키지 구조물

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JP5032456B2 (ja) * 2008-08-12 2012-09-26 新光電気工業株式会社 半導体装置、インターポーザ、及びそれらの製造方法

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