JP5471268B2 - 貫通電極基板及びその製造方法 - Google Patents

貫通電極基板及びその製造方法 Download PDF

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Publication number
JP5471268B2
JP5471268B2 JP2009233412A JP2009233412A JP5471268B2 JP 5471268 B2 JP5471268 B2 JP 5471268B2 JP 2009233412 A JP2009233412 A JP 2009233412A JP 2009233412 A JP2009233412 A JP 2009233412A JP 5471268 B2 JP5471268 B2 JP 5471268B2
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Prior art keywords
electrode
substrate
hole
layer
resin layer
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JP2009233412A
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English (en)
Japanese (ja)
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JP2010171377A5 (enExample
JP2010171377A (ja
Inventor
浩一 中山
陽一 人見
貴正 高野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
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Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP2009233412A priority Critical patent/JP5471268B2/ja
Priority to US12/628,712 priority patent/US8198726B2/en
Publication of JP2010171377A publication Critical patent/JP2010171377A/ja
Priority to US13/466,514 priority patent/US8623751B2/en
Publication of JP2010171377A5 publication Critical patent/JP2010171377A5/ja
Application granted granted Critical
Publication of JP5471268B2 publication Critical patent/JP5471268B2/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1178—Means for venting or for letting gases escape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2009233412A 2008-12-26 2009-10-07 貫通電極基板及びその製造方法 Active JP5471268B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009233412A JP5471268B2 (ja) 2008-12-26 2009-10-07 貫通電極基板及びその製造方法
US12/628,712 US8198726B2 (en) 2008-12-26 2009-12-01 Through-hole electrode substrate and method of manufacturing the same
US13/466,514 US8623751B2 (en) 2008-12-26 2012-05-08 Through-hole electrode substrate and method of manufacturing the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008332243 2008-12-26
JP2008332243 2008-12-26
JP2009233412A JP5471268B2 (ja) 2008-12-26 2009-10-07 貫通電極基板及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010248721A Division JP4900508B2 (ja) 2008-12-26 2010-11-05 貫通電極基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2010171377A JP2010171377A (ja) 2010-08-05
JP2010171377A5 JP2010171377A5 (enExample) 2012-11-08
JP5471268B2 true JP5471268B2 (ja) 2014-04-16

Family

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Family Applications (1)

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JP2009233412A Active JP5471268B2 (ja) 2008-12-26 2009-10-07 貫通電極基板及びその製造方法

Country Status (2)

Country Link
US (2) US8198726B2 (enExample)
JP (1) JP5471268B2 (enExample)

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JP5455538B2 (ja) * 2008-10-21 2014-03-26 キヤノン株式会社 半導体装置及びその製造方法
JP5471268B2 (ja) * 2008-12-26 2014-04-16 大日本印刷株式会社 貫通電極基板及びその製造方法
JP5644242B2 (ja) * 2009-09-09 2014-12-24 大日本印刷株式会社 貫通電極基板及びその製造方法
DE102010054898A1 (de) 2010-12-17 2012-06-21 Osram Opto Semiconductors Gmbh Träger für einen optoelektronischen Halbleiterchip und Halbleiterchip
JP5605275B2 (ja) * 2011-03-08 2014-10-15 富士通株式会社 半導体装置の製造方法
JP5275400B2 (ja) * 2011-04-18 2013-08-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP5275401B2 (ja) * 2011-04-18 2013-08-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
GB201108425D0 (en) * 2011-05-19 2011-07-06 Zarlink Semiconductor Inc Integrated circuit package
US8829684B2 (en) 2011-05-19 2014-09-09 Microsemi Semiconductor Limited Integrated circuit package
US9691636B2 (en) * 2012-02-02 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer frame and method of manufacturing the same
US8946072B2 (en) * 2012-02-02 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. No-flow underfill for package with interposer frame
US9159699B2 (en) * 2012-11-13 2015-10-13 Delta Electronics, Inc. Interconnection structure having a via structure
US9865524B2 (en) * 2013-04-08 2018-01-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming conductive vias using backside via reveal and selective passivation
JP5558614B1 (ja) * 2013-08-26 2014-07-23 清川メッキ工業株式会社 配線用基板の製造方法
TWI544593B (zh) * 2013-09-09 2016-08-01 矽品精密工業股份有限公司 半導體裝置及其製法
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JP6406598B2 (ja) * 2014-07-24 2018-10-17 学校法人福岡大学 プリント配線板及びその製造方法
JP6557953B2 (ja) 2014-09-09 2019-08-14 大日本印刷株式会社 構造体及びその製造方法
JP6458429B2 (ja) * 2014-09-30 2019-01-30 大日本印刷株式会社 導電材充填貫通電極基板及びその製造方法
JP2016072433A (ja) * 2014-09-30 2016-05-09 大日本印刷株式会社 貫通電極基板及びその製造方法
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JP6648544B2 (ja) * 2016-02-08 2020-02-14 三菱電機株式会社 半導体装置
TWI761852B (zh) * 2016-06-03 2022-04-21 日商大日本印刷股份有限公司 貫通電極基板及其製造方法、以及安裝基板
JP6372546B2 (ja) * 2016-11-15 2018-08-15 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置
CN110050338B (zh) * 2016-12-07 2023-02-28 株式会社村田制作所 电子部件及其制造方法
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Also Published As

Publication number Publication date
US8198726B2 (en) 2012-06-12
US8623751B2 (en) 2014-01-07
US20100164120A1 (en) 2010-07-01
US20120220123A1 (en) 2012-08-30
JP2010171377A (ja) 2010-08-05

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