JP5444124B2 - 拡散バリアを形成する方法、拡散バリア構造体及び半導体デバイスを形成する方法 - Google Patents

拡散バリアを形成する方法、拡散バリア構造体及び半導体デバイスを形成する方法 Download PDF

Info

Publication number
JP5444124B2
JP5444124B2 JP2010123865A JP2010123865A JP5444124B2 JP 5444124 B2 JP5444124 B2 JP 5444124B2 JP 2010123865 A JP2010123865 A JP 2010123865A JP 2010123865 A JP2010123865 A JP 2010123865A JP 5444124 B2 JP5444124 B2 JP 5444124B2
Authority
JP
Japan
Prior art keywords
layer
iridium
tantalum
amorphous
barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010123865A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010283347A (ja
JP2010283347A5 (https=
Inventor
毅 野上
ダニエル・シー．・イーデルスタイン
スティーヴン・エム．・ロスネーゲル
フィリップ・リー・フレイツ
パトリック・ウィリアム・デハヴン
チー−チャオ・ヤン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2010283347A publication Critical patent/JP2010283347A/ja
Publication of JP2010283347A5 publication Critical patent/JP2010283347A5/ja
Application granted granted Critical
Publication of JP5444124B2 publication Critical patent/JP5444124B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2010123865A 2009-06-03 2010-05-31 拡散バリアを形成する方法、拡散バリア構造体及び半導体デバイスを形成する方法 Expired - Fee Related JP5444124B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/477,389 US7951708B2 (en) 2009-06-03 2009-06-03 Copper interconnect structure with amorphous tantalum iridium diffusion barrier
US12/477389 2009-06-03

Publications (3)

Publication Number Publication Date
JP2010283347A JP2010283347A (ja) 2010-12-16
JP2010283347A5 JP2010283347A5 (https=) 2013-09-12
JP5444124B2 true JP5444124B2 (ja) 2014-03-19

Family

ID=43263917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010123865A Expired - Fee Related JP5444124B2 (ja) 2009-06-03 2010-05-31 拡散バリアを形成する方法、拡散バリア構造体及び半導体デバイスを形成する方法

Country Status (4)

Country Link
US (1) US7951708B2 (https=)
JP (1) JP5444124B2 (https=)
KR (1) KR101581050B1 (https=)
CN (1) CN101908501A (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6013901B2 (ja) * 2012-12-20 2016-10-25 東京エレクトロン株式会社 Ｃｕ配線の形成方法
KR20160086757A (ko) * 2014-12-09 2016-07-20 인텔 코포레이션 구리 합금 도전성 루트 구조체를 갖는 마이크로전자 기판
US9875958B1 (en) 2016-11-09 2018-01-23 International Business Machines Corporation Trace/via hybrid structure and method of manufacture
KR102624631B1 (ko) 2016-12-02 2024-01-12 삼성전자주식회사 반도체 장치
US10211052B1 (en) * 2017-09-22 2019-02-19 Lam Research Corporation Systems and methods for fabrication of a redistribution layer to avoid etching of the layer
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
KR102747527B1 (ko) 2018-06-30 2024-12-31 램 리써치 코포레이션 라이너 패시베이션 및 접착 개선을 위한 금속 라이너의 징케이팅 (zincating) 및 도핑
WO2021108252A1 (en) 2019-11-25 2021-06-03 Lam Research Corporation Doping processes in metal interconnect structures
JP2021144969A (ja) * 2020-03-10 2021-09-24 キオクシア株式会社 磁気記憶装置
US11107731B1 (en) 2020-03-30 2021-08-31 International Business Machines Corporation Self-aligned repaired top via
CN114373714A (zh) * 2020-10-15 2022-04-19 长鑫存储技术有限公司 半导体结构的制作方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8303298D0 (en) * 1983-02-07 1983-03-09 Gen Electric Co Plc Temperature sensors
NL8800857A (nl) * 1988-04-05 1989-11-01 Philips Nv Inrichting en werkwijze voor het vervaardigen van een inrichting.
NL8802873A (nl) * 1988-11-22 1990-06-18 Philips Nv Zachtmagnetische multilaagfilm en magneetkop voorzien van een dergelijke zachtmagnetische multilaagfilm.
EP0428730B1 (en) * 1989-02-28 1995-07-12 Canon Kabushiki Kaisha Ink jet head having heat-generating resistor constituted of non-monocrystalline substance containing iridium, tantalum and aluminum, and ink jet device equipped with said head
JP2757797B2 (ja) * 1994-11-10 1998-05-25 日本電気株式会社 配線層形成方法およびその装置
US6181012B1 (en) * 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
US6294836B1 (en) * 1998-12-22 2001-09-25 Cvc Products Inc. Semiconductor chip interconnect barrier material and fabrication method
US6812143B2 (en) * 2002-04-26 2004-11-02 International Business Machines Corporation Process of forming copper structures
US6787912B2 (en) * 2002-04-26 2004-09-07 International Business Machines Corporation Barrier material for copper structures
US7205662B2 (en) * 2003-02-27 2007-04-17 Symmorphix, Inc. Dielectric barrier layer films
US20050263891A1 (en) * 2004-05-28 2005-12-01 Bih-Huey Lee Diffusion barrier for damascene structures
JP4832807B2 (ja) * 2004-06-10 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置
US20060251872A1 (en) * 2005-05-05 2006-11-09 Wang Jenn Y Conductive barrier layer, especially an alloy of ruthenium and tantalum and sputter deposition thereof
US7999330B2 (en) * 2005-06-24 2011-08-16 Micron Technology, Inc. Dynamic random access memory device and electronic systems
US7727888B2 (en) * 2005-08-31 2010-06-01 International Business Machines Corporation Interconnect structure and method for forming the same
EP2003226B1 (en) * 2006-02-22 2013-04-24 JX Nippon Mining & Metals Corporation Sintered sputtering target made of high-melting metals
JP5285898B2 (ja) * 2007-12-17 2013-09-11 Ｊｘ日鉱日石金属株式会社 銅拡散防止用バリア膜、同バリア膜の形成方法、ダマシン銅配線用シード層の形成方法及びダマシン銅配線を備えた半導体ウェハー

Also Published As

Publication number Publication date
KR101581050B1 (ko) 2015-12-30
US7951708B2 (en) 2011-05-31
JP2010283347A (ja) 2010-12-16
KR20100130551A (ko) 2010-12-13
US20100311236A1 (en) 2010-12-09
CN101908501A (zh) 2010-12-08

Similar Documents

Publication Publication Date Title
JP5444124B2 (ja) 拡散バリアを形成する方法、拡散バリア構造体及び半導体デバイスを形成する方法
US7718524B2 (en) Method of manufacturing semiconductor device
US8232195B2 (en) Method for fabricating back end of the line structures with liner and seed materials
KR101857915B1 (ko) 상호접속 구조물 및 상호접속 구조물의 형성 방법
JP2007281485A (ja) 狭いトレンチ中でスーパー第２結晶粒の成長を発生させる方法
US7193327B2 (en) Barrier structure for semiconductor devices
US8169077B2 (en) Dielectric interconnect structures and methods for forming the same
US7790617B2 (en) Formation of metal silicide layer over copper interconnect for reliability enhancement
TW200849468A (en) Interconnect structure with bi-layer metal cap
US20150076695A1 (en) Selective passivation of vias
JP2019062190A (ja) 銅配線のためのシード層
US7955971B2 (en) Hybrid metallic wire and methods of fabricating same
KR100712358B1 (ko) 반도체 소자의 다마신 배선 형성 방법 및 그에 의해 형성된다마신 배선 구조체
JP2007150298A (ja) 導体−誘電体構造およびこれを作成するための方法
JP4886165B2 (ja) デポジション処理によって、相互接続領域を選択的に合金にする方法
US11164815B2 (en) Bottom barrier free interconnects without voids
JP2008515229A (ja) 後工程のための均一な銅相互接続部及び形成方法
US7638425B2 (en) Metal line of semiconductor device having a diffusion barrier including CRxBy and method for forming the same
CN115084004B (zh) 制造半导体结构的方法及半导体结构
JP2012039019A (ja) 半導体装置およびその製造方法
KR20070066426A (ko) 반도체 소자의 금속배선 형성방법
JP2004014816A (ja) 半導体製造方法および半導体装置
KR20020092731A (ko) 듀얼 다마센 공정을 이용한 금속 배선 형성 방법
JP2000340565A (ja) 半導体集積回路装置およびその製造方法
JP2005311087A (ja) アルミニウム配線の形成方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130215

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130805

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20130805

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20130820

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130924

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131105

RD12 Notification of acceptance of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7432

Effective date: 20131105

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20131107

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131209

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131220

R150 Certificate of patent or registration of utility model

Ref document number: 5444124

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees