JP2007150298A - 導体−誘電体構造およびこれを作成するための方法 - Google Patents
導体−誘電体構造およびこれを作成するための方法 Download PDFInfo
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- JP2007150298A JP2007150298A JP2006310984A JP2006310984A JP2007150298A JP 2007150298 A JP2007150298 A JP 2007150298A JP 2006310984 A JP2006310984 A JP 2006310984A JP 2006310984 A JP2006310984 A JP 2006310984A JP 2007150298 A JP2007150298 A JP 2007150298A
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- seed layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
Abstract
【解決手段】導体−誘電体相互接続構造は、パターン形成されたフィーチャをその内部に有する誘電体層を含む構造を用意し、パターン形成されたフィーチャ内の誘電体層の表面にめっきシード層を付着させ、パターン形成されたフィーチャ内のめっきシード層の表面に犠牲シード層を付着させ、犠牲シード層の厚さを逆めっきによって低減させ、パターン形成されたフィーチャ内の犠牲シード層の表面に導電性金属をめっきすることによって作成される。さらに、パターン形成されたフィーチャをその内部に有する誘電体層と、パターン形成されたフィーチャ内の誘電体層の表面のめっきシード層と、パターン形成されたフィーチャ内に位置する不連続な犠牲シード層とを含む構造も提供される。
【選択図】図1
Description
11 トレンチ
12 トレンチ
13 バイア
14 層間誘電体
15 キャッピング層
16 層間誘電体
17 導電層
18 障壁層
20 デュアル・ダマシン・エッチング断面
21 めっきシード層
31 犠牲シード層
41 薄くされた層
51 不連続な犠牲シード層
71 導電層
Claims (19)
- 導体−誘電体相互接続構造を製造するための方法であって、パターン形成されたフィーチャをその内部に有する誘電体層を含む構造を用意するステップと、前記パターン形成されたフィーチャ内の前記誘電体層の表面にめっきシード層を付着するステップと、前記パターン形成されたフィーチャ内の前記めっきシード層の表面に犠牲シード層を付着するステップと、前記犠牲シード層の厚さを逆めっきによって低減させるステップと、前記パターン形成されたフィーチャ内の前記犠牲シード層の表面に導電材料を付着するステップとを含む方法。
- 前記構造が、シングル・ダマシン構造またはデュアル・ダマシン構造あるいはその両方を含む、請求項1に記載の方法。
- 前記めっきシード層がRuまたはIrあるいはその両方を含む、請求項1に記載の方法。
- 前記犠牲シード層がCuまたはCu合金を含む、請求項1に記載の方法。
- 前記めっきシード層が、RuとTaもしくはRuとTaN、またはRuとTaとTaN、あるいはIrとTaもしくはIrとTaN、またはIrとTaとTaN、あるいはRuとTiSiN、あるいはIrとTiSiNを含む、請求項1に記載の方法。
- 前記犠牲シード層の厚さが約3nmから約100nmである、請求項1に記載の方法。
- 前記犠牲シード層の厚さを、元の厚さの少なくとも50%まで低減させる、請求項1に記載の方法。
- 前記犠牲シード層の厚さを低減させて不連続な犠牲シード層を形成する、請求項1に記載の方法。
- 前記導電材料がCu、Al、Ag、Au、Wおよびこれらの合金からなるグループから選択される、請求項1に記載の方法。
- 前記導電材料がCuまたはCu合金を含む、請求項1に記載の方法。
- 前記導電材料を平坦化するステップをさらに含む、請求項1に記載の方法。
- 前記めっきシード層が、化学蒸着(CVD)または原子層付着(ALD)技法によって付着される、請求項1に記載の方法。
- 前記犠牲シード層が、物理蒸着(PVD)、化学蒸着(CVD)または原子層付着(ALD)技法によって付着される、請求項1に記載の方法。
- 前記犠牲シード層が、前記めっきシードを付着させたプラットホームと同じプラットホームで付着される、請求項13に記載の方法。
- 前記導電材料は、無電解めっきまたは電気めっきによって、前記犠牲シード層の厚さを低減させるめっき浴と同じめっき浴中で、付着される、請求項1に記載の方法。
- パターン形成されたフィーチャをその内部に有する誘電体層と、前記パターン形成されたフィーチャ内の前記誘電体層の表面のめっきシード層と、前記パターン形成されたフィーチャ内の前記めっきシード層の表面に位置する不連続な犠牲シード層とを含む構造。
- 前記めっきシード層がRuまたはIrあるいはその両方を含む、請求項16に記載の構造。
- 前記犠牲シード層がCuまたはCu合金を含む、請求項16に記載の構造。
- 前記犠牲シード層の表面の導電性相互接続をさらに含む、請求項16に記載の構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US11/286093 | 2005-11-23 | ||
US11/286,093 US20070117377A1 (en) | 2005-11-23 | 2005-11-23 | Conductor-dielectric structure and method for fabricating |
Publications (2)
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JP2007150298A true JP2007150298A (ja) | 2007-06-14 |
JP5255198B2 JP5255198B2 (ja) | 2013-08-07 |
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JP2006310984A Expired - Fee Related JP5255198B2 (ja) | 2005-11-23 | 2006-11-17 | 導体−誘電体相互接続構造を製造するための方法 |
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US (2) | US20070117377A1 (ja) |
JP (1) | JP5255198B2 (ja) |
CN (1) | CN100481384C (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009078254A1 (ja) * | 2007-12-17 | 2009-06-25 | Nippon Mining & Metals Co., Ltd. | 基板、及びその製造方法 |
WO2009078255A1 (ja) * | 2007-12-17 | 2009-06-25 | Nippon Mining & Metals Co., Ltd. | 基板、及びその製造方法 |
JP2010171398A (ja) * | 2008-12-26 | 2010-08-05 | Toshiba Corp | 半導体装置の製造方法 |
JP2011510517A (ja) * | 2008-01-22 | 2011-03-31 | 東京エレクトロン株式会社 | 半導体デバイスのCuメタライゼーションへ選択的低温Ru堆積を統合する方法 |
Families Citing this family (7)
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US7402883B2 (en) * | 2006-04-25 | 2008-07-22 | International Business Machines Corporation, Inc. | Back end of the line structures with liner and noble metal layer |
CN101911257B (zh) * | 2008-01-23 | 2012-03-07 | 日矿金属株式会社 | 在阻挡层上具有钌电镀层的ulsi微细配线构件 |
US7745324B1 (en) | 2009-01-09 | 2010-06-29 | International Business Machines Corporation | Interconnect with recessed dielectric adjacent a noble metal cap |
US8399350B2 (en) * | 2010-02-05 | 2013-03-19 | International Business Machines Corporation | Formation of air gap with protection of metal lines |
TW201230245A (en) * | 2011-01-14 | 2012-07-16 | Nat Applied Res Laboratories | Method for synchronously forming diffusion barrier layer and electroplating seed layer of silver interconnects |
US10490448B2 (en) * | 2017-12-29 | 2019-11-26 | Texas Instruments Incorporated | Method of using a sacrificial conductive stack to prevent corrosion |
US11096271B1 (en) * | 2020-04-09 | 2021-08-17 | Raytheon Company | Double-sided, high-density network fabrication |
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JP2001148383A (ja) * | 1999-11-18 | 2001-05-29 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2001185553A (ja) * | 1999-08-30 | 2001-07-06 | Applied Materials Inc | 電気めっき充填を改善する方法 |
JP2002075994A (ja) * | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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2005
- 2005-11-23 US US11/286,093 patent/US20070117377A1/en not_active Abandoned
-
2006
- 2006-11-14 CN CNB2006101635587A patent/CN100481384C/zh not_active Expired - Fee Related
- 2006-11-17 JP JP2006310984A patent/JP5255198B2/ja not_active Expired - Fee Related
-
2008
- 2008-05-29 US US12/128,713 patent/US7960276B2/en not_active Expired - Fee Related
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JP2002515645A (ja) * | 1998-05-12 | 2002-05-28 | セミトゥール・インコーポレイテッド | 被加工片に1つ以上の金属化レベルを形成するのに使用するための方法及び製造ツール構造体 |
JP2001185553A (ja) * | 1999-08-30 | 2001-07-06 | Applied Materials Inc | 電気めっき充填を改善する方法 |
JP2001148383A (ja) * | 1999-11-18 | 2001-05-29 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2002075994A (ja) * | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
WO2004095510A2 (en) * | 2003-04-17 | 2004-11-04 | International Business Machines Corporation | Multilayered cap barrier in microelectronic, interconnect structures |
JP2005213610A (ja) * | 2004-01-30 | 2005-08-11 | Ebara Corp | めっき装置及びめっき方法 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2009078254A1 (ja) * | 2007-12-17 | 2009-06-25 | Nippon Mining & Metals Co., Ltd. | 基板、及びその製造方法 |
WO2009078255A1 (ja) * | 2007-12-17 | 2009-06-25 | Nippon Mining & Metals Co., Ltd. | 基板、及びその製造方法 |
US8247301B2 (en) | 2007-12-17 | 2012-08-21 | Nippon Mining & Metals Co., Ltd. | Substrate and manufacturing method therefor |
KR101186702B1 (ko) * | 2007-12-17 | 2012-09-27 | 닛코킨조쿠 가부시키가이샤 | 기판, 및 그 제조방법 |
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JP2011510517A (ja) * | 2008-01-22 | 2011-03-31 | 東京エレクトロン株式会社 | 半導体デバイスのCuメタライゼーションへ選択的低温Ru堆積を統合する方法 |
JP2010171398A (ja) * | 2008-12-26 | 2010-08-05 | Toshiba Corp | 半導体装置の製造方法 |
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Also Published As
Publication number | Publication date |
---|---|
US7960276B2 (en) | 2011-06-14 |
CN100481384C (zh) | 2009-04-22 |
CN1971876A (zh) | 2007-05-30 |
US20080284019A1 (en) | 2008-11-20 |
JP5255198B2 (ja) | 2013-08-07 |
US20070117377A1 (en) | 2007-05-24 |
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