JP5431777B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5431777B2
JP5431777B2 JP2009101679A JP2009101679A JP5431777B2 JP 5431777 B2 JP5431777 B2 JP 5431777B2 JP 2009101679 A JP2009101679 A JP 2009101679A JP 2009101679 A JP2009101679 A JP 2009101679A JP 5431777 B2 JP5431777 B2 JP 5431777B2
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Japan
Prior art keywords
wafer
insulating film
film pattern
thickness
back surface
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JP2009101679A
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English (en)
Japanese (ja)
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JP2010251632A (ja
JP2010251632A5 (enExample
Inventor
春男 天田
健二 嶋澤
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009101679A priority Critical patent/JP5431777B2/ja
Priority to US12/719,067 priority patent/US8039276B2/en
Publication of JP2010251632A publication Critical patent/JP2010251632A/ja
Priority to US13/237,235 priority patent/US8153452B2/en
Publication of JP2010251632A5 publication Critical patent/JP2010251632A5/ja
Application granted granted Critical
Publication of JP5431777B2 publication Critical patent/JP5431777B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Formation Of Insulating Films (AREA)
JP2009101679A 2009-04-20 2009-04-20 半導体装置の製造方法 Active JP5431777B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009101679A JP5431777B2 (ja) 2009-04-20 2009-04-20 半導体装置の製造方法
US12/719,067 US8039276B2 (en) 2009-04-20 2010-03-08 Manufacturing method of semiconductor device
US13/237,235 US8153452B2 (en) 2009-04-20 2011-09-20 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009101679A JP5431777B2 (ja) 2009-04-20 2009-04-20 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010251632A JP2010251632A (ja) 2010-11-04
JP2010251632A5 JP2010251632A5 (enExample) 2012-04-12
JP5431777B2 true JP5431777B2 (ja) 2014-03-05

Family

ID=42981301

Family Applications (1)

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JP2009101679A Active JP5431777B2 (ja) 2009-04-20 2009-04-20 半導体装置の製造方法

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US (2) US8039276B2 (enExample)
JP (1) JP5431777B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11081344B2 (en) 2018-01-25 2021-08-03 Fujifilm Business Innovation Corp. Method for manufacturing semiconductor substrate

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2953064B1 (fr) * 2009-11-20 2011-12-16 St Microelectronics Tours Sas Procede d'encapsulation de composants electroniques sur tranche
JP5898679B2 (ja) * 2011-06-02 2016-04-06 デンカ株式会社 粘着テープおよび半導体ウエハ加工方法
JP5755043B2 (ja) * 2011-06-20 2015-07-29 株式会社ディスコ 半導体ウエーハの加工方法
JP5846060B2 (ja) * 2011-07-27 2016-01-20 信越化学工業株式会社 ウエハ加工体、ウエハ加工用部材、ウエハ加工用仮接着材、及び薄型ウエハの製造方法
JP5464192B2 (ja) * 2011-09-29 2014-04-09 株式会社デンソー 半導体装置の製造方法
JP5893887B2 (ja) * 2011-10-11 2016-03-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5687647B2 (ja) * 2012-03-14 2015-03-18 株式会社東芝 半導体装置の製造方法、半導体製造装置
JP5591852B2 (ja) * 2012-03-19 2014-09-17 株式会社東芝 半導体装置の検査方法、半導体装置の製造方法、検査用治具
US9318446B2 (en) * 2013-03-15 2016-04-19 Infineon Technologies Austria Ag Metal deposition on substrates
JP6304445B2 (ja) * 2015-03-16 2018-04-04 富士電機株式会社 半導体装置の製造方法
EP3164890B1 (en) * 2015-04-24 2017-11-01 ABB Schweiz AG Method for manufacturing a power semiconductor device with thick top-metal-design
DE102015112649B4 (de) * 2015-07-31 2021-02-04 Infineon Technologies Ag Verfahren zum bilden eines halbleiterbauelements und halbleiterbauelement
JP6658171B2 (ja) 2016-03-22 2020-03-04 富士電機株式会社 半導体装置の製造方法
KR20200101833A (ko) * 2018-01-17 2020-08-28 에스피피 테크놀로지스 컴퍼니 리미티드 와이드 갭 반도체 기판, 와이드 갭 반도체 기판의 제조 장치 및 와이드 갭 반도체 기판의 제조 방법
JP7200537B2 (ja) * 2018-08-21 2023-01-10 富士フイルムビジネスイノベーション株式会社 半導体基板の製造方法
US20200321236A1 (en) * 2019-04-02 2020-10-08 Semiconductor Components Industries, Llc Edge ring removal methods
CN110676207B (zh) * 2019-09-27 2021-11-16 云谷（固安）科技有限公司 分离装置以及分离方法

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JP3184493B2 (ja) * 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
US6162702A (en) * 1999-06-17 2000-12-19 Intersil Corporation Self-supported ultra thin silicon wafer process
JP3834589B2 (ja) * 2001-06-27 2006-10-18 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3620528B2 (ja) 2001-12-12 2005-02-16 株式会社デンソー 半導体装置の製造方法
DE10256985B4 (de) * 2001-12-12 2013-01-10 Denso Corporation Verfahren zur Herstellung eines Leistungshalbleiterbauelements
US6884717B1 (en) * 2002-01-03 2005-04-26 The United States Of America As Represented By The Secretary Of The Air Force Stiffened backside fabrication for microwave radio frequency wafers
JP2004186522A (ja) * 2002-12-05 2004-07-02 Renesas Technology Corp 半導体装置の製造方法
JP4570896B2 (ja) * 2004-04-06 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2005303218A (ja) * 2004-04-16 2005-10-27 Renesas Technology Corp 半導体装置およびその製造方法
JP4020097B2 (ja) 2004-05-11 2007-12-12 セイコーエプソン株式会社 半導体チップ、半導体装置及びその製造方法、並びに電子機器
US20080318362A1 (en) * 2004-07-16 2008-12-25 Chuichi Miyazaki Manufacturing Method of Semiconductor Integrated Circuit Device
JP4904922B2 (ja) 2006-05-26 2012-03-28 トヨタ自動車株式会社 半導体基板製造方法及び半導体基板
JP4816278B2 (ja) * 2006-06-15 2011-11-16 富士電機株式会社 半導体装置の製造方法
JP2008053595A (ja) 2006-08-28 2008-03-06 Toyota Motor Corp 半導体ウエハとその製造方法
JP5007179B2 (ja) * 2007-08-29 2012-08-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11081344B2 (en) 2018-01-25 2021-08-03 Fujifilm Business Innovation Corp. Method for manufacturing semiconductor substrate

Also Published As

Publication number Publication date
US8039276B2 (en) 2011-10-18
JP2010251632A (ja) 2010-11-04
US20100267175A1 (en) 2010-10-21
US8153452B2 (en) 2012-04-10
US20120009695A1 (en) 2012-01-12

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