JP6337217B1 - 厚い上部金属設計を有するパワー半導体デバイスおよびそのパワー半導体デバイスの製造方法 - Google Patents
厚い上部金属設計を有するパワー半導体デバイスおよびそのパワー半導体デバイスの製造方法 Download PDFInfo
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Abstract
Description
本発明の目的は、ブロッキング能力およびオン状態電圧に関して最適化された、すなわち、可能な限り高いブロッキング能力を有し、かつ可能な限り低いオン状態電圧を有するパワー半導体デバイスを製造することができる、パワー半導体デバイスの製造方法を提供することである。
典型的な実施形態において、第1面と第2面との間の距離、すなわち終端領域における絶縁層の上面とアクティブセル領域における金属層の上面との間の高さの違いは、1μm未満である。この典型的な実施形態において、最終デバイスのウェハの厚みは、ウェハを通して非常に均一であることが保証され得る。
Claims (10)
- パワー半導体デバイスの製造方法であって、
第1導電型のウェハ(41)を提供し、前記ウェハ(41)は、第1主面側(42)と当該第1主面側(42)に対向する第2主面側(43)とを有し、前記ウェハ(41)は、前記ウェハ(41)の中央部において、前記第1主面側(42)から前記第2主面側(43)に延びるアクティブセル領域(44)と、前記第1主面側(42)に平行な面上に直角に突出し前記アクティブセル領域(44)を取り囲む終端領域(45)とを含み、
前記アクティブセル領域(44)において前記ウェハ(41)に電気的に接触するために前記第1主面側(42)上に金属層(46;86)を形成し、前記ウェハ(41)から離れる方向を向く前記金属層(46;86)の表面は、前記第1主面側(42)に平行な第1面(B;B’)を規定し、
前記終端領域(45)を覆うように前記第1主面側(42)上に絶縁層(417)を形成し、前記ウェハ(41)から離れる方向を向く前記絶縁層(417)の表面は、前記第1主面側(42)に平行な第2面(A)を規定し;
前記金属層(46;86)を形成するステップの後、および前記絶縁層(417)を形成するステップの後、チャック(421)の平坦面に、その第1主面側で前記ウェハ(41)を装着し;さらに、
その後、前記チャック(421)と研削ホイール(422)との間に圧力を加えることにより前記研削ホイール上に前記ウェハ(41)の前記第2主面側を押し付けながら研削することによって、その第2主面側(43)から前記ウェハ(41)の厚みを薄くし、
前記第2面(A)は、前記第1面(B;B’)よりも前記ウェハ(41)から1μm以下離れ、さらに、
前記金属層(46;86)を形成するステップは、
前記絶縁層(417)を形成するステップの前に、前記アクティブセル領域(44)における前記第1主面側(42)上に前記金属層(46;86)の下部(46a;86a)を形成する第1ステップと、
前記絶縁層(417)を形成するステップの後に、前記アクティブセル領域(44)における前記金属層(46;86)の前記下部(46a;86a)上に前記金属層(46;86)の上部(46b;86b)を形成する第2ステップとを含む、パワー半導体デバイスの製造方法。 - 前記第1面(B)と前記第2面(A)との間の距離は、1μm未満である、請求項1に記載のパワー半導体デバイスの製造方法。
- 前記第1面(B’)は、前記第2面(A)よりも前記ウェハ(41)からさらに離れ、かつ前記第1面(B’)と前記第2面(A)との間の距離は、1μm以上である、請求項1に記載のパワー半導体デバイスの製造方法。
- 前記第1主面側に垂直な方向における前記絶縁層(417)の厚みは、5μm以上である、請求項1〜請求項3のいずれか1項に記載のパワー半導体デバイスの製造方法。
- 前記金属層(46;86)の前記下部(46a;86a)を形成する第1ステップにおいて、同時に少なくとも1つのフィールドプレート(48)が前記終端領域(45)に形成される、請求項1〜請求項4のいずれか1項に記載のパワー半導体デバイスの製造方法。
- 前記第1主面側(42)に近接する前記終端領域(45)において、前記第1導電型とは異なる第2導電型の少なくとも1つの終端層(47)を形成するステップを含み、前記終端層(47)は前記アクティブセル領域(44)を取り囲み、
前記少なくとも1つの終端層(47)は、少なくとも1つの螺旋状に巻かれた層、少なくとも1つのガードリング、および、
横方向に前記アクティブセル領域から離れるにつれて徐々に減少するドーピング濃度を有するVLD層である、請求項1〜請求項5のいずれか1項に記載のパワー半導体デバイスの製造方法。 - 前記少なくとも1つの終端層(47)のそれぞれは、前記終端領域(45)において形成される前記金属層(46;86)の前記下部(46a;86a)の個々の部分(48)に電気的に接続され、前記金属層(46;86)の前記下部(46a;86a)の前記個々の部分(48)は、前記アクティブセル領域(44)に配置された前記金属層(46;86)の前記下部(46a;86a)の任意の部分から物理的および電気的に分離されている、請求項6に記載のパワー半導体デバイスの製造方法。
- 前記絶縁層(417)は、ポリイミドで形成されている、請求項1〜請求項7のいずれか1項に記載のパワー半導体デバイスの製造方法。
- 前記パワー半導体は、絶縁ゲートバイポーラトランジスタであり、前記方法は、前記金属層(46;86)を形成するステップの前に以下のステップを含む:
前記アクティブセル領域(44)において複数のセルを形成するステップであり、各セルは、前記第1導電型とは異なる第2導電型のベース層領域(74;84)と前記第1導電型のエミッタ層領域(73;83)とを少なくとも含み、
前記エミッタ層領域(73;83)は、前記ベース層領域(74;84)によって前記第1導電型を有する前記ウェハ(41)の残りの領域から分離されるように前記ベース層領域(74;84)において形成され、
前記ベース層領域(74;84)および前記エミッタ層領域(73;83)の両方は、前記第1主面側(42)に近接して配置され、さらに、
前記金属層(46;86)は、前記エミッタ層領域(73:83)および前記ベース層領域(74;84)に電気的に接続され;さらに、
前記第1主面側(42)で複数のゲート電極を形成するステップであり、各ゲート電極は、電気的な導電ゲート層(71;81)と第1絶縁層(76;88)と第2絶縁層(72;82)とを含み、前記ゲート層(71)は、前記第1絶縁層(76;88)によって前記ウェハ(41)のいずれかの層から、および前記第2絶縁層(72;82)によって前記金属層(46;86)から、分離されかつ電気的に絶縁される、請求項1〜請求項8のいずれか1項に記載のパワー半導体デバイスの製造方法。 - 前記ウェハ(41)の厚みを薄くするステップの前または後において、前記第2主面側(43)に近接する前記第2導電型のコレクタ層(78)を形成するステップを含み、前記第1導電型のドリフト層(77)は、いずれか1つの前記ベース層領域(74;84)を前記コレクタ層(78)から分離させる、請求項9に記載のパワー半導体デバイスの製造方法。
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