CN109478561B - 半导体装置以及其制造方法 - Google Patents

半导体装置以及其制造方法 Download PDF

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CN109478561B
CN109478561B CN201680087689.3A CN201680087689A CN109478561B CN 109478561 B CN109478561 B CN 109478561B CN 201680087689 A CN201680087689 A CN 201680087689A CN 109478561 B CN109478561 B CN 109478561B
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substrate
electrode
semiconductor device
back surface
cell
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CN109478561A (zh
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高野和丰
松尾一成
平尾柾宜
八寻淳二
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明涉及的半导体装置具备：基板，其具有单元部、包围单元部的终端部；表面构造，其设置于基板之上；以及背面电极，其设置于基板的背面，表面构造在单元部的上部具有向上方凸出的凸部，单元部的至少一部分比终端部薄。

Description

半导体装置以及其制造方法
技术领域
本发明涉及例如用于大电力用途的半导体装置以及其制造方法。
背景技术
在专利文献1中公开了半导体装置。就该半导体装置而言，为了实现低电阻化，使基板的中央部变薄。另外，为了保持强度，使基板的外周部变得比中央部厚。
专利文献1：日本特开2003-303966号公报
发明内容
就专利文献1示出的半导体装置而言，为了使基板的中央部形成得薄，追加有蚀刻等工序。因此，制造工序复杂化。
本发明就是为了解决上述问题而提出的，其目的在于得到能够通过容易的方法而实现低电阻化以及保持强度的半导体装置以及其制造方法。
本发明涉及的半导体装置具备：基板，其具有流过主电流的单元部、包围所述单元部的终端部；表面构造，其设置于所述基板之上；以及背面电极，其设置于所述基板的背面，所述表面构造在所述单元部的上部具有向上方凸出的凸部，所述单元部的至少一部分比所述终端部薄。
本发明涉及的半导体装置的制造方法具备以下工序：表面工序，在基板的表面侧形成表面层，该基板具有单元部、包围所述单元部的终端部；表面构造工序，在实施所述表面工序之后，在所述单元部之上形成具有向上方凸出的凸部的表面构造；粘贴保护膜以覆盖所述表面构造的工序；研磨工序，在粘贴了所述保护膜的状态下，对所述基板的背面进行研磨；背面工序，在所述基板的背面侧形成背面半导体层；以及在实施所述研磨工序之后，在所述背面半导体层的背面形成背面电极的工序。
发明的效果
本发明涉及的半导体装置在表面侧具有凸部。在这种状态下，通过对基板的背面进行研磨，从而能够将基板的与凸部相对的位置形成得薄。因此，不追加工序即可使单元部形成得比终端部薄。因此，本发明涉及的半导体装置能够实现低电阻化以及保持强度，能够通过简单的制造方法而得到。
根据本发明涉及的半导体装置的制造方法，在半导体装置的表面侧形成凸部。在这种状态下，通过对基板的背面进行研磨，从而能够将基板的与凸部相对的位置形成得薄。因此，不追加工序即可使单元部形成得比终端部薄。因此，在本发明涉及的半导体装置的制造方法中，可以通过简单的工序而得到能够实现低电阻化以及保持强度的半导体装置。
附图说明
图1是本发明的实施方式1涉及的半导体装置的剖面图。
图2是表示本发明的实施方式1涉及的半导体装置的制造方法的图。
图3是表示本发明的实施方式1涉及的半导体装置的制造方法的图。
图4是表示本发明的实施方式1涉及的半导体装置的制造方法的图。
图5是表示本发明的实施方式1涉及的半导体装置的制造方法的图。
图6是表示本发明的实施方式1涉及的半导体装置的制造方法的图。
图7是表示本发明的实施方式1涉及的半导体装置的制造方法的图。
图8是对比例涉及的半导体装置的剖面图。
图9是本发明的实施方式1的变形例涉及的半导体装置的剖面图。
图10是本发明的实施方式1的变形例涉及的半导体装置的剖面图。
图11是本发明的实施方式2涉及的半导体装置的俯视图。
图12是本发明的实施方式2涉及的半导体装置的剖面图。
图13是表示本发明的实施方式2涉及的半导体装置的制造方法的图。
图14是表示本发明的实施方式2涉及的半导体装置的制造方法的图。
图15是表示本发明的实施方式2涉及的半导体装置的制造方法的图。
图16是表示本发明的实施方式2涉及的半导体装置的制造方法的图。
图17是表示本发明的实施方式2涉及的半导体装置的制造方法的图。
图18是本发明的实施方式3涉及的半导体装置的俯视图。
图19是本发明的实施方式3涉及的半导体装置的剖面图。
图20是表示本发明的实施方式3涉及的半导体装置的制造方法的图。
图21是表示本发明的实施方式3涉及的半导体装置的制造方法的图。
图22是表示本发明的实施方式3涉及的半导体装置的制造方法的图。
图23是表示本发明的实施方式3涉及的半导体装置的制造方法的图。
图24是表示本发明的实施方式3涉及的半导体装置的制造方法的图。
图25是表示本发明的实施方式3涉及的半导体装置的制造方法的图。
具体实施方式
参照附图对本发明的实施方式涉及的半导体装置以及其制造方法进行说明。对相同或相应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是本发明的实施方式1涉及的半导体装置的剖面图。本实施方式涉及的半导体装置100具有基板30。基板30具有单元部10。单元部10是在基板30形成流过主电流的单元的区域。另外，基板30具有包围单元部10的终端部20。终端部20是在基板30形成边缘端接(edge termination)构造的区域。边缘端接构造是为了对半导体装置100的端部处的电场集中进行抑制而设置的。
本实施方式涉及的半导体装置100是沟槽IGBT(Insulated Gate BipolarTransistor)。基板30具有N型的漂移层31。在单元部10，在漂移层31的表面形成P-型的基极32、N+型的发射极33以及栅极34。栅极34是沟槽栅极。另外，在终端部20，在漂移层31的表面形成FLR(Field Limiting Ring)构造37。在漂移层31的背面形成N型的缓冲层35。在缓冲层35的背面形成P型的集电极36。
在本实施方式中，基板30具有漂移层31、表面层38、背面半导体层39。表面层38是在基板30的表面侧形成的层，包含基极32、发射极33、栅极34以及FLR构造37。另外，背面半导体层39是在基板30的背面侧形成的层，包含缓冲层35以及集电极36。
在栅极34之上设置绝缘层46。另外，在绝缘层46以及基板30之上设置铝电极41。在单元部10的上部，在铝电极41之上设置金属电极42。金属电极42形成在单元部10的上部的整个区域。铝电极41和金属电极42形成表面电极44。
在终端部20的上部，在表面电极44之上设置绝缘膜50。绝缘膜50是以氧化膜及氮化膜为代表的所谓玻璃。绝缘层46、表面电极44、绝缘膜50构成表面构造60。金属电极42的上表面比绝缘膜50的上表面高。因此，表面构造60在单元部10的上部具有向上方凸出的凸部61。
在基板30的背面，以与集电极36接触的方式设置背面电极43。另外，在基板30的背面侧，在与金属电极42相对的位置形成凹部19。通过在基板30的背面侧设置凹部19，从而与终端部20相比较，单元部10变薄。
接下来，对本实施方式涉及的半导体装置100的制造方法进行说明。图2～图7是表示本发明的实施方式1涉及的半导体装置的制造方法的图。首先，实施表面工序。在表面工序中，如图2所示，向基板30进行注入以及扩散，形成漂移层31以及表面层38。然后，实施表面构造工序。在表面构造工序中，首先，在栅极34之上形成绝缘层46。然后，在基板30以及绝缘层46之上形成铝电极41。然后，在终端部20的上部，在铝电极41之上形成绝缘膜50。绝缘膜50是通过玻璃包敷(glass coating)而形成的。
然后，如图3所示，以覆盖单元部10的上部的整个区域的方式，在铝电极41之上形成金属电极42。金属电极42以配置于上表面比绝缘膜50的上表面高的位置的方式而形成。由此，在基板30之上形成表面构造60。表面构造60在单元部10之上具有向上方凸出的凸部61。这里，当在绝缘膜50之上设置焊盘电极的情况下，以配置于金属电极42的上表面比焊盘电极的上表面高的位置的方式而形成金属电极42。金属电极42是以表面构造60的形状成为凸型的方式形成的。
然后，如图4所示，粘贴保护膜80以覆盖表面构造60。保护膜80是用于在晶片研磨时对晶片表面进行保护的粘接片。然后，如图5所示，实施研磨工序。在研磨工序中，首先，将粘贴了保护膜80的状态的晶片以基板30的背面朝上的方式放置于工作台70。此时，保护膜80与工作台70接触。然后，通过研磨机对基板30的背面进行研磨。
这里，就在表面存在凹凸的晶片而言，如果在向晶片表面粘贴了保护膜的状态下，对晶片背面进行研磨，则晶片表面的凹凸被转印到晶片背面。这是因为，由于晶片表面的凹凸，在研磨时施加到晶片的压力在晶片面内是不均匀的。对于在晶片表面具有凸部的部分，在研磨时压力强烈地作用，晶片被研磨得深。另外，对于在晶片表面形成凹部的部分，与工作台之间产生间隙。因此，在研磨时施加的压力变弱，晶片被研磨得浅。
因此，在本实施方式中，在基板30的背面，与凸部61相对的位置被研磨得深。另外，由于表面构造60在单元部10的上部具有凸部61，因此，在终端部20的上部，在保护膜80与工作台70之间形成间隙72。因此，在研磨时向终端部20施加的压力变弱。因此，终端部20与单元部10相比被研磨得浅。由此，单元部10与终端部20相比变薄。
这里，在本实施方式中，设置保护膜80，以使得在研磨时晶片表面的凹凸易于转印到背面。为了使晶片表面的凹凸转印到背面，需要凸部61的形状出现在保护膜80的表面。因此，使保护膜80密接于表面构造60。另外，保护膜80使用薄的保护膜。另外，如果保护膜柔软，则存在保护膜将晶片表面的凹凸抵消的可能性。因此，保护膜80使用刚性高的保护膜。由此，晶片表面的凹凸变得易于转印到背面。另外，在本实施方式中，基板30的研磨使用了研磨机，但也可以使用CMP(Chemical Mechanical Polishing)而进行研磨。
图6示出在研磨工序的实施之后去除了保护膜80的状态。在本实施方式中，表面构造60具有凸部61。通过研磨工序将凸部61的形状转印到基板30的背面。因此，单元部10形成得比终端部20薄。
然后，如图7所示，实施背面工序。在背面工序中，向基板30的背面侧进行注入以及扩散，形成背面半导体层39。然后，在背面半导体层39的背面形成背面电极43。由此，形成本实施方式涉及的半导体装置100。
图8是对比例涉及的半导体装置的剖面图。对比例涉及的半导体装置110不具有金属电极42。因此，如果对基板30的背面进行研磨，则与单元部10相伴地，终端部也形成得薄。或者，半导体装置110的表面的凹凸被转印，与终端部20相比较，单元部10存在变厚的可能性。
通常，如果基板变薄，则半导体装置成为低电阻。另一方面，如果基板变薄，则强度下降。因此，对比例涉及的半导体装置110通过基板30的研磨而实现低电阻化，另一方面，强度下降。与此相对，想到仅将基板的中央部变薄，外周部残留得厚的构造。这种构造的半导体装置由于基板的中央部薄而成为低电阻，由于外周部厚而保持强度。
这里，作为仅将基板的中央部变薄的方法，想到通过照相制版处理而形成掩模，然后，实施干蚀刻或者喷砂。但是，就该方法而言，为了将基板的中央部变薄，需要追加照相制版处理以及干蚀刻或者喷砂的工序。因此，制造工序复杂化。
与此相对，在本实施方式中，表面构造60具有凸部61。在研磨工序中，凸部61的形状被转印到基板30的背面。其结果，单元部10形成得比终端部20薄。这里，基板30的研磨工序以往是以晶片的薄化、氧化膜的去除或者多晶硅的去除为目的而实施的工序。因此，在本实施方式中，不追加工序即可使单元部10与终端部20相比变薄。因此，可以通过简单的制造工序而得到能够低电阻化以及保持强度的半导体装置100。
另外，在本实施方式中，以覆盖单元部10的上部的整个区域的方式形成凸部61。因此，成为流过主电流的区域的单元部10的整个区域形成得薄。因此，能够提高通过将基板30变薄而实现的低电阻化的效果。
另外，在本实施方式中，终端部20设置得比单元部10厚。因此，在半导体装置100的外周部，设置基板30厚的区域。因此，能够保持半导体装置100的强度。另外，终端部20是设置用于使半导体装置100的耐压提高的构造的区域。通常，存在终端部越厚，耐压越提高的倾向。因此，在本实施方式中，通过使终端部20设置得比单元部10厚，从而终端部20能够保持比单元部10高的耐压。
另外，如果使用RIE(Reactive Ion Etching)等干蚀刻或者喷砂在基板的背面侧形成凹部，则有时在由于凹部而形成的台阶处形成角。此时，有时电场集中在台阶的角的部分。
与此相对，在本实施方式中，通过研磨工序将晶片表面的凸部61转印到背面，因此在漂移层31不形成角。因此，在背面半导体层39以及背面电极43也不形成角。因此，与使用干蚀刻或者喷砂的情况相比较，电场易于被缓和。因此，能够提高耐压。在本实施方式中，单元部10之下的背面电极43和终端部20之下的背面电极43形成凹形状。单元部10之下的背面电极43的下表面与终端部20之下的背面电极43的下表面平滑地连接。
另外，在本实施方式中，在铝电极41之上设置金属电极42。金属电极42形成得厚，以在表面构造60形成凸部61。通过设置厚的金属电极42，从而能够提高针对导线键合的强度。另外，能够使直接引线键合时的端子与金属电极42的接合的可靠性提高。
另外，就开关元件而言，在通断动作的瞬态期间，有时基板内部的电场增强。基板内部的电场随着基板越薄而变得越强。就这样的在开关元件形成了5μm左右厚度的铝电极的构造而言，有时由于电场增强而导致电流集中。由于电流的集中而导致温度上升。因此，有时开关元件的针对电流的耐性下降。即，有时开关元件的破坏耐量下降。这里，在本实施方式中，在铝电极41之上设置金属电极42。通过设置厚的金属电极42，从而能够使表面电极44的扩展电阻下降。如果表面电极44的扩展电阻下降，则电流的集中被抑制。因此，针对电流的耐性提高。其结果，能够提高半导体装置100的破坏耐量。
本实施方式涉及的半导体装置100是纵向型的沟槽IGBT。作为其变形例，半导体装置100只要是纵向型的功率器件即可。例如，半导体装置100也可以是IGBT、功率MOSFET、二极管。另外，在本实施方式中，以覆盖单元部10的上部的整个区域的方式形成凸部61。与此相对，凸部61也可以形成于单元部10的上部的一部分。在该情况下，单元部10的一部分形成得比终端部20薄。
图9是本发明的实施方式1的变形例涉及的半导体装置的剖面图。变形例涉及的半导体装置400具有金属电极442。其他的构造与半导体装置100相同。就半导体装置400而言，在绝缘膜50与金属电极442之间形成间隙451。
金属电极442在半导体装置400的上表面向上方凸出。因此，在对基板30的背面进行研磨时，有时向金属电极442施加强的应力。在本实施方式中，在绝缘膜50与金属电极442之间形成间隙451。由此，在研磨工序中抑制了施加至金属电极442的应力向绝缘膜50传递。因此，能够防止作为玻璃的绝缘膜50破裂。
图10是本发明的实施方式1的其他变形例涉及的半导体装置500的剖面图。变形例涉及的半导体装置500具有金属电极542。由金属电极542形成的凸部561的厚度A比基板30的厚度B薄。由此，在对基板30的背面进行研磨时，能够防止研磨部分贯穿基板30。另外，能够防止由于基板30变薄而引起的基板30的破裂。
基板30也可以由宽带隙半导体形成。通过使用宽带隙半导体，从而能够提高耐压以及针对电流的耐性。即，能够提高半导体装置100的破坏耐量。作为宽带隙半导体，能够使用碳化硅、氮化镓类材料以及金刚石。
上述变形能够适当地应用于以下的实施方式涉及的半导体装置以及其制造方法。此外，以下的实施方式涉及的半导体装置以及其制造方法与实施方式1的共通点多，因此以与实施方式1的不同点为中心进行说明。
实施方式2.
图11是本发明的实施方式2涉及的半导体装置的俯视图。本实施方式涉及的半导体装置200形成有IGBT 292和二极管291。二极管291与IGBT 292相邻而形成。IGBT 292和二极管291被终端部20包围。终端部20处的基板230的构造与实施方式1相同。另外，在IGBT292的端部形成有用于向IGBT 292的栅极234施加栅极电压的栅极焊盘213。
图12是发明的实施方式2涉及的半导体装置的剖面图。图12是通过将图11所示的半导体装置200以I-II直线进行切断而得到的剖面图。半导体装置200具有基板230、在基板230之上设置的表面构造260、在基板230的背面设置的背面电极243。基板230具有单元部210和包围单元部210的终端部20。
在单元部210设置IGBT区域212和二极管区域211，该二极管区域211是与IGBT区域212相邻设置的。IGBT区域212是单元部210的形成IGBT 292的区域。另外，二极管区域211是单元部210的形成二极管291的区域。
基板230具有N型的漂移层231、表面层238以及背面半导体层239。在IGBT区域212，在漂移层231的表面设置P-型的基极232、N+型的发射极233以及作为沟槽栅极的栅极234。在二极管区域211，在漂移层231的表面设置P-型的阳极252以及栅极234。这里，基极232是与阳极252相同的层。另外，二极管区域211也可以不具有栅极234。
在漂移层231的背面形成N型的缓冲层235。在缓冲层235的背面形成P型的集电极236。另外，在二极管区域211，集电极236的一部分置换为N型的阴极256。在本实施方式中，表面层238包含基极232、阳极252、发射极233、栅极234以及FLR构造37。另外，背面半导体层239包含缓冲层235、集电极236以及阴极256。
在栅极234之上设置绝缘层246。另外，在绝缘层246以及基板230之上设置铝电极241。在IGBT区域212的上部，在铝电极241之上设置金属电极242。金属电极242形成在IGBT区域212的上部的整个区域。铝电极241与金属电极242形成表面电极244。绝缘层246、表面电极244以及绝缘膜50构成表面构造260。金属电极242的上表面比绝缘膜50的上表面高。因此，表面构造260在IGBT区域212的上部具有向上方凸出的凸部261。
在基板230的背面以与集电极236以及阴极256接触的方式设置背面电极243。由此，在半导体装置200形成二极管291和作为沟槽IGBT的IGBT 292。因此，半导体装置200成为RC(Reverse Conducting)-IGBT。二极管291通过将P型的集电极236的一部分置换为N型的阴极256而形成。另外，在基板230的背面侧，在与金属电极242相对的位置形成凹部219。通过在基板230的背面侧设置凹部219，从而与二极管区域211相比较，IGBT区域212变薄。
然后，对本实施方式涉及的半导体装置200的制造方法进行说明。图13～图17是表示本发明的实施方式2涉及的半导体装置的制造方法的图。首先，实施表面工序。在表面工序中，如图13所示，在基板230形成漂移层231和表面层238。然后，实施表面构造工序。在表面构造工序中，首先，在栅极234之上形成绝缘层246。然后，在基板230以及绝缘层246之上形成铝电极241。然后，在终端部20的上部，在铝电极241之上形成绝缘膜50。
然后，如图14所示，在IGBT区域212的上部，在铝电极241之上形成金属电极242。以覆盖IGBT区域212的上部的整个区域的方式形成金属电极242。与实施方式1相同地，金属电极242以配置于上表面比绝缘膜50的上表面高的位置的方式而形成。由此，形成具有凸部261的表面构造260。
然后，如图15所示，在表面构造260之上粘贴保护膜280。然后，实施研磨工序，对基板230的背面进行研磨。在本实施方式中，在IGBT区域212的上部形成有凸部261。因此，通过对基板230的背面进行研磨，从而与凸部261相对的部分被研磨得深。因此，如图16所示，基板230的IGBT区域212形成得薄。
然后，如图17所示，实施背面工序。在背面工序中，在基板230的背面侧形成缓冲层235。然后，在缓冲层235的背面形成阴极256。然后，通过由照相制版处理实现的抗蚀层注入，形成集电极236。然后，在集电极236以及阴极256的背面形成背面电极243。由此，形成本实施方式涉及的半导体装置200。
就本实施方式涉及的半导体装置200而言，在IGBT区域212的上部形成凸部261。因此，通过研磨工序将基板230的IGBT区域212形成得比二极管区域211薄。因此，能够使流过主电流的IGBT区域212低电阻化。另外，终端部20以及二极管区域211比IGBT区域212厚。因此，能够保持强度以及耐压。
另外，就二极管而言，在从正向偏置状态起切换了偏置方向时，存在电流沿反方向流过的期间。沿反方向流过电流的期间即恢复时的浪涌电压通常随着基板越厚而变得越难以振荡。在本实施方式中，基板230的二极管区域211形成得比IGBT区域厚。因此，与实施方式1相比较能够期待恢复耐量的提高。
实施方式3.
图18是本发明的实施方式3涉及的半导体装置的俯视图。在本实施方式涉及的半导体装置300形成有IGBT 392和二极管391。二极管391与IGBT 392相邻而形成。IGBT 392和二极管391被终端部20包围。终端部20的构造与实施方式1相同。另外，在IGBT 392的端部形成有用于向IGBT 392的栅极234供给电力的栅极焊盘313。
图19是发明的实施方式3涉及的半导体装置的剖面图。图19是通过将图18示出的半导体装置300以I-II直线进行切断而得到的剖面图。半导体装置300具有基板330、在基板330之上设置的表面构造360、在基板330的背面设置的背面电极343。基板330具有单元部310和包围单元部310的终端部20。
在单元部310设置IGBT区域312和二极管区域311，该二极管区域311是与IGBT区域312相邻设置的。IGBT区域312是单元部310的形成IGBT 392的区域。另外，二极管区域311是单元部310的形成二极管391的区域。
在本实施方式中，基板330具有漂移层331、表面层238以及背面半导体层339。表面层238的构造与实施方式2相同。在IGBT区域312，在漂移层331的背面形成N型的缓冲层335。在缓冲层335的背面形成P型的集电极336。另外，在二极管区域311，在漂移层331的背面形成缓冲层335。缓冲层335在二极管区域311从集电极336露出。背面半导体层339包含缓冲层335以及集电极336。
本实施方式涉及的绝缘层246以及铝电极241的构造与实施方式2相同。在本实施方式中，在二极管区域311的上部，在铝电极241之上设置金属电极342。金属电极342形成在二极管区域311的上部的整个区域。铝电极241和金属电极342形成表面电极344。绝缘层246、表面电极344以及绝缘膜50构成表面构造360。金属电极342的上表面比绝缘膜50的上表面高。因此，表面构造360在二极管区域311的上部具有向上方凸出的凸部361。
在基板330的背面设置背面电极343。这里，缓冲层335在二极管区域311从集电极336露出。因此，在二极管区域311，缓冲层335与背面电极343接触。在本实施方式中，通过使N型的缓冲层335与背面电极343接触，从而形成有二极管391。由此，在半导体装置300形成二极管391和作为沟槽IGBT的IGBT 392。因此，半导体装置300与半导体装置200相同地成为RC-IGBT。
接下来，对本实施方式涉及的半导体装置300的制造方法进行说明。图20～图25是表示本发明的实施方式3涉及的半导体装置的制造方法的图。如图20所示，直至形成绝缘膜50的工序为止，半导体装置300的制造方法与实施方式2相同。
然后，如图21所示，以覆盖二极管区域311的上部的整个区域的方式在铝电极241之上形成金属电极342。与实施方式1相同地，金属电极342以配置于上表面比绝缘膜50的上表面高的位置的方式而形成。
然后，如图22所示，实施背面工序。在背面工序中，形成背面半导体层339。首先，在基板330的背面侧形成缓冲层335。然后，在缓冲层335的背面形成集电极336。
然后，如图23所示，在表面构造360之上粘贴保护膜380。然后，实施研磨工序。在本实施方式中，在背面工序之后实施研磨工序。因此，在研磨工序中，背面半导体层339被研磨。在本实施方式中，在二极管区域311的上部，表面电极344具有凸部361。因此，在背面半导体层339的背面，与凸部361相对的位置被研磨得深。因此，如图24所示，基板330的二极管区域311形成得薄。在研磨工序中，进行研磨以去除二极管区域311的集电极336，使得缓冲层335露出。
然后，如图25所示，在集电极336的背面形成背面电极343。背面电极343以在集电极336被去除、缓冲层335露出的部分与缓冲层335接触的方式设置。由此，形成本实施方式涉及的半导体装置300。
在实施方式2中，实施照相制版处理以及离子注入，通过将P型的集电极236的一部分置换为N型的阴极256，从而形成二极管291。与此相对，在本实施方式中，通过在研磨工序中将集电极336的一部分进行去除，从而形成二极管391。因此，在本实施方式中，不追加照相制版处理以及蚀刻的工序即可形成二极管391。因此，能够通过简单的工序而得到RC-IGBT。另外，由于单元部310的一部分变薄，因此能够得到低电阻化的效果。
在本实施方式中，通过研磨工序使缓冲层335露出。作为其变形例，也可以通过研磨工序使漂移层331露出。在该情况下，以N型的漂移层331与背面电极343接触的方式形成背面电极343。此外，各实施方式中说明的技术特征也可以适当地组合使用。
标号的说明
100、200、300、400、500半导体装置，10、210、310单元部，20终端部，30、230、330基板，60、260、360表面构造，61、261、361、561凸部，44、244、344表面电极，43、243、343背面电极，212、312 IGBT区域，211、311二极管区域，50绝缘膜，451间隙，80、280、380保护膜，38、238表面层，39、239、339背面半导体层，32、232基极，33、233发射极，34、234栅极，35、235、335缓冲层，36、236、336集电极，256阴极，252阳极。

Claims (13)

1.一种半导体装置，其特征在于，具备：
基板，其具有单元部、包围所述单元部的终端部；
表面构造，其设置于所述基板之上；以及
背面电极，其设置于所述基板的背面，
所述表面构造在所述单元部的上部具有相对于所述表面构造中的在所述终端部的上部设置的部分向上方凸出的凸部，
所述单元部的至少一部分比所述终端部薄，
所述单元部之下的所述背面电极相对于所述终端部之下的所述背面电极形成凹形状，
所述单元部之下的所述背面电极的下表面与所述终端部之下的所述背面电极的下表面平滑地连接，
所述表面构造具有在所述基板之上设置的表面电极，
所述凸部是所述表面电极的一部分，
在所述单元部设置IGBT区域和二极管区域，该二极管区域是与所述IGBT区域相邻设置的，
所述凸部设置于所述IGBT区域的上部，
所述IGBT区域比所述二极管区域薄。
2.根据权利要求1所述的半导体装置，其特征在于，
所述表面构造具有绝缘膜，该绝缘膜在所述终端部的上部设置于所述表面电极之上，
在所述绝缘膜与所述凸部之间设置间隙。
3.一种半导体装置，其特征在于，具备：
基板，其具有单元部、包围所述单元部的终端部；
表面构造，其设置于所述基板之上；以及
背面电极，其设置于所述基板的背面，
所述表面构造在所述单元部的上部具有相对于所述表面构造中的在所述终端部的上部设置的部分向上方凸出的凸部，
所述单元部的至少一部分比所述终端部薄，
所述单元部之下的所述背面电极相对于所述终端部之下的所述背面电极形成凹形状，
所述单元部之下的所述背面电极的下表面与所述终端部之下的所述背面电极的下表面平滑地连接，
所述表面构造具有在所述基板之上设置的表面电极，
所述凸部是所述表面电极的一部分，
在所述单元部设置IGBT区域和二极管区域，该二极管区域是与所述IGBT区域相邻设置的，
所述凸部设置于所述二极管区域的上部，
所述二极管区域比所述IGBT区域薄。
4.根据权利要求3所述的半导体装置，其特征在于，
所述基板是N型，
所述基板在所述IGBT区域的背面侧具有N型的缓冲层和P型的集电极，在所述二极管区域的背面侧具有所述缓冲层。
5.根据权利要求1至4中任一项所述的半导体装置，其特征在于，
所述凸部比所述基板薄。
6.根据权利要求1至4中任一项所述的半导体装置，其特征在于，
所述基板由宽带隙半导体形成。
7.根据权利要求6所述的半导体装置，其特征在于，
所述宽带隙半导体是碳化硅、氮化镓类材料或者金刚石。
8.一种半导体装置的制造方法，其特征在于，具备以下工序：
表面工序，在基板的表面侧形成表面层，该基板具有单元部、包围所述单元部的终端部；
表面构造工序，在实施所述表面工序之后，在所述单元部之上形成具有向上方凸出的凸部的表面构造；
粘贴保护膜以覆盖所述表面构造的工序；
研磨工序，在粘贴了所述保护膜的状态下，对所述基板的背面进行研磨；
背面工序，在所述基板的背面侧形成背面半导体层；以及
在实施所述研磨工序之后，在所述背面半导体层的背面形成背面电极的工序，
所述凸部是设置于所述基板之上的表面电极的一部分，
在所述表面构造工序中，具有在所述终端部的上部在所述表面电极之上设置绝缘膜的工序，
所述绝缘膜是在所述绝缘膜与所述凸部之间设置间隙而形成的。
9.根据权利要求8所述的半导体装置的制造方法，其特征在于，
在所述表面工序中，在所述单元部形成基极、发射极、与所述基极相邻的阳极，
在所述表面构造工序中，在所述基极以及所述发射极的上部形成所述凸部，
在所述背面工序中，在所述基板形成缓冲层，在所述缓冲层的背面形成集电极、阴极，
所述研磨工序是在所述背面工序之前实施的。
10.根据权利要求8所述的半导体装置的制造方法，其特征在于，
在所述表面工序中，在所述单元部形成基极、发射极、与所述基极相邻的阳极，
在所述表面构造工序中，在所述阳极的上部形成所述凸部，
在所述背面工序中，在所述基板形成缓冲层，在所述缓冲层的背面形成集电极，
所述研磨工序是在所述背面工序之后实施的。
11.根据权利要求8至10中任一项所述的半导体装置的制造方法，其特征在于，
所述凸部比所述基板形成得薄。
12.根据权利要求8至10中任一项所述的半导体装置的制造方法，其特征在于，
所述基板由宽带隙半导体形成。
13.根据权利要求12所述的半导体装置的制造方法，其特征在于，
所述宽带隙半导体是碳化硅、氮化镓类材料或者金刚石。
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