JP5404755B2 - プリント基板の製造方法 - Google Patents
プリント基板の製造方法 Download PDFInfo
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- JP5404755B2 JP5404755B2 JP2011273536A JP2011273536A JP5404755B2 JP 5404755 B2 JP5404755 B2 JP 5404755B2 JP 2011273536 A JP2011273536 A JP 2011273536A JP 2011273536 A JP2011273536 A JP 2011273536A JP 5404755 B2 JP5404755 B2 JP 5404755B2
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- 238000000034 method Methods 0.000 title claims description 38
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- 238000007747 plating Methods 0.000 claims description 27
- 238000007772 electroless plating Methods 0.000 claims description 26
- 238000009713 electroplating Methods 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 238000004140 cleaning Methods 0.000 claims description 13
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 12
- YJVFFLUZDVXJQI-UHFFFAOYSA-L palladium(ii) acetate Chemical compound [Pd+2].CC([O-])=O.CC([O-])=O YJVFFLUZDVXJQI-UHFFFAOYSA-L 0.000 claims description 12
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- 239000010410 layer Substances 0.000 description 117
- 229910052802 copper Inorganic materials 0.000 description 49
- 239000010949 copper Substances 0.000 description 49
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 47
- 239000010408 film Substances 0.000 description 42
- 238000004377 microelectronic Methods 0.000 description 34
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 31
- 239000000463 material Substances 0.000 description 25
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- 229910000679 solder Inorganic materials 0.000 description 2
- 229910019655 synthetic inorganic crystalline material Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- VZPPHXVFMVZRTE-UHFFFAOYSA-N [Kr]F Chemical compound [Kr]F VZPPHXVFMVZRTE-UHFFFAOYSA-N 0.000 description 1
- JNDMLEXHDPKVFC-UHFFFAOYSA-N aluminum;oxygen(2-);yttrium(3+) Chemical compound [O-2].[O-2].[O-2].[Al+3].[Y+3] JNDMLEXHDPKVFC-UHFFFAOYSA-N 0.000 description 1
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 1
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- ILFGODHCYAHKOR-UHFFFAOYSA-N dibromoxenon Chemical compound Br[Xe]Br ILFGODHCYAHKOR-UHFFFAOYSA-N 0.000 description 1
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- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
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- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 description 1
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- 229910019901 yttrium aluminum garnet Inorganic materials 0.000 description 1
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- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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Description
Claims (18)
- 基板上に第一の誘電体層をラミネートする工程と、
レーザ照射により前記第一の誘電体層に複数のビアを形成する工程と、
レーザ照射にさらされた領域が活性化し、活性化部分が無電解めっきのシード、または、電解めっきの導電材料として機能し、かつ、レーザ照射により活性化されない非活性化部分が洗浄により除去可能な第一のシードコートを、前記第一の誘電体層がラミネートされた前記基板の表面全体に形成する工程と、
前記第一のシードコートに対して、選択的にレーザを照射する工程と、
前記第一のシードコートを洗浄することで、前記第一のシードコートの前記非活性化部分を除去する工程と、
前記第一のシードコートの前記活性化部分に対して選択的に金属めっきする工程と、
を備え、
前記金属めっきする工程は、
前記活性化部分に選択的に無電解めっきを行う工程と、
前記無電解めっきされた前記第一のシードコートの前記活性化部分に対して選択的に電解めっきする工程とを含み
前記レーザを照射する工程は、
所定のタイバーパターンを用いたレーザ照射により、前記電解めっき用のレーザ活性タイバー領域を形成する工程を含み、
前記複数のビアが前記レーザを照射する工程と同じレーザデバイスにより形成される、プリント基板の製造方法。 - 前記レーザを照射する工程は、前記第一のシードコートに対して、配線を形成すべき領域に選択的にレーザを照射する工程を含み、
前記複数のビアに形成された前記第一のシードコートの領域は、前記配線を形成すべき領域の少なくとも一部である、
請求項1に記載のプリント基板の製造方法。 - 前記無電解めっきする工程は、前記第一のシードコートの前記活性化部分に第一導電層を形成する工程を含み、
前記電解めっきする工程は、前記第一導電層上に第二導電層を形成する工程を含む
請求項1または2に記載のプリント基板の製造方法。 - 前記第一のシードコートを形成する工程は、前記基板をシード溶液内に浸漬する工程を有する請求項1から3のいずれか一項に記載のプリント基板の製造方法。
- 前記第一のシードコートは酢酸パラジウムを含む、請求項1から4のいずれか一項に記載のプリント基板の製造方法。
- 前記第一のシードコートにおいて、レーザの照射により活性化された前記活性化部分は、酢酸がアブレーションされた活性化層を含む請求項5に記載のプリント基板の製造方法。
- 前記第一の誘電体層をラミネートする工程の前に、
前記基板が有する金属パネルをレーザによりパターニングする工程をさらに備える、
請求項1に記載のプリント基板の製造方法。 - 前記金属めっきする工程の後に、
前記基板上に第二の誘電体層を形成する工程と、
前記第二の誘電体層をレーザにより掘削し、前記金属めっきまで達する第二のビアを形成する工程と、
第二のシードコートを基板の表面全体に形成する工程と、
前記第二のビアに形成された前記第二のシードコートに対して、選択的にレーザを照射する工程と、
前記第二のシードコートを洗浄することで、前記第二のシードコートの非活性化部分を除去する工程と、
前記第二のシードコートの活性化部分に対して選択的に金属めっきする工程と、
をさらに備える請求項1に記載のプリント基板の製造方法。 - 金属パネルを含む基板上に第一の誘電体層をラミネートする工程と、
レーザ照射により前記第一の誘電体層に複数のビアを形成し、前記金属パネルの一部を露出させる工程と、
レーザ照射にさらされた領域が活性化し、活性化部分が電解めっきの導電材料として機能し、かつ、レーザ照射により活性化されない非活性化部分が洗浄により除去可能な第一のシードコートを、前記第一の誘電体層がラミネートされた前記基板の表面全体に形成する工程と、
前記第一のシードコートに対して、選択的にレーザを照射する工程と、
前記第一のシードコートを洗浄することで、前記第一のシードコートの前記非活性化部分を除去する工程と、
前記第一のシードコートの前記活性化部分に対して選択的に金属めっきする工程と、
を備え、
前記金属めっきする工程は、
前記第一のシードコートの前記活性化部分に対して、前記金属パネルを用いて選択的に電解めっきする工程を含み、
前記複数のビアが前記レーザを照射する工程と同じレーザデバイスにより形成される、プリント基板の製造方法。 - 前記第一のシードコートを形成する工程は、前記基板をシード溶液内に浸漬する工程を有する請求項9に記載のプリント基板の製造方法。
- 前記第一のシードコートは酢酸パラジウムを含む、請求項9または10に記載のプリント基板の製造方法。
- 前記第一のシードコートにおいて、レーザの照射により活性化された前記活性化部分は、酢酸がアブレーションされた活性化層を含む請求項11に記載のプリント基板の製造方法。
- 前記第一の誘電体層をラミネートする工程の前に、
前記基板が有する前記金属パネルをレーザによりパターニングする工程をさらに備える、
請求項9から12のいずれか1項に記載のプリント基板の製造方法。 - 前記金属めっきする工程の後に、
前記基板上に第二の誘電体層を形成する工程と、
前記第二の誘電体層をレーザにより掘削し、前記金属めっきまで達する第二のビアを形成する工程と、
第二のシードコートを基板の表面全体に形成する工程と、
前記第二のビアに形成された前記第二のシードコートに対して、選択的にレーザを照射する工程と、
前記第二のシードコートを洗浄することで、前記第二のシードコートの非活性化部分を除去する工程と、
前記第二のシードコートの活性化部分に対して選択的に金属めっきする工程と、
をさらに備える請求項9から13のいずれか1項に記載のプリント基板の製造方法。 - 前記第二のシードコートに対してレーザを照射する工程は、前記第二のシードコートに対して、配線を形成すべき領域に選択的にレーザを照射する工程を含み、
前記第二のビアに形成された前記第二のシードコートの領域は、前記配線を形成すべき領域の少なくとも一部である、
請求項14に記載のプリント基板の製造方法。 - 複数の金属突起を形成すべく、前記金属パネルをエッチングで除去する工程を更に含む、請求項9から15のいずれか1項に記載のプリント基板の製造方法。
- 前記第一のシードコートに対して選択的にレーザを照射する工程は、所定のタイバーパターンを用いたレーザ照射により、前記電解めっき用のレーザ活性タイバー領域を形成する工程を含む、請求項9から16のいずれか1項に記載のプリント基板の製造方法。
- 前記レーザを照射する工程が、
レーザを照射するパルス期間を設定する工程と、
供給すべきパルスの数を前記活性化部分の厚みの関数として決定する工程と
を含む、
請求項1から17のいずれか1項に記載のプリント基板の製造方法。
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Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8017022B2 (en) * | 2007-12-28 | 2011-09-13 | Intel Corporation | Selective electroless plating for electronic substrates |
TWI355220B (en) | 2008-07-14 | 2011-12-21 | Unimicron Technology Corp | Circuit board structure |
TWI394506B (zh) | 2008-10-13 | 2013-04-21 | Unimicron Technology Corp | 多層立體線路的結構及其製作方法 |
US9113547B2 (en) * | 2008-10-24 | 2015-08-18 | Intel Corporation | Same layer microelectronic circuit patterning using hybrid laser projection patterning (LPP) and semi-additive patterning(SAP) |
US8395051B2 (en) * | 2008-12-23 | 2013-03-12 | Intel Corporation | Doping of lead-free solder alloys and structures formed thereby |
US20110095410A1 (en) * | 2009-10-28 | 2011-04-28 | Fairchild Semiconductor Corporation | Wafer level semiconductor device connector |
TWI405317B (zh) * | 2010-03-04 | 2013-08-11 | Unimicron Technology Corp | 封裝基板及其製法 |
US8835217B2 (en) | 2010-12-22 | 2014-09-16 | Intel Corporation | Device packaging with substrates having embedded lines and metal defined pads |
TWI432116B (zh) * | 2011-03-23 | 2014-03-21 | Unimicron Technology Corp | 線路板的內埋式線路結構的製造方法 |
CN102806789A (zh) * | 2011-06-03 | 2012-12-05 | 上海安费诺永亿通讯电子有限公司 | 在绝缘体表面形成金属图案的方法 |
US20130037312A1 (en) * | 2011-08-10 | 2013-02-14 | Invensas Corporation | High density trace formation method by laser ablation |
US10098242B2 (en) | 2012-03-29 | 2018-10-09 | Taiwan Green Point Enterprises Co., Ltd. | Double-sided circuit board and method for preparing the same |
US10149390B2 (en) | 2012-08-27 | 2018-12-04 | Mycronic AB | Maskless writing of a workpiece using a plurality of exposures having different focal planes using multiple DMDs |
US20140174791A1 (en) * | 2012-12-26 | 2014-06-26 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof |
KR102356809B1 (ko) | 2014-12-26 | 2022-01-28 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR20160080526A (ko) | 2014-12-29 | 2016-07-08 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
IT201900005156A1 (it) * | 2019-04-05 | 2020-10-05 | St Microelectronics Srl | Procedimento per fabbricare leadframe per dispositivi a semiconduttore |
IT201900006740A1 (it) * | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di strutturazione di substrati |
IT201900024292A1 (it) | 2019-12-17 | 2021-06-17 | St Microelectronics Srl | Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente |
CN113853063A (zh) * | 2021-09-09 | 2021-12-28 | 深圳市海目星激光智能装备股份有限公司 | 介电材料去除方法、激光去除设备与电子器件 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0287843B1 (de) | 1987-04-24 | 1990-08-29 | Siemens Aktiengesellschaft | Verfahren zur Herstellung von Leiterplatten |
EP0399161B1 (en) | 1989-04-17 | 1995-01-11 | International Business Machines Corporation | Multi-level circuit card structure |
JPH03268392A (ja) * | 1990-03-16 | 1991-11-29 | Hitachi Chem Co Ltd | 多層配線板の製造法 |
US5462773A (en) * | 1992-12-28 | 1995-10-31 | Xerox Corporation | Synchronized process for catalysis of electroless metal plating on plastic |
JPH0758438A (ja) * | 1993-08-18 | 1995-03-03 | Shinko Electric Ind Co Ltd | 回路基板及びその製造方法 |
JP3493703B2 (ja) * | 1994-01-25 | 2004-02-03 | 松下電工株式会社 | 回路板の形成方法 |
JP3414024B2 (ja) * | 1995-01-30 | 2003-06-09 | 株式会社日立製作所 | 電子回路基板の配線修正方法 |
JPH09260808A (ja) * | 1996-03-19 | 1997-10-03 | Fujitsu Ltd | 光触媒反応による金属配線の形成方法及び基材 |
JP3111891B2 (ja) * | 1996-04-09 | 2000-11-27 | 株式会社村田製作所 | 無電解めっきのための活性化触媒液および無電解めっき方法 |
JP3633252B2 (ja) | 1997-01-10 | 2005-03-30 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP3297006B2 (ja) * | 1997-12-05 | 2002-07-02 | イビデン株式会社 | 多層プリント配線板 |
DE19723734C2 (de) * | 1997-06-06 | 2002-02-07 | Gerhard Naundorf | Leiterbahnstrukturen auf einem nichtleitenden Trägermaterial und Verfahren zu ihrer Herstellung |
KR100244580B1 (ko) | 1997-06-24 | 2000-02-15 | 윤종용 | 금속 범프를 갖는 회로 기판의 제조 방법 및 그를 이용한 반도체 칩 패키지의 제조 방법 |
US6222136B1 (en) | 1997-11-12 | 2001-04-24 | International Business Machines Corporation | Printed circuit board with continuous connective bumps |
US6562656B1 (en) | 2001-06-25 | 2003-05-13 | Thin Film Module, Inc. | Cavity down flip chip BGA |
JP2003031924A (ja) * | 2001-07-16 | 2003-01-31 | Toray Eng Co Ltd | 金属回路形成方法 |
AU2002211864A1 (en) | 2001-07-23 | 2003-02-17 | Gary A. Clayton | Grid interposer |
US20030180448A1 (en) | 2002-03-21 | 2003-09-25 | T.L.M. Advanced Laser Technology Ltd. | Method for fabrication of printed circuit boards |
JP3953900B2 (ja) * | 2002-06-27 | 2007-08-08 | 日本特殊陶業株式会社 | 積層樹脂配線基板及びその製造方法 |
TWI254995B (en) * | 2004-01-30 | 2006-05-11 | Phoenix Prec Technology Corp | Presolder structure formed on semiconductor package substrate and method for fabricating the same |
JP2005286158A (ja) * | 2004-03-30 | 2005-10-13 | Seiko Epson Corp | パターン形成方法、電子デバイス及びその製造方法並びに電子機器 |
JP3918828B2 (ja) * | 2004-05-20 | 2007-05-23 | 株式会社トッパンNecサーキットソリューションズ | 半導体装置 |
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