JP5354900B2 - 半導体基板の作製方法 - Google Patents

半導体基板の作製方法 Download PDF

Info

Publication number
JP5354900B2
JP5354900B2 JP2007339764A JP2007339764A JP5354900B2 JP 5354900 B2 JP5354900 B2 JP 5354900B2 JP 2007339764 A JP2007339764 A JP 2007339764A JP 2007339764 A JP2007339764 A JP 2007339764A JP 5354900 B2 JP5354900 B2 JP 5354900B2
Authority
JP
Japan
Prior art keywords
substrate
single crystal
crystal semiconductor
insulating film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007339764A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009164197A (ja
JP2009164197A5 (enExample
Inventor
舜平 山崎
健吾 秋元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2007339764A priority Critical patent/JP5354900B2/ja
Publication of JP2009164197A publication Critical patent/JP2009164197A/ja
Publication of JP2009164197A5 publication Critical patent/JP2009164197A5/ja
Application granted granted Critical
Publication of JP5354900B2 publication Critical patent/JP5354900B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
JP2007339764A 2007-12-28 2007-12-28 半導体基板の作製方法 Expired - Fee Related JP5354900B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007339764A JP5354900B2 (ja) 2007-12-28 2007-12-28 半導体基板の作製方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007339764A JP5354900B2 (ja) 2007-12-28 2007-12-28 半導体基板の作製方法

Publications (3)

Publication Number Publication Date
JP2009164197A JP2009164197A (ja) 2009-07-23
JP2009164197A5 JP2009164197A5 (enExample) 2011-02-03
JP5354900B2 true JP5354900B2 (ja) 2013-11-27

Family

ID=40966517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007339764A Expired - Fee Related JP5354900B2 (ja) 2007-12-28 2007-12-28 半導体基板の作製方法

Country Status (1)

Country Link
JP (1) JP5354900B2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5487741B2 (ja) * 2009-06-10 2014-05-07 株式会社ニコン 基板貼り合わせ装置
JP2011129777A (ja) * 2009-12-18 2011-06-30 Nikon Corp 基板重ね合わせ装置及びデバイスの製造方法
JP5445160B2 (ja) * 2010-01-18 2014-03-19 株式会社ニコン ウェハ処理装置、ウェハ処理方法およびデバイスの製造方法
JP5421825B2 (ja) 2010-03-09 2014-02-19 東京エレクトロン株式会社 接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP5447110B2 (ja) * 2010-04-06 2014-03-19 株式会社ニコン 基板貼り合わせ装置、積層半導体の製造方法、積層半導体及び基板貼り合わせ方法
FR2963848B1 (fr) * 2010-08-11 2012-08-31 Soitec Silicon On Insulator Procede de collage par adhesion moleculaire a basse pression
JP5538282B2 (ja) * 2010-08-23 2014-07-02 東京エレクトロン株式会社 接合装置、接合方法、プログラム及びコンピュータ記憶媒体
JP5129848B2 (ja) * 2010-10-18 2013-01-30 東京エレクトロン株式会社 接合装置及び接合方法
JP5314057B2 (ja) * 2011-01-07 2013-10-16 東京エレクトロン株式会社 剥離システム、剥離方法、プログラム及びコンピュータ記憶媒体
JP6037734B2 (ja) * 2012-09-07 2016-12-07 三菱重工工作機械株式会社 常温接合装置および常温接合方法
KR102162798B1 (ko) 2014-08-12 2020-10-08 삼성디스플레이 주식회사 증착장치 및 이를 이용한 유기발광 디스플레이 장치 제조방법
JP2023057752A (ja) * 2021-10-12 2023-04-24 ランテクニカルサービス株式会社 薄型基板の接合、剥離方法、薄型基板の製造方法、薄型基板、剥離装置、及び、接合装置
JP2023071504A (ja) * 2021-11-11 2023-05-23 東京エレクトロン株式会社 基板処理方法
JP7747416B2 (ja) * 2021-11-11 2025-10-01 東京エレクトロン株式会社 基板処理装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3250722B2 (ja) * 1995-12-12 2002-01-28 キヤノン株式会社 Soi基板の製造方法および製造装置
JPH09162088A (ja) * 1995-12-13 1997-06-20 Asahi Chem Ind Co Ltd 半導体基板とその製造方法
JPH10150176A (ja) * 1996-11-15 1998-06-02 Tadahiro Omi 半導体基体とその作製方法
JP2004266071A (ja) * 2003-02-28 2004-09-24 Canon Inc 貼り合わせシステム
JP2006028562A (ja) * 2004-07-14 2006-02-02 Shimadzu Corp 成膜装置および逆スパッタリング方法
FR2888663B1 (fr) * 2005-07-13 2008-04-18 Soitec Silicon On Insulator Procede de diminution de la rugosite d'une couche epaisse d'isolant

Also Published As

Publication number Publication date
JP2009164197A (ja) 2009-07-23

Similar Documents

Publication Publication Date Title
JP5354900B2 (ja) 半導体基板の作製方法
JP5548395B2 (ja) Soi基板の作製方法
JP5568260B2 (ja) Soi基板の作製方法
US8658508B2 (en) Method for manufacturing SOI substrate
JP5500833B2 (ja) Soi基板の作製方法
KR101596454B1 (ko) Soi 기판의 제작 방법
JP5478166B2 (ja) 半導体装置の作製方法
JP2010114431A (ja) Soi基板の作製方法
JP5666794B2 (ja) Soi基板の作製方法
JP5386193B2 (ja) Soi基板の作製方法
JP5618521B2 (ja) 半導体装置の作製方法
JP5201967B2 (ja) 半導体基板の作製方法および半導体装置の作製方法
US20100173472A1 (en) Method for manufacturing soi substrate and method for manufacturing semiconductor device
JP5580010B2 (ja) 半導体装置の作製方法
JP5430109B2 (ja) Soi基板の作製方法
US20090223628A1 (en) Manufacturing apparatus of composite substrate and manufacturing method of composite substrate with use of the manufacturing apparatus
JP5438945B2 (ja) ボンド基板の作製方法
JP2012186459A (ja) Soi基板、およびsoi基板の作製方法
JP2009246346A (ja) Soi基板の作製方法

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101209

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101209

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130129

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130131

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130325

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130611

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130730

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130820

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130827

R150 Certificate of patent or registration of utility model

Ref document number: 5354900

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees