JP5259197B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP5259197B2
JP5259197B2 JP2008002553A JP2008002553A JP5259197B2 JP 5259197 B2 JP5259197 B2 JP 5259197B2 JP 2008002553 A JP2008002553 A JP 2008002553A JP 2008002553 A JP2008002553 A JP 2008002553A JP 5259197 B2 JP5259197 B2 JP 5259197B2
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Japan
Prior art keywords
insulating layer
semiconductor substrate
via hole
layer
semiconductor device
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Expired - Fee Related
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JP2008002553A
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English (en)
Japanese (ja)
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JP2009164481A (ja
JP2009164481A5 (https=
Inventor
恵充 原田
優美 鈴木
義博 鍋
裕二 高岡
英之 和田
正暢 猿田
龍夫 末益
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Fujikura Ltd
Sony Corp
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Fujikura Ltd
Sony Corp
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Publication date
Application filed by Fujikura Ltd, Sony Corp filed Critical Fujikura Ltd
Priority to JP2008002553A priority Critical patent/JP5259197B2/ja
Priority to US12/348,988 priority patent/US8564101B2/en
Priority to KR1020090001448A priority patent/KR101573302B1/ko
Priority to TW098100752A priority patent/TWI492354B/zh
Priority to CN2009100007762A priority patent/CN101483162B/zh
Publication of JP2009164481A publication Critical patent/JP2009164481A/ja
Publication of JP2009164481A5 publication Critical patent/JP2009164481A5/ja
Priority to US13/027,614 priority patent/US8273657B2/en
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Publication of JP5259197B2 publication Critical patent/JP5259197B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/153—Containers comprising an insulating or insulated base having interconnections in passages through the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/804—Containers or encapsulations
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
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    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/216—Through-semiconductor vias, e.g. TSVs characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
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    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2008002553A 2008-01-09 2008-01-09 半導体装置及びその製造方法 Expired - Fee Related JP5259197B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2008002553A JP5259197B2 (ja) 2008-01-09 2008-01-09 半導体装置及びその製造方法
US12/348,988 US8564101B2 (en) 2008-01-09 2009-01-06 Semiconductor apparatus having a through-hole interconnection
KR1020090001448A KR101573302B1 (ko) 2008-01-09 2009-01-08 반도체 장치 및 그 제조 방법
CN2009100007762A CN101483162B (zh) 2008-01-09 2009-01-09 半导体装置及其制造方法
TW098100752A TWI492354B (zh) 2008-01-09 2009-01-09 半導體裝置及其製造方法
US13/027,614 US8273657B2 (en) 2008-01-09 2011-02-15 Method for manufacturing a semiconductor apparatus having a through-hole interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008002553A JP5259197B2 (ja) 2008-01-09 2008-01-09 半導体装置及びその製造方法

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JP2009164481A JP2009164481A (ja) 2009-07-23
JP2009164481A5 JP2009164481A5 (https=) 2011-02-10
JP5259197B2 true JP5259197B2 (ja) 2013-08-07

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US (2) US8564101B2 (https=)
JP (1) JP5259197B2 (https=)
KR (1) KR101573302B1 (https=)
CN (1) CN101483162B (https=)
TW (1) TWI492354B (https=)

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WO2017202288A1 (zh) * 2016-05-25 2017-11-30 苏州晶方半导体科技股份有限公司 半导体芯片的封装方法以及封装结构
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Publication number Publication date
TW200947659A (en) 2009-11-16
US20110136342A1 (en) 2011-06-09
US8564101B2 (en) 2013-10-22
CN101483162A (zh) 2009-07-15
TWI492354B (zh) 2015-07-11
KR20090076832A (ko) 2009-07-13
US20090200679A1 (en) 2009-08-13
CN101483162B (zh) 2010-09-08
JP2009164481A (ja) 2009-07-23
US8273657B2 (en) 2012-09-25
KR101573302B1 (ko) 2015-12-01

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