JP5258997B2 - 相互接続システム - Google Patents
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- JP5258997B2 JP5258997B2 JP2012129297A JP2012129297A JP5258997B2 JP 5258997 B2 JP5258997 B2 JP 5258997B2 JP 2012129297 A JP2012129297 A JP 2012129297A JP 2012129297 A JP2012129297 A JP 2012129297A JP 5258997 B2 JP5258997 B2 JP 5258997B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Description
(a)リンクの全てが第1の側の接続インタフェースから離れていくように第1から第3リンクが配置される、
(b)上端に最も近いラインを有するリンクが接続インタフェースの第1の側から離れていき、2つの残りのリンクが接続インタフェースの第2の側から離れていき、かつ接続インタフェースの第2の側から離れていくリンクが隣接して配置されるように、第1から第3リンクが配置される、
(c)下端に最も近いラインを有するリンクが接続インタフェースの第2の側から離れていき、2つの残りのリンクが接続インタフェースの第1の側から離れていき、かつ接続の第1の側から離れていくリンクが隣接して配置されるように、第1から第3リンクが配置される、
(d)上端に最も近いラインを有するリンク及び下端に最も近いラインを有するリンクが接続インタフェースの第1の側から離れていき、かつ最初の2つのリンク間の中間に配置されたラインを有するリンクが接続インタフェースの第2の側から離れていくように、第1から第3リンクが配置される、かつ
(e)、(f)、(g)、及び(h)、ここで(e)、(f)、(g)、及び(h)は、(a)、(b)、(c)、及び(d)であり、上端及び下端は、コネクタに直交する軸の周りに180度ずつ(a)、(b)、(c)、及び(d)のパターンを回転させることによって相互に交換される。
(a)リンクの全てが第1の側の接続インタフェースから離れていくように第1から第3リンクが配置される、
(b)上端に最も近いラインを有するリンクが接続インタフェースの第1の側から離れていき、2つの残りのリンクが接続インタフェースの第2の側から離れていき、かつ接続インタフェースの第2の側から離れていくリンクが隣接して配置されるように、第1から第3リンクが配置される、
(c)下端に最も近いラインを有するリンクが接続インタフェースの第2の側から離れていき、2つの残りのリンクが接続インタフェースの第1の側から離れていき、かつ接続の第1の側から離れていくリンクが隣接して配置されるように、第1から第3リンクが配置される、
(d)上端に最も近いラインを有するリンク及び下端に最も近いラインを有するリンクが接続インタフェースの第1の側から離れていき、かつ最初の2つのリンク間の中間に配置されたラインを有するリンクが接続インタフェースの第2の側から離れていくように、第1から第3リンクが配置される、かつ
(e)、(f)、(g)、及び(h)、ここで(e)、(f)、(g)、及び(h)は、(a)、(b)、(c)、及び(d)であり、上端及び下端は、コネクタに直交する軸の周りに180度ずつ(a)、(b)、(c)、及び(d)のパターンを回転させることによって相互に交換される。
L0は、別々のデータライン30及び制御ライン40を表し、ラインの各セットは、等しい幅の別々のノースバウンド及びサウスバウンド一方向ラインを有する、
L1は、等しくない幅の別々のノースバウンド及びサウスバウンド一方向データライン30a、b、M1からM0へのノースバウンド制御ライン40a及びMCからM1へのサウスバウンド制御ライン40b及びM1からMCへのノースバウンドデータライン30cを表す、
L2は、M1とM2間のノースバウンド及びサウスバウンド一方向データライン30d及び制御ライン40c並びにM1とM2間の別々の双方向制御ライン40d、また、M1からM3へのサウスバウンド一方向制御ライン40eを表す、かつ
L3は、M3からM2への結合ノースバウンド一方向データライン30e及び制御ライン40f、MC及びM3間の双方向サウスバウンド制御ライン40g及びM2からM3への一方向サウスバウンド及びノースバウンドデータライン30f、gを表している。
MCからM1(40b)、M1からM3(40e)の制御ラインのような制御ラインスキッピング隣接モジュールは、各ホップを通って送信される場合よりも少ない待ち時間で、M1からMC(30c)のようなデータラインと同様に制御信号を送信するのに使用することができる。「データ」又は「制御」というラベルを備えたラインは、単に「大抵は」データ又は制御ラインであるだけで、これらは、他のタイプの信号を運ぶのに使用することもできる。すなわち、制御信号をデータラインで運ぶことができ、データ信号を制御ラインで運ぶことができる。従って、データ及び制御ラインは、コンテキストに応じて論理的又は物理的とすることができる。
クロック信号は、シングルエンドクロックライン又は2つ又はそれよりも多くのモジュール間に接続した差異クロックを使用して、クロック生成回路から直接様々な構成要素及びモジュールに分配することができる。高速クロックはまた、データ又は制御信号と結合させることができる。
このような修復は、「ホットスワッピング」として当業技術で公知である。
R 受信接続
T 送信接続
Claims (7)
- マザーボード上のネットワークにノードを収容するための相互接続ネットワークであって、
第1端及び第2端を有し、第1、第2、及び第3リンク接続を形成する複数の信号ラインを含む接続インタフェースであって、前記のリンクは前記接続インタフェースの第1の側又は第2の側で前記接続インタフェースから離れるように広がり、前記第1の側及び前記第2の側は前記接続インタフェースの前記第1端及び前記第2端の間の軸に関して対向する方向である接続インタフェースと、
少なくとも前記接続インタフェースによって形成されたネットワークと、を含み、前記接続インタフェースの少なくとも2つの構成はトレースによって結合され、前記構成は、
(a)前記第1から第3リンクが、該リンクの全てが前記第2の側の前記接続インタフェースから離れていくように配置されるもの、
(b)前記第1から第3リンクが、前記第1端に最も近いリンクが前記接続インタフェースの前記第1の側から離れていき、2つの残りのリンクが該接続インタフェースの第2の側から離れていき、かつ該接続インタフェースの該第2の側から離れていく該リンクが隣接して配置されるように配置されるもの、
(c)前記第1から第3のリンクは、前記第1端に最も近いラインを有するリンク及び前記第2端に最も近いラインを有するリンクが前記接続インタフェースの前記第2の側から離れていき、2つの前記の最初のリンクの間に配置されたラインを有するリンクが前記接続インタフェースの前記第1の側から離れていくように配置されるもの、
(d)前記第1から第3リンクが、前記第2端に最も近いリンクが前記接続インタフェースの前記第2の側から離れていき、2つの残りのリンクが該接続インタフェースの前記第1の側から離れていき、かつ該接続の該第1の側から離れていく該リンクが隣接して配置されるように配置されるもの、及び
(e)、(f)、(g)、及び(h)であって、それは、それぞれ(d)、(c)、(b)、及び(a)であり、前記トレースの位置は、前記接続インタフェースの前記軸の周りに(a)、(b)、(c)、及び(d)のパターンを180度回転させることによって相互に交換されるもの、である
ことを特徴とする相互接続ネットワーク。 - 前記構成(a)から(h)の少なくとも3つを含むことを特徴とする請求項1に記載の相互接続ネットワーク。
- 前記リンクは、平坦なプリント配線アセンブリで配置されていることを特徴とする請求項1に記載の相互接続ネットワーク。
- 前記リンクは、基板の層で導電性金属要素として配置されていることを特徴とする請求項1に記載の相互接続ネットワーク。
- 少なくともメモリ回路が、前記基板上に配置されていることを特徴とする請求項1に記載の相互接続ネットワーク。
- 少なくとも3つの接続インタフェースが、互いに並行に配置されていることを特徴とする請求項1に記載の相互接続ネットワーク。
- マザーボードのためのネットワーク相互接続を配置する方法であって、
複数の接続インタフェースを、該接続インタフェースの第1端が互いに対向して置かれ、かつ該接続インタフェースの第2端が互いに対向して置かれ、それぞれの接続インタフェースは、第1、第2,及び第3リンク接続を形成する複数の信号ラインを含み、前記のリンクは前記接続インタフェースの第1の側又は第2の側で前記接続インタフェースから離れるように広がり、前記第1の側及び前記第2の側は前記接続インタフェースの前記第1端及び前記第2端の間の軸に関して対向する方向であるように配置する段階と、
前記複数の接続インタフェース間に接続のネットワークを形成する段階と、を含み、
前記接続インタフェースの少なくとも2つの構成はトレースによって結合され、前記構成は、
(a)第1から第3リンクが、該リンクの全てが第2の側の前記接続インタフェースから離れていくように配置されるもの、
(b)前記第1から第3リンクが、前記第1端に最も近いリンクが前記接続インタフェースの前記第1の側から離れていき、2つの残りのリンクが該接続インタフェースの第2の側から離れていき、かつ該接続インタフェースの該第2の側から離れていく該リンクが隣接して配置されるように配置されるもの、
(c)前記第1から第3のリンクは、前記第1端に最も近いラインを有するリンク及び前記第2端に最も近いラインを有するリンクが前記接続インタフェースの前記第1の側から離れていき、2つの前記の最初のリンクの間に配置されたラインを有するリンクが前記接続インタフェースの前記第2の側から離れていくように配置されるもの、
(d)前記第1から第3リンクが、前記第2端に最も近いリンクが前記接続インタフェースの前記第2の側から離れていき、2つの残りのリンクが該接続インタフェースの前記第1の側から離れていき、かつ該接続の該第1の側から離れていく該リンクが隣接して配置されるように配置されるもの、及び
(e)、(f)、(g)、及び(h)であって、それは、それぞれ(d)、(c)、(b)、及び(a)であり、前記トレースの位置は、前記接続インタフェースの前記軸の周りに(a)、(b)、(c)、及び(d)のパターンを180度回転させることによって相互に交換されるもの、である
ことを特徴とする方法。
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US67418905P | 2005-04-21 | 2005-04-21 | |
US60/674,189 | 2005-04-21 | ||
US69862605P | 2005-07-11 | 2005-07-11 | |
US60/698,626 | 2005-07-11 |
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JP2009124465A Division JP2009238234A (ja) | 2005-04-21 | 2009-05-22 | 相互接続システム |
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JP5258997B2 true JP5258997B2 (ja) | 2013-08-07 |
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JP2009124465A Pending JP2009238234A (ja) | 2005-04-21 | 2009-05-22 | 相互接続システム |
JP2012129297A Expired - Fee Related JP5258997B2 (ja) | 2005-04-21 | 2012-06-06 | 相互接続システム |
JP2013077997A Expired - Fee Related JP5654630B2 (ja) | 2005-04-21 | 2013-04-03 | 相互接続システム |
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US (2) | US10417159B2 (ja) |
EP (8) | EP2383660B1 (ja) |
JP (5) | JP2008537265A (ja) |
KR (4) | KR101331569B1 (ja) |
CN (4) | CN101727429B (ja) |
CA (1) | CA2597692A1 (ja) |
WO (1) | WO2006115896A2 (ja) |
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