JP5003033B2 - GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 - Google Patents
GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 Download PDFInfo
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- JP5003033B2 JP5003033B2 JP2006182118A JP2006182118A JP5003033B2 JP 5003033 B2 JP5003033 B2 JP 5003033B2 JP 2006182118 A JP2006182118 A JP 2006182118A JP 2006182118 A JP2006182118 A JP 2006182118A JP 5003033 B2 JP5003033 B2 JP 5003033B2
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- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/1033—Gallium nitride [GaN]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006182118A JP5003033B2 (ja) | 2006-06-30 | 2006-06-30 | GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 |
TW096120036A TW200818248A (en) | 2006-06-30 | 2007-06-05 | Substrate having thin film of GaN joined thereon and method of fabricating the same, and a GaN-based semiconductor device and method of fabricating the same |
EP07011175.2A EP1873817B1 (de) | 2006-06-30 | 2007-06-06 | Substrat mit darauf aufgetragener GaN-Dünnschicht und Herstellungsverfahren dafür |
US11/819,574 US7728348B2 (en) | 2006-06-30 | 2007-06-28 | Substrate having thin film of GaN joined thereon and method of fabricating the same, and a GaN-based semiconductor device and method of fabricating the same |
KR1020070064361A KR20080002644A (ko) | 2006-06-30 | 2007-06-28 | GaN 박막 접합 기판 및 그 제조 방법과, GaN계반도체 디바이스 및 그 제조 방법 |
CNB2007101273561A CN100573822C (zh) | 2006-06-30 | 2007-07-02 | 衬底及其制备方法以及半导体器件及其制备方法 |
HK08105764.5A HK1117270A1 (en) | 2006-06-30 | 2008-05-23 | Substrate and method of fabricating the same, and semiconductor device and method of fabricating the same |
US12/765,357 US8143140B2 (en) | 2006-06-30 | 2010-04-22 | Substrate having thin film of GaN joined thereon and method of fabricating the same, and a GaN-based semiconductor device and method of fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006182118A JP5003033B2 (ja) | 2006-06-30 | 2006-06-30 | GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008010766A JP2008010766A (ja) | 2008-01-17 |
JP5003033B2 true JP5003033B2 (ja) | 2012-08-15 |
Family
ID=38616553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006182118A Expired - Fee Related JP5003033B2 (ja) | 2006-06-30 | 2006-06-30 | GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US7728348B2 (de) |
EP (1) | EP1873817B1 (de) |
JP (1) | JP5003033B2 (de) |
KR (1) | KR20080002644A (de) |
CN (1) | CN100573822C (de) |
HK (1) | HK1117270A1 (de) |
TW (1) | TW200818248A (de) |
Families Citing this family (69)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7018909B2 (en) * | 2003-02-28 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Forming structures that include a relaxed or pseudo-relaxed layer on a substrate |
FR2926674B1 (fr) * | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable |
US8343824B2 (en) * | 2008-04-29 | 2013-01-01 | International Rectifier Corporation | Gallium nitride material processing and related device structures |
JP2009272380A (ja) * | 2008-05-01 | 2009-11-19 | Sumitomo Electric Ind Ltd | Iii族窒化物結晶およびその表面処理方法、iii族窒化物積層体およびその製造方法、ならびにiii族窒化物半導体デバイスおよびその製造方法 |
FR2931293B1 (fr) * | 2008-05-15 | 2010-09-03 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante |
EP2151861A1 (de) * | 2008-08-06 | 2010-02-10 | S.O.I. TEC Silicon | Passivierung von geätzten Halbleiterstrukturen |
EP2151856A1 (de) * | 2008-08-06 | 2010-02-10 | S.O.I. TEC Silicon | Relaxation von Spannungsschichten |
TWI457984B (zh) | 2008-08-06 | 2014-10-21 | Soitec Silicon On Insulator | 應變層的鬆弛方法 |
EP2151852B1 (de) * | 2008-08-06 | 2020-01-15 | Soitec | Relaxation und Übertragung von Spannungsschichten |
JP4631946B2 (ja) * | 2008-08-11 | 2011-02-16 | 住友電気工業株式会社 | Iii族窒化物半導体層貼り合わせ基板の製造方法 |
EP2159836B1 (de) * | 2008-08-25 | 2017-05-31 | Soitec | Versteifungsschichten zur Relaxation von verspannten Schichten |
JP5441094B2 (ja) * | 2008-10-01 | 2014-03-12 | 国立大学法人京都工芸繊維大学 | 半導体基板の製造方法および半導体基板 |
FR2936903B1 (fr) * | 2008-10-07 | 2011-01-14 | Soitec Silicon On Insulator | Relaxation d'une couche de materiau contraint avec application d'un raidisseur |
JP5608969B2 (ja) * | 2008-10-20 | 2014-10-22 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
US8637383B2 (en) | 2010-12-23 | 2014-01-28 | Soitec | Strain relaxation using metal materials and related structures |
JP5907730B2 (ja) | 2008-10-30 | 2016-04-26 | エス・オー・アイ・テック・シリコン・オン・インシュレーター・テクノロジーズ | 低減した格子ひずみを備えた半導体材料、同様に包含する半導体構造体、デバイス、および、加工された基板を製造する方法 |
JP2010165927A (ja) * | 2009-01-16 | 2010-07-29 | Sumitomo Electric Ind Ltd | 発光素子用基板 |
JP2010177464A (ja) * | 2009-01-29 | 2010-08-12 | Sumitomo Electric Ind Ltd | 電子デバイスの製造方法 |
JP5407385B2 (ja) * | 2009-02-06 | 2014-02-05 | 住友電気工業株式会社 | 複合基板、エピタキシャル基板、半導体デバイス及び複合基板の製造方法 |
JP5597933B2 (ja) * | 2009-05-01 | 2014-10-01 | 住友電気工業株式会社 | Iii族窒化物半導体層貼り合わせ基板およびその製造方法 |
JP5420968B2 (ja) * | 2009-05-07 | 2014-02-19 | 信越化学工業株式会社 | 貼り合わせウェーハの製造方法 |
JP2011077102A (ja) * | 2009-09-29 | 2011-04-14 | Toyoda Gosei Co Ltd | ウエハ、iii族窒化物系化合物半導体素子、及びそれらの製造方法 |
JP2011077351A (ja) * | 2009-09-30 | 2011-04-14 | Sumitomo Electric Ind Ltd | 発光素子 |
JP5381581B2 (ja) * | 2009-09-30 | 2014-01-08 | 住友電気工業株式会社 | 窒化ガリウム基板 |
JP5365454B2 (ja) * | 2009-09-30 | 2013-12-11 | 住友電気工業株式会社 | Iii族窒化物半導体基板、エピタキシャル基板及び半導体デバイス |
FR2953328B1 (fr) | 2009-12-01 | 2012-03-30 | S O I Tec Silicon On Insulator Tech | Heterostructure pour composants electroniques de puissance, composants optoelectroniques ou photovoltaiques |
JP2011146652A (ja) * | 2010-01-18 | 2011-07-28 | Sumitomo Electric Ind Ltd | 貼り合わせ基板、貼り合わせ基板の製造方法、及び発光素子 |
EP2562789A4 (de) | 2010-04-20 | 2015-03-04 | Sumitomo Electric Industries | Verfahren zur herstellung eines verbundsubstrats |
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JP2008010766A (ja) | 2008-01-17 |
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US20100210089A1 (en) | 2010-08-19 |
CN101101868A (zh) | 2008-01-09 |
TW200818248A (en) | 2008-04-16 |
US7728348B2 (en) | 2010-06-01 |
EP1873817A3 (de) | 2009-09-23 |
KR20080002644A (ko) | 2008-01-04 |
US8143140B2 (en) | 2012-03-27 |
EP1873817B1 (de) | 2013-08-14 |
US20080169483A1 (en) | 2008-07-17 |
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