JP5003033B2 - GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 - Google Patents

GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 Download PDF

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JP5003033B2
JP5003033B2 JP2006182118A JP2006182118A JP5003033B2 JP 5003033 B2 JP5003033 B2 JP 5003033B2 JP 2006182118 A JP2006182118 A JP 2006182118A JP 2006182118 A JP2006182118 A JP 2006182118A JP 5003033 B2 JP5003033 B2 JP 5003033B2
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gan
substrate
thin film
bulk crystal
bonded
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JP2008010766A (ja
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仁 笠井
昭広 八郷
祥紀 三浦
勝史 秋田
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority to JP2006182118A priority Critical patent/JP5003033B2/ja
Priority to TW096120036A priority patent/TW200818248A/zh
Priority to EP07011175.2A priority patent/EP1873817B1/de
Priority to KR1020070064361A priority patent/KR20080002644A/ko
Priority to US11/819,574 priority patent/US7728348B2/en
Priority to CNB2007101273561A priority patent/CN100573822C/zh
Publication of JP2008010766A publication Critical patent/JP2008010766A/ja
Priority to HK08105764.5A priority patent/HK1117270A1/xx
Priority to US12/765,357 priority patent/US8143140B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/1033Gallium nitride [GaN]
    • HELECTRICITY
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    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
JP2006182118A 2006-06-30 2006-06-30 GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法 Expired - Fee Related JP5003033B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2006182118A JP5003033B2 (ja) 2006-06-30 2006-06-30 GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法
TW096120036A TW200818248A (en) 2006-06-30 2007-06-05 Substrate having thin film of GaN joined thereon and method of fabricating the same, and a GaN-based semiconductor device and method of fabricating the same
EP07011175.2A EP1873817B1 (de) 2006-06-30 2007-06-06 Substrat mit darauf aufgetragener GaN-Dünnschicht und Herstellungsverfahren dafür
US11/819,574 US7728348B2 (en) 2006-06-30 2007-06-28 Substrate having thin film of GaN joined thereon and method of fabricating the same, and a GaN-based semiconductor device and method of fabricating the same
KR1020070064361A KR20080002644A (ko) 2006-06-30 2007-06-28 GaN 박막 접합 기판 및 그 제조 방법과, GaN계반도체 디바이스 및 그 제조 방법
CNB2007101273561A CN100573822C (zh) 2006-06-30 2007-07-02 衬底及其制备方法以及半导体器件及其制备方法
HK08105764.5A HK1117270A1 (en) 2006-06-30 2008-05-23 Substrate and method of fabricating the same, and semiconductor device and method of fabricating the same
US12/765,357 US8143140B2 (en) 2006-06-30 2010-04-22 Substrate having thin film of GaN joined thereon and method of fabricating the same, and a GaN-based semiconductor device and method of fabricating the same

Applications Claiming Priority (1)

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JP2006182118A JP5003033B2 (ja) 2006-06-30 2006-06-30 GaN薄膜貼り合わせ基板およびその製造方法、ならびにGaN系半導体デバイスおよびその製造方法

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JP2008010766A JP2008010766A (ja) 2008-01-17
JP5003033B2 true JP5003033B2 (ja) 2012-08-15

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US (2) US7728348B2 (de)
EP (1) EP1873817B1 (de)
JP (1) JP5003033B2 (de)
KR (1) KR20080002644A (de)
CN (1) CN100573822C (de)
HK (1) HK1117270A1 (de)
TW (1) TW200818248A (de)

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US20100210089A1 (en) 2010-08-19
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