JP4993739B2 - 配線基板、その製造方法及び電子部品装置 - Google Patents

配線基板、その製造方法及び電子部品装置 Download PDF

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Publication number
JP4993739B2
JP4993739B2 JP2007315925A JP2007315925A JP4993739B2 JP 4993739 B2 JP4993739 B2 JP 4993739B2 JP 2007315925 A JP2007315925 A JP 2007315925A JP 2007315925 A JP2007315925 A JP 2007315925A JP 4993739 B2 JP4993739 B2 JP 4993739B2
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JP
Japan
Prior art keywords
wiring
reinforcing
layer
wiring board
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007315925A
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English (en)
Japanese (ja)
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JP2009141121A (ja
JP2009141121A5 (https=
Inventor
浩 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007315925A priority Critical patent/JP4993739B2/ja
Priority to US12/211,458 priority patent/US8138424B2/en
Publication of JP2009141121A publication Critical patent/JP2009141121A/ja
Publication of JP2009141121A5 publication Critical patent/JP2009141121A5/ja
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Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
JP2007315925A 2007-12-06 2007-12-06 配線基板、その製造方法及び電子部品装置 Expired - Fee Related JP4993739B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007315925A JP4993739B2 (ja) 2007-12-06 2007-12-06 配線基板、その製造方法及び電子部品装置
US12/211,458 US8138424B2 (en) 2007-12-06 2008-09-16 Wiring substrate including a reinforcing structural body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007315925A JP4993739B2 (ja) 2007-12-06 2007-12-06 配線基板、その製造方法及び電子部品装置

Publications (3)

Publication Number Publication Date
JP2009141121A JP2009141121A (ja) 2009-06-25
JP2009141121A5 JP2009141121A5 (https=) 2010-10-28
JP4993739B2 true JP4993739B2 (ja) 2012-08-08

Family

ID=40720442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007315925A Expired - Fee Related JP4993739B2 (ja) 2007-12-06 2007-12-06 配線基板、その製造方法及び電子部品装置

Country Status (2)

Country Link
US (1) US8138424B2 (https=)
JP (1) JP4993739B2 (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100704919B1 (ko) * 2005-10-14 2007-04-09 삼성전기주식회사 코어층이 없는 기판 및 그 제조 방법
US20100073894A1 (en) * 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
TWI393233B (zh) * 2009-08-18 2013-04-11 欣興電子股份有限公司 無核心層封裝基板及其製法
JP5623308B2 (ja) 2010-02-26 2014-11-12 日本特殊陶業株式会社 多層配線基板及びその製造方法
JP5638269B2 (ja) 2010-03-26 2014-12-10 日本特殊陶業株式会社 多層配線基板
JP5566771B2 (ja) 2010-05-18 2014-08-06 日本特殊陶業株式会社 多層配線基板
CN102376675B (zh) * 2010-08-04 2015-11-25 欣兴电子股份有限公司 嵌埋有半导体元件的封装结构及其制法
JP5732238B2 (ja) * 2010-11-29 2015-06-10 シャープ株式会社 固体撮像装置および電子情報機器
US8595927B2 (en) * 2011-03-17 2013-12-03 Ibiden Co., Ltd. Method for manufacturing multilayer printed wiring board
US8841209B2 (en) * 2011-08-18 2014-09-23 International Business Machines Corporation Method for forming coreless flip chip ball grid array (FCBGA) substrates and such substrates formed by the method
WO2013147706A1 (en) * 2012-03-26 2013-10-03 Advanpack Solutions Pte Ltd Multi-layer substrate for semiconductor packaging
US9615447B2 (en) * 2012-07-23 2017-04-04 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Multilayer electronic support structure with integral constructional elements
KR101451502B1 (ko) * 2013-03-05 2014-10-15 삼성전기주식회사 인쇄회로기판
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US9704735B2 (en) 2014-08-19 2017-07-11 Intel Corporation Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication
JP6428038B2 (ja) * 2014-08-19 2018-11-28 株式会社デンソー 回路基板
TWI595810B (zh) * 2015-05-22 2017-08-11 欣興電子股份有限公司 封裝結構及其製作方法
CN106298707B (zh) * 2015-06-05 2019-05-21 欣兴电子股份有限公司 封装结构及其制作方法
JP6505521B2 (ja) * 2015-06-26 2019-04-24 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
WO2017111125A1 (ja) * 2015-12-25 2017-06-29 太陽誘電株式会社 プリント配線板、及びカメラモジュール
TWI641087B (zh) * 2015-12-28 2018-11-11 Siliconware Precision Industries Co., Ltd. 電子封裝件及封裝用之基板
KR102456322B1 (ko) 2017-11-08 2022-10-19 삼성전기주식회사 기판 스트립 및 이를 포함하는 전자소자 패키지
CN213124101U (zh) * 2017-11-30 2021-05-04 株式会社村田制作所 多层基板以及多层基板的安装构造
US11638351B2 (en) 2018-06-14 2023-04-25 Fujikura Ltd. Component-embedded substrate
KR20240151497A (ko) * 2023-04-11 2024-10-18 엘지이노텍 주식회사 반도체 패키지

Family Cites Families (9)

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JP3921756B2 (ja) * 1997-10-06 2007-05-30 株式会社デンソー プリント基板およびその製造方法
JP2001015638A (ja) * 1999-06-30 2001-01-19 Mitsumi Electric Co Ltd Ｉｃパッケージの基板
JP2004288661A (ja) * 2003-01-29 2004-10-14 Kyocera Corp 配線基板
JP2006270082A (ja) * 2005-02-25 2006-10-05 Kyocera Corp 配線基板及びそれを用いた電子装置
CN100553413C (zh) 2005-05-12 2009-10-21 株式会社村田制作所 多层陶瓷基板
JP4452222B2 (ja) * 2005-09-07 2010-04-21 新光電気工業株式会社 多層配線基板及びその製造方法
TWI290349B (en) * 2005-12-30 2007-11-21 Advanced Semiconductor Eng Thermally enhanced coreless thin substrate with an embedded chip and method for manufacturing the same
JP2009135162A (ja) * 2007-11-29 2009-06-18 Shinko Electric Ind Co Ltd 配線基板及び電子部品装置
KR101067199B1 (ko) * 2009-07-07 2011-09-22 삼성전기주식회사 인쇄회로기판 및 그 제조방법

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Publication number Publication date
JP2009141121A (ja) 2009-06-25
US8138424B2 (en) 2012-03-20
US20090145635A1 (en) 2009-06-11

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