JP4991925B2 - パッケージ基板及びその製造方法 - Google Patents
パッケージ基板及びその製造方法 Download PDFInfo
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- JP4991925B2 JP4991925B2 JP2010248935A JP2010248935A JP4991925B2 JP 4991925 B2 JP4991925 B2 JP 4991925B2 JP 2010248935 A JP2010248935 A JP 2010248935A JP 2010248935 A JP2010248935 A JP 2010248935A JP 4991925 B2 JP4991925 B2 JP 4991925B2
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- 239000000758 substrate Substances 0.000 title claims description 67
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 39
- 239000010949 copper Substances 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 38
- 230000002265 prevention Effects 0.000 claims description 38
- 229910000679 solder Inorganic materials 0.000 claims description 35
- 238000007747 plating Methods 0.000 claims description 30
- 229910052802 copper Inorganic materials 0.000 claims description 28
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 21
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 13
- 238000009713 electroplating Methods 0.000 claims description 11
- 229910001152 Bi alloy Inorganic materials 0.000 claims description 8
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 8
- 239000002245 particle Substances 0.000 claims description 5
- 230000008569 process Effects 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 239000000956 alloy Substances 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
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- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
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- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Electroplating Methods And Accessories (AREA)
Description
10:基板
101:導電性パッド
102:絶縁層
105:剥離防止層
106:柱形端子
107:はんだバンプ
Claims (19)
- 少なくとも一つの導電性パッドを具備した基板と、
前記基板上に提供され、前記導電性パッドを露出させる開口部を有する絶縁層と、
前記開口部内の前記導電性パッド上に形成され、前記絶縁層の側壁に沿って前記絶縁層の上部面より高く形成される剥離防止層と、
前記剥離防止層上に形成される柱形端子と、
前記柱形端子上に形成されるはんだバンプと
を含むことを特徴とするパッケージ基板。 - 前記剥離防止層は前記開口部の形状に対応してコップ状に形成されることを特徴とする請求項1に記載のパッケージ基板。
- 前記剥離防止層は銅からなることを特徴とする請求項1または2に記載のパッケージ基板。
- 前記剥離防止層は前記剥離防止層の最下部にメッキシード層を含むことを特徴とする請求項1から3の何れか1項に記載のパッケージ基板。
- 前記剥離防止層及び前記柱形端子は電解メッキ法で形成されることを特徴とする請求項1から4の何れか1項に記載のパッケージ基板。
- 前記柱形端子は錫(tin)及び銅(copper)の合金からなることを特徴とする請求項1から5の何れか1項に記載のパッケージ基板。
- 前記銅(copper)の含量は0.2wt%〜4wt%であることを特徴とする請求項6に記載のパッケージ基板。
- 前記はんだバンプは錫(tin)及びビズマス(bismuth)の合金からなることを特徴とする請求項1から7の何れか1項に記載のパッケージ基板。
- 少なくとも一つの導電性パッドを具備した基板を用意する段階と、
前記基板上に前記導電性パッドを露出させるように開口部を有する絶縁層を形成する段階と、
前記開口部内の前記導電性パッド上に、前記絶縁層の側壁に沿って前記絶縁層の上部面より高く剥離防止層を形成する段階と、
前記剥離防止層上に柱形端子を形成する段階と、
前記柱形端子上にはんだバンプを形成する段階と
を含むことを特徴とするパッケージ基板の製造方法。 - 前記剥離防止層を形成する段階の前に、
前記絶縁層上にメッキシード層を形成する段階と、
前記メッキシード層上に前記剥離防止層形成のためのドライフィルムパターンを形成する段階と、をさらに含むことを特徴とする請求項9に記載のパッケージ基板の製造方法。 - 前記ドライフィルムパターンを形成する段階は、
前記メッキシード層上にドライフィルムレジストを形成する段階と、
前記ドライフィルムレジストを露光及び現像して前記ドライフィルムパターンを形成する段階と、を含むことを特徴とする請求項10に記載のパッケージ基板の製造方法。 - 前記剥離防止層は前記開口部の形状に対応してコップ状に形成されることを特徴とする請求項9から11の何れか1項に記載のパッケージ基板の製造方法。
- 前記剥離防止層は銅で形成されることを特徴とする請求項9から12の何れか1項に記載のパッケージ基板の製造方法。
- 前記剥離防止層及び前記柱形端子は電解メッキ法で形成されることを特徴とする請求項9から13の何れか1項に記載のパッケージ基板の製造方法。
- 前記柱形端子は、前記柱形端子を成す粒子の大きさが小さく形成されるように、0.5ASD(A/dm2)〜3ASD(A/dm2)で電解メッキされることを特徴とする請求項14に記載のパッケージ基板の製造方法。
- 前記柱形端子は錫(tin)及び銅(copper)の合金で形成されることを特徴とする請求項9から15の何れか1項に記載のパッケージ基板の製造方法。
- 前記柱形端子は、前記銅(copper)の含量が0.2wt%〜4wt%になるように形成されることを特徴とする請求項16に記載のパッケージ基板の製造方法。
- 前記はんだバンプは錫(tin)及びビズマス(bismuth)の合金で形成されることを特徴とする請求項9から17の何れか1項に記載のパッケージ基板の製造方法。
- 前記はんだバンプを形成する段階の後に、リフロー段階をさらに含むことを特徴とする請求項9から18の何れか1項に記載のパッケージ基板の製造方法。
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KR1020090121098A KR101187977B1 (ko) | 2009-12-08 | 2009-12-08 | 패키지 기판 및 그의 제조방법 |
KR10-2009-0121098 | 2009-12-08 |
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JP4991925B2 true JP4991925B2 (ja) | 2012-08-08 |
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US (2) | US8456003B2 (ja) |
JP (1) | JP4991925B2 (ja) |
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JP2011124559A (ja) | 2011-06-23 |
US20110186991A1 (en) | 2011-08-04 |
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US20130237049A1 (en) | 2013-09-12 |
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