JP4927080B2 - 厚い絶縁層の粗さを減少させるための方法 - Google Patents

厚い絶縁層の粗さを減少させるための方法 Download PDF

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Publication number
JP4927080B2
JP4927080B2 JP2008520879A JP2008520879A JP4927080B2 JP 4927080 B2 JP4927080 B2 JP 4927080B2 JP 2008520879 A JP2008520879 A JP 2008520879A JP 2008520879 A JP2008520879 A JP 2008520879A JP 4927080 B2 JP4927080 B2 JP 4927080B2
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Japan
Prior art keywords
insulating layer
plasma
substrate
layer
roughness
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Expired - Lifetime
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JP2008520879A
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Japanese (ja)
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JP2009501440A (ja
JP2009501440A5 (cg-RX-API-DMAC10.html
Inventor
ニコラ、ダバル
セバスチアン、ケルディレ
セシル、オルネット
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Soitec SA
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Soitec SA
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Magnetic Heads (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
JP2008520879A 2005-07-13 2006-07-12 厚い絶縁層の粗さを減少させるための方法 Expired - Lifetime JP4927080B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0507573A FR2888663B1 (fr) 2005-07-13 2005-07-13 Procede de diminution de la rugosite d'une couche epaisse d'isolant
FR05/07573 2005-07-13
PCT/EP2006/064169 WO2007006803A1 (fr) 2005-07-13 2006-07-12 Procede de diminution de la rugosite d'une couche epaisse d'isolant

Publications (3)

Publication Number Publication Date
JP2009501440A JP2009501440A (ja) 2009-01-15
JP2009501440A5 JP2009501440A5 (cg-RX-API-DMAC10.html) 2009-02-26
JP4927080B2 true JP4927080B2 (ja) 2012-05-09

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JP2008520879A Expired - Lifetime JP4927080B2 (ja) 2005-07-13 2006-07-12 厚い絶縁層の粗さを減少させるための方法

Country Status (9)

Country Link
US (2) US7446019B2 (cg-RX-API-DMAC10.html)
EP (1) EP1902463B1 (cg-RX-API-DMAC10.html)
JP (1) JP4927080B2 (cg-RX-API-DMAC10.html)
KR (1) KR100958467B1 (cg-RX-API-DMAC10.html)
CN (1) CN100576462C (cg-RX-API-DMAC10.html)
AT (1) ATE524828T1 (cg-RX-API-DMAC10.html)
FR (1) FR2888663B1 (cg-RX-API-DMAC10.html)
SG (1) SG151287A1 (cg-RX-API-DMAC10.html)
WO (1) WO2007006803A1 (cg-RX-API-DMAC10.html)

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FR2911598B1 (fr) * 2007-01-22 2009-04-17 Soitec Silicon On Insulator Procede de rugosification de surface.
FR2911597B1 (fr) * 2007-01-22 2009-05-01 Soitec Silicon On Insulator Procede de formation et de controle d'interfaces rugueuses.
FR2912839B1 (fr) * 2007-02-16 2009-05-15 Soitec Silicon On Insulator Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud
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KR101440930B1 (ko) * 2007-04-20 2014-09-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판의 제작방법
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FR2931585B1 (fr) * 2008-05-26 2010-09-03 Commissariat Energie Atomique Traitement de surface par plasma d'azote dans un procede de collage direct
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US20100022070A1 (en) * 2008-07-22 2010-01-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
SG160295A1 (en) * 2008-09-29 2010-04-29 Semiconductor Energy Lab Method for manufacturing semiconductor device
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5496598B2 (ja) * 2008-10-31 2014-05-21 信越化学工業株式会社 シリコン薄膜転写絶縁性ウェーハの製造方法
FR2942911B1 (fr) * 2009-03-09 2011-05-13 Soitec Silicon On Insulator Procede de realisation d'une heterostructure avec adaptation locale de coefficient de dilatation thermique
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JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP2012156495A (ja) 2011-01-07 2012-08-16 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
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KR102148336B1 (ko) * 2013-11-26 2020-08-27 삼성전자주식회사 표면 처리 방법, 반도체 제조 방법 및 이에 의해 제조된 반도체 장치
WO2015147952A2 (en) * 2014-01-29 2015-10-01 Palvannanathan Ganesan Floating nuclear power reactor with a self-cooling containment structure and an emergency heat exchange system
CN107004639B (zh) * 2014-07-08 2021-02-05 麻省理工学院 衬底制造方法
FR3036200B1 (fr) * 2015-05-13 2017-05-05 Soitec Silicon On Insulator Methode de calibration pour equipements de traitement thermique
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JP7487659B2 (ja) * 2020-12-25 2024-05-21 株式会社Sumco Ｓｏｉウェーハの製造方法
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Also Published As

Publication number Publication date
US7446019B2 (en) 2008-11-04
KR100958467B1 (ko) 2010-05-17
JP2009501440A (ja) 2009-01-15
FR2888663A1 (fr) 2007-01-19
CN101243545A (zh) 2008-08-13
SG151287A1 (en) 2009-04-30
KR20080031747A (ko) 2008-04-10
CN100576462C (zh) 2009-12-30
WO2007006803A1 (fr) 2007-01-18
US20070020947A1 (en) 2007-01-25
FR2888663B1 (fr) 2008-04-18
EP1902463A1 (fr) 2008-03-26
ATE524828T1 (de) 2011-09-15
US8183128B2 (en) 2012-05-22
US20090023267A1 (en) 2009-01-22
EP1902463B1 (fr) 2011-09-14

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