SG151287A1 - Method for reducing roughness of a thick insulating layer - Google Patents

Method for reducing roughness of a thick insulating layer

Info

Publication number
SG151287A1
SG151287A1 SG200901884-7A SG2009018847A SG151287A1 SG 151287 A1 SG151287 A1 SG 151287A1 SG 2009018847 A SG2009018847 A SG 2009018847A SG 151287 A1 SG151287 A1 SG 151287A1
Authority
SG
Singapore
Prior art keywords
insulating layer
less
roughness
whereof
layer
Prior art date
Application number
SG200901884-7A
Other languages
English (en)
Inventor
Nicolas Daval
Sebastien Kerdiles
Cecile Aulnette
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG151287A1 publication Critical patent/SG151287A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Magnetic Heads (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
SG200901884-7A 2005-07-13 2006-07-12 Method for reducing roughness of a thick insulating layer SG151287A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0507573A FR2888663B1 (fr) 2005-07-13 2005-07-13 Procede de diminution de la rugosite d'une couche epaisse d'isolant

Publications (1)

Publication Number Publication Date
SG151287A1 true SG151287A1 (en) 2009-04-30

Family

ID=36090950

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200901884-7A SG151287A1 (en) 2005-07-13 2006-07-12 Method for reducing roughness of a thick insulating layer

Country Status (9)

Country Link
US (2) US7446019B2 (cg-RX-API-DMAC10.html)
EP (1) EP1902463B1 (cg-RX-API-DMAC10.html)
JP (1) JP4927080B2 (cg-RX-API-DMAC10.html)
KR (1) KR100958467B1 (cg-RX-API-DMAC10.html)
CN (1) CN100576462C (cg-RX-API-DMAC10.html)
AT (1) ATE524828T1 (cg-RX-API-DMAC10.html)
FR (1) FR2888663B1 (cg-RX-API-DMAC10.html)
SG (1) SG151287A1 (cg-RX-API-DMAC10.html)
WO (1) WO2007006803A1 (cg-RX-API-DMAC10.html)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115530B2 (en) * 2003-12-03 2006-10-03 Texas Instruments Incorporated Top surface roughness reduction of high-k dielectric materials using plasma based processes
EP1789999B1 (en) * 2004-09-16 2017-06-07 Soitec Method of manufacturing a silicon dioxide layer
FR2911598B1 (fr) * 2007-01-22 2009-04-17 Soitec Silicon On Insulator Procede de rugosification de surface.
FR2911597B1 (fr) * 2007-01-22 2009-05-01 Soitec Silicon On Insulator Procede de formation et de controle d'interfaces rugueuses.
FR2912839B1 (fr) * 2007-02-16 2009-05-15 Soitec Silicon On Insulator Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud
WO2008123116A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
WO2008123117A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
CN101657882B (zh) * 2007-04-13 2012-05-30 株式会社半导体能源研究所 显示器件、用于制造显示器件的方法、以及soi衬底
KR101440930B1 (ko) * 2007-04-20 2014-09-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판의 제작방법
EP1993128A3 (en) * 2007-05-17 2010-03-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
US8513678B2 (en) 2007-05-18 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device
US7763502B2 (en) * 2007-06-22 2010-07-27 Semiconductor Energy Laboratory Co., Ltd Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
FR2923079B1 (fr) * 2007-10-26 2017-10-27 S O I Tec Silicon On Insulator Tech Substrats soi avec couche fine isolante enterree
CN101842910B (zh) * 2007-11-01 2013-03-27 株式会社半导体能源研究所 用于制造光电转换器件的方法
US8093136B2 (en) * 2007-12-28 2012-01-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5354900B2 (ja) * 2007-12-28 2013-11-27 株式会社半導体エネルギー研究所 半導体基板の作製方法
FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
JP5503876B2 (ja) * 2008-01-24 2014-05-28 株式会社半導体エネルギー研究所 半導体基板の製造方法
US8119490B2 (en) * 2008-02-04 2012-02-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US7858495B2 (en) * 2008-02-04 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP4577382B2 (ja) * 2008-03-06 2010-11-10 信越半導体株式会社 貼り合わせウェーハの製造方法
CN101981654B (zh) 2008-04-01 2012-11-21 信越化学工业株式会社 Soi基板的制造方法
FR2931585B1 (fr) * 2008-05-26 2010-09-03 Commissariat Energie Atomique Traitement de surface par plasma d'azote dans un procede de collage direct
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US20100022070A1 (en) * 2008-07-22 2010-01-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
SG160295A1 (en) * 2008-09-29 2010-04-29 Semiconductor Energy Lab Method for manufacturing semiconductor device
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5496598B2 (ja) * 2008-10-31 2014-05-21 信越化学工業株式会社 シリコン薄膜転写絶縁性ウェーハの製造方法
FR2942911B1 (fr) * 2009-03-09 2011-05-13 Soitec Silicon On Insulator Procede de realisation d'une heterostructure avec adaptation locale de coefficient de dilatation thermique
FR2951023B1 (fr) 2009-10-01 2012-03-09 St Microelectronics Sa Procede de fabrication d'oscillateurs monolithiques a resonateurs baw
FR2951024B1 (fr) 2009-10-01 2012-03-23 St Microelectronics Sa Procede de fabrication de resonateur baw a facteur de qualite eleve
FR2951026B1 (fr) * 2009-10-01 2011-12-02 St Microelectronics Sa Procede de fabrication de resonateurs baw sur une tranche semiconductrice
JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP2012156495A (ja) 2011-01-07 2012-08-16 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
WO2012100786A1 (de) 2011-01-25 2012-08-02 Ev Group E. Thallner Gmbh Verfahren zum permanenten bonden von wafern
WO2012136267A1 (de) 2011-04-08 2012-10-11 Ev Group E. Thallner Gmbh Verfahren zum permanenten bonden von wafern
US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
KR102148336B1 (ko) * 2013-11-26 2020-08-27 삼성전자주식회사 표면 처리 방법, 반도체 제조 방법 및 이에 의해 제조된 반도체 장치
WO2015147952A2 (en) * 2014-01-29 2015-10-01 Palvannanathan Ganesan Floating nuclear power reactor with a self-cooling containment structure and an emergency heat exchange system
CN107004639B (zh) * 2014-07-08 2021-02-05 麻省理工学院 衬底制造方法
FR3036200B1 (fr) * 2015-05-13 2017-05-05 Soitec Silicon On Insulator Methode de calibration pour equipements de traitement thermique
EP3391151B1 (en) * 2015-12-18 2022-02-16 ASML Netherlands B.V. A method of manufacturing a membrane assembly for euv lithography, a membrane assembly, a lithographic apparatus, and a device manufacturing method
FR3045939B1 (fr) 2015-12-22 2018-03-30 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct entre deux structures
WO2019022826A1 (en) * 2017-07-24 2019-01-31 Applied Materials, Inc. PRETREATMENT APPARATUS FOR IMPROVING THE CONTINUITY OF ULTRA-THIN AMORPHOUS SILICON FILM ON SILICON OXIDE
FR3079345B1 (fr) * 2018-03-26 2020-02-21 Soitec Procede de fabrication d'un substrat pour dispositif radiofrequence
CN114203546B (zh) * 2020-09-18 2026-04-03 中芯集成电路（宁波）有限公司 半导体器件及其制造方法
JP7487659B2 (ja) * 2020-12-25 2024-05-21 株式会社Sumco Ｓｏｉウェーハの製造方法
CN114688950B (zh) * 2022-05-31 2022-08-23 陕西建工第一建设集团有限公司 一种建筑施工用铝合金板平整检测装置
FR3171514A1 (fr) * 2025-01-22 2026-07-24 Commissariat A L' Energie Atomique Et Aux Energies Alternatives Procédé de fabrication d’un guide d’ondes

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489255B1 (en) * 1995-06-05 2002-12-03 International Business Machines Corporation Low temperature/low dopant oxide glass film
US6051478A (en) * 1997-12-18 2000-04-18 Advanced Micro Devices, Inc. Method of enhancing trench edge oxide quality
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US6489241B1 (en) * 1999-09-17 2002-12-03 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US7749910B2 (en) * 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
JP4086272B2 (ja) * 2001-07-26 2008-05-14 株式会社東芝 半導体装置
FR2835095B1 (fr) * 2002-01-22 2005-03-18 Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
US6869821B2 (en) * 2002-12-30 2005-03-22 Xerox Corporation Method for producing organic electronic devices on deposited dielectric materials
KR100889886B1 (ko) * 2003-01-07 2009-03-20 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 박층을 박리한 후 다층 구조를 포함하는 웨이퍼의 재활용방법
JP2004259970A (ja) * 2003-02-26 2004-09-16 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
US6723666B1 (en) * 2003-03-06 2004-04-20 Advanced Micro Devices, Inc. Method for reducing gate oxide surface irregularities
US6982210B2 (en) * 2003-07-10 2006-01-03 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for manufacturing a multilayer semiconductor structure that includes an irregular layer
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2857982B1 (fr) * 2003-07-24 2007-05-18 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
JP2005150686A (ja) * 2003-10-22 2005-06-09 Sharp Corp 半導体装置およびその製造方法
US20050250346A1 (en) * 2004-05-06 2005-11-10 Applied Materials, Inc. Process and apparatus for post deposition treatment of low k dielectric materials
US7349140B2 (en) * 2005-05-31 2008-03-25 Miradia Inc. Triple alignment substrate method and structure for packaging devices

Also Published As

Publication number Publication date
US7446019B2 (en) 2008-11-04
KR100958467B1 (ko) 2010-05-17
JP2009501440A (ja) 2009-01-15
FR2888663A1 (fr) 2007-01-19
JP4927080B2 (ja) 2012-05-09
CN101243545A (zh) 2008-08-13
KR20080031747A (ko) 2008-04-10
CN100576462C (zh) 2009-12-30
WO2007006803A1 (fr) 2007-01-18
US20070020947A1 (en) 2007-01-25
FR2888663B1 (fr) 2008-04-18
EP1902463A1 (fr) 2008-03-26
ATE524828T1 (de) 2011-09-15
US8183128B2 (en) 2012-05-22
US20090023267A1 (en) 2009-01-22
EP1902463B1 (fr) 2011-09-14

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