JP4737221B2 - 表示装置 - Google Patents
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- JP4737221B2 JP4737221B2 JP2008106456A JP2008106456A JP4737221B2 JP 4737221 B2 JP4737221 B2 JP 4737221B2 JP 2008106456 A JP2008106456 A JP 2008106456A JP 2008106456 A JP2008106456 A JP 2008106456A JP 4737221 B2 JP4737221 B2 JP 4737221B2
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- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Control Of El Displays (AREA)
- Electroluminescent Light Sources (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
また、電源供給線は、引出し配線とは別の配線層に形成され、かつ、引出し配線が接続される部分において、その短手方向の幅が、他の部分よりも太くなるように形成する。
引出し配線の長さまたは幅を画素回路ごとに設定する部分は、電源供給線の短手方向の幅が太くされている部分において電源供給線と面内方向で重なるように形成され、かつ、電源供給線と平行して配線されるものとする。
図1は、本発明に係る表示装置の一実施形態であるアクティブマトリクス型表示装置の構成の概略を示すブロック図である。ここで示す構成例では、たとえば画素の表示素子(電気光学素子、発光素子)として電流駆動型の素子である有機EL素子を、また能動素子としてポリシリコン薄膜トランジスタ(TFT;Thin Film Transistor)をそれぞれ用い、薄膜トランジスタを形成した半導体基板上に有機EL素子を形成してなるアクティブマトリクス型有機ELディスプレイ(以下「有機EL表示装置」や、単に「表示装置」とも称する)に適用した場合を例に採って説明する。薄膜トランジスタとしては、FET(Field-effect Transistor :電界効果トランジスタ)を使用する。
図2は、本実施形態の画素回路Pに対する第1比較例を示す図である。なお、表示パネル部100の基板101上において画素アレイ部102の周辺部に配置される垂直駆動部103および水平駆動部106も合わせて示している。
図3は画素構成素子(有機EL素子や駆動トランジスタ)の特性変動とその影響を説明する図である。ここで、図3(1)は有機EL素子や駆動トランジスタの動作点を説明する図である。図3(2)は、有機EL素子や駆動トランジスタの特性ばらつきが駆動電流Idsに与える影響を説明する図である。
一般的に、有機EL素子を始めとする電流駆動型の発光素子のI−V特性は、図3(2)に示すように時間が経過すると劣化する。図3(2)に示す有機EL素子で代表される電流駆動型の発光素子の電流−電圧(Iel−Vel)特性において、実線で示す曲線が初期状態時の特性を示し、破線で示す曲線が経時変化後の特性を示している。
図4は、本実施形態の画素回路Pに対する第2比較例を示す図である。なお、表示パネル部100の基板101上において画素アレイ部102の周辺部に配置される垂直駆動部103および水平駆動部106も合わせて示している。
また、画素ごとに駆動トランジスタ121の特性が異なると、その影響が駆動トランジスタ121に流れる駆動電流Idsに影響を及ぼす。一例としては、式(1)から分かるように、移動度μや閾値電圧Vthが画素によってばらついた場合や経時的に変化した場合、ゲート・ソース間電圧Vgsが同じであっても、駆動トランジスタ121に流れる駆動電流Idsにばらつきや経時変化が生じ、有機EL素子127の発光輝度も画素ごとに変化してしまうことになる。
これに対して、閾値補正機能および移動度補正機能を実現する駆動タイミング(詳細は後述する)とすることで、それらの変動の影響を抑制でき、画面輝度の均一性(ユニフォーミティ)を確保できる。
図5は、本実施形態の画素回路Pを示す図である。なお、表示パネル部100の基板101上において画素アレイ部102の周辺部に配置される垂直駆動部103および水平駆動部106も合わせて示している。本実施形態の画素回路Pは、基本的にNch型のFETで駆動トランジスタ121が構成されている。また、有機EL素子127の経時劣化による当該有機EL素子127への駆動電流Idsの変動を抑制するための回路、すなわち電気光学素子の一例である有機EL素子の電流−電圧特性の変化を補正して駆動電流Idsを一定に維持する駆動信号一定化回路(その1)を備える。
図6は、図5に示した本実施形態の画素回路Pに関する本実施形態の駆動タイミングの基本例を説明するタイミングチャートである。図6A〜図6Gは、図6に示したタイミングチャートの各期間における等価回路と動作状態を説明する図である。
図7および図8は、本実施形態の表示パネル部100に発生する問題点を説明する図である。ここで、図7は、電源配線である電源供給線105DSL の配線抵抗に起因する全白表示時に画像に現われる問題を説明する図である。図8は、電源配線である電源供給線105DSL の配線抵抗に起因するウィンドウパターン表示時に画像に現われる問題を説明する図である。なお、図8においては、トランジスタのアーリー効果との関係において、図7、図8の問題が生じる原因も説明する。
図9は、電源供給線105DSL の電圧降下を起因とする表示むらを抑制する本実施形態の仕組みを説明する概念図である。
図10および図11は、図9に示した基本原理を実現する第1実施形態のレイアウト例(模式図)を説明する図である。ここで、図10は、本実施形態を適用しない比較例のレイアウト例を示す模式図である。図11は、第1実施形態を適用したレイアウト例を示す模式図である。なお、本実施形態の仕組みは、電源供給線105DSL と引出し配線121DLの関係がポイントであるので、その他の部分については画素回路Pを利用して簡単に示している。図10(1)には、画素回路Pを示す。
図11Aは、図9に示した基本原理を実現する第2実施形態のレイアウト例を示す模式図である。図9に示した仕組みを実現するために、駆動走査部105に近い方の画素回路P(図ではP1,P4)は引出し配線121DLの抵抗値が大きく、駆動走査部105から遠ざかるほど引出し配線121DLの抵抗値が小さくなるように、画素回路Pごとに引出し配線121DLの幅を設定する。この際、第2実施形態のレイアウトでは、引出し配線121DLの長さではなく、引出し配線121DLの幅を、駆動走査部105に近い方では細く、駆動走査部105から遠ざかるほど太くすることで、これを実現している。引出し配線121DLは、第2配線層L2に配された電源供給線105DSL とは別の第3配線層L3にポリシリコンなどで平行に配線しておく。こうすることで、他の配線のレイアウトの障害とならないようにする。因みに、駆動走査部105から遠ざかる側では、引出し配線121DLの幅を広くするのに合わせて、電源供給線105DSL との接続をとるコンタクト部の数を増やしてもよいし、全列、同一のコンタクト数としてもよい。
図11Bは、図9に示した基本原理を実現する第3実施形態のレイアウト例を示す模式図である。図9に示した仕組みを実現するために、駆動走査部105に近い方の画素回路P(図ではP1,P4)は引出し配線121DLの抵抗値が大きく、駆動走査部105から遠ざかるほど引出し配線121DLの抵抗値が小さくなるように、画素回路Pごとに引出し配線121DLの長さと幅を設定する。この際、第3実施形態のレイアウトは、第1実施形態と第2実施形態を併用したもので、駆動走査部105に近い方では引出し配線121DLを長くかつ細くし、駆動走査部105から遠ざかるほど、引出し配線121DLを短くかつ太くすることで、これを実現している。引出し配線121DL_1,121DL_2は、第2配線層L2に配された電源供給線105DSL とは別の第3配線層L3にポリシリコンなどで平行に配線しておく。こうすることで、他の配線のレイアウトの障害とならないようにする。長さと幅(太さ)の双方を調整する第3実施形態では、引出し配線121DLの抵抗値の調整範囲が前述の第1・第2実施形態よりも広がる。
Claims (3)
- 駆動電流を生成する駆動トランジスタおよび前記駆動トランジスタの出力端に接続された電気光学素子を含む画素回路が行列状に配置され、前記駆動トランジスタの電源供給端にパルス状の電源電圧を供給する走査線である電源供給線が配線された画素アレイ部、
を備え、
各画素回路の前記駆動トランジスタの電源供給端が、引出し配線を介して前記電源供給線に接続されており、
前記電源供給線は、前記引出し配線とは別の配線層に形成され、かつ、前記引出し配線が接続される部分において、その短手方向の幅が、他の部分よりも太くなるように形成され、
各画素回路の前記引出し配線は、その配線抵抗が、前記電源供給線の長手方向に、前記パルス状の電源電圧の供給元に近い方では大きく遠ざかるほど小さくなるように、長さおよび幅の少なくとも一方が、前記電源供給線の長手方向に沿って、画素回路ごとに設定され、
前記引出し配線の長さまたは幅を画素回路ごとに設定する部分は、前記電源供給線の短手方向の幅が太くされている部分において前記電源供給線と面内方向で重なるように形成され、かつ、前記電源供給線と平行して配線されている
表示装置。 - 各画素回路の前記電気光学素子を同一輝度で発光させる条件下では、各駆動トランジスタの前記電源供給端の電位が同一となるように、前記引出し配線の長さおよび幅の少なくとも一方が設定されている
請求項1に記載の表示装置。 - 前記引出し配線の配線部材は、前記電源供給線の配線部材よりも抵抗率が大きい
請求項1または2に記載の表示装置。
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JP2008106456A JP4737221B2 (ja) | 2008-04-16 | 2008-04-16 | 表示装置 |
TW98109800A TW200947390A (en) | 2008-04-16 | 2009-03-25 | Display apparatus |
US12/385,189 US8350972B2 (en) | 2008-04-16 | 2009-04-01 | Display apparatus |
CN2009101327433A CN101561992B (zh) | 2008-04-16 | 2009-04-16 | 显示装置 |
US13/682,906 US8730136B2 (en) | 2008-04-16 | 2012-11-21 | Display apparatus |
US14/245,473 US8907874B2 (en) | 2008-04-16 | 2014-04-04 | Display apparatus |
US14/540,085 US9202858B2 (en) | 2008-04-16 | 2014-11-13 | Display apparatus |
US14/936,385 US20160078799A1 (en) | 2008-04-16 | 2015-11-09 | Display apparatus |
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US20140218271A1 (en) | 2014-08-07 |
US20130076603A1 (en) | 2013-03-28 |
US20090262258A1 (en) | 2009-10-22 |
US8350972B2 (en) | 2013-01-08 |
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US8907874B2 (en) | 2014-12-09 |
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