JP4728833B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4728833B2 JP4728833B2 JP2006038580A JP2006038580A JP4728833B2 JP 4728833 B2 JP4728833 B2 JP 4728833B2 JP 2006038580 A JP2006038580 A JP 2006038580A JP 2006038580 A JP2006038580 A JP 2006038580A JP 4728833 B2 JP4728833 B2 JP 4728833B2
- Authority
- JP
- Japan
- Prior art keywords
- guard ring
- region
- semiconductor device
- silicide
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 97
- 229910021332 silicide Inorganic materials 0.000 claims description 90
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 90
- 238000009792 diffusion process Methods 0.000 claims description 52
- 239000012535 impurity Substances 0.000 claims description 52
- 230000015572 biosynthetic process Effects 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 230000003071 parasitic effect Effects 0.000 description 35
- 239000000758 substrate Substances 0.000 description 12
- 239000012141 concentrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 101150110971 CIN7 gene Proteins 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 2
- 101150110298 INV1 gene Proteins 0.000 description 2
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
以下、本発明の半導体装置の第1の実施形態について、図6〜9を参照して説明する。
<第2の実施形態>
以下、本発明の半導体装置の第2の実施形態について、図10〜12を参照して説明する。なお、第1の実施形態に係る半導体装置と同一の部位については、同一の符号を付して重複説明を省略する。
<第3の実施形態>
以下、本発明の半導体装置の第3の実施形態について、図13〜16を参照して説明する。なお、第1の実施形態に係る半導体装置と同一の部位については、同一の符号を付して重複説明を省略する。
Q1〜Q5…トランジスタ
20…トランジスタ形成領域
30…ゲート領域
40…ドレイン領域
50…ソース領域
61…第1ガードリング
71…第2ガードリング
Claims (5)
- 第1導電型トランジスタが形成されたトランジスタ形成領域と、
・ 第1幅をもって前記トランジスタ形成領域を取り囲む第2導電型の第1不純物拡散層であって、第1基準電位線に接続された第1ガードリングと、
第2幅をもって前記第1ガードリングを取り囲む第1導電型の第2不純物拡散層である第2ガードリングと、
前記第1導電型トランジスタのドレイン領域と対向する側にはシリサイドが形成されないようにして前記第2ガードリングの表面に形成されたシリサイド領域であって、前記第1基準電位よりも高電位の第2基準電位線に接続されたシリサイド領域と、
を備えた半導体装置。 - 前記第2ガードリングにおいて前記第1導電型トランジスタのドレイン領域と対向する端を基準として、前記第2ガードリングの表面にシリサイドが形成されない領域が前記トランジスタ形成領域を取り囲む所定の第3幅のリング形状であることを特徴とする
請求項1記載の半導体装置。 - 前記第2ガードリングにおいて前記第1導電型トランジスタのドレイン領域と近接した範囲には、シリサイドが前記第2幅全体に形成されないことを特徴とする
請求項1記載の半導体装置。 - 前記第2ガードリングにおいて前記第1導電型トランジスタのドレイン領域と近接した範囲には、金属配線とのコンタクトが形成されないことを特徴とする
請求項1または3記載の半導体装置。 - 前記シリサイド領域は、互いに離間して形成された複数のサブ領域を含み、各サブ領域は金属配線に接続されることを特徴とする
請求項1記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006038580A JP4728833B2 (ja) | 2006-02-15 | 2006-02-15 | 半導体装置 |
CN2007100042184A CN101022106B (zh) | 2006-02-15 | 2007-01-18 | 半导体装置 |
US11/624,656 US7791148B2 (en) | 2006-02-15 | 2007-01-18 | Semiconductor device |
KR1020070005900A KR20070082506A (ko) | 2006-02-15 | 2007-01-19 | 반도체장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006038580A JP4728833B2 (ja) | 2006-02-15 | 2006-02-15 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007220831A JP2007220831A (ja) | 2007-08-30 |
JP4728833B2 true JP4728833B2 (ja) | 2011-07-20 |
Family
ID=38367509
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006038580A Expired - Fee Related JP4728833B2 (ja) | 2006-02-15 | 2006-02-15 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7791148B2 (ja) |
JP (1) | JP4728833B2 (ja) |
KR (1) | KR20070082506A (ja) |
CN (1) | CN101022106B (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090032906A1 (en) * | 2007-07-30 | 2009-02-05 | Infineon Technologies Austria Ag | Electro static discharge device and method for manufacturing an electro static discharge device |
US7759734B2 (en) * | 2008-03-07 | 2010-07-20 | United Microelectronics Corp. | Semiconductor device |
JP5497997B2 (ja) * | 2008-06-05 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | Esd保護回路及び半導体装置 |
TWI360875B (en) | 2008-10-08 | 2012-03-21 | Kinpo Elect Inc | Electrostatic discharge protection structure |
US8134813B2 (en) * | 2009-01-29 | 2012-03-13 | Xilinx, Inc. | Method and apparatus to reduce footprint of ESD protection within an integrated circuit |
JP5529607B2 (ja) * | 2010-03-29 | 2014-06-25 | セイコーインスツル株式会社 | 半導体装置 |
JP5593160B2 (ja) * | 2010-08-13 | 2014-09-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6022804B2 (ja) * | 2011-07-25 | 2016-11-09 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
KR102248282B1 (ko) * | 2014-01-21 | 2021-05-06 | 삼성전자주식회사 | Cmos 반도체 장치 |
US9496251B2 (en) * | 2014-09-24 | 2016-11-15 | United Microelectronics Corporation | Electrostatic discharge protector |
JP2015216410A (ja) * | 2015-09-04 | 2015-12-03 | セイコーエプソン株式会社 | 半導体装置 |
CN105552073A (zh) * | 2015-12-14 | 2016-05-04 | 武汉芯昌科技有限公司 | 一种防止闩锁效应及噪声干扰的芯片版图结构及方法 |
US10090291B2 (en) * | 2016-04-26 | 2018-10-02 | United Microelectronics Corp. | Electrostatic discharge protection semiconductor device and layout structure of ESD protection semiconductor device |
JP6828588B2 (ja) * | 2017-05-22 | 2021-02-10 | 株式会社ソシオネクスト | 半導体装置 |
CN109545841A (zh) * | 2018-11-22 | 2019-03-29 | 长江存储科技有限责任公司 | 双保护环及其形成方法 |
CN110060997B (zh) * | 2019-04-15 | 2020-04-17 | 长江存储科技有限责任公司 | 一种静电放电保护结构及其制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10313065A (ja) * | 1997-05-13 | 1998-11-24 | Seiko Epson Corp | 半導体装置 |
JP2003031668A (ja) * | 2001-07-13 | 2003-01-31 | Hitachi Ltd | 半導体装置 |
JP2005354014A (ja) * | 2004-06-14 | 2005-12-22 | Nec Electronics Corp | 静電気放電保護素子 |
JP2006518941A (ja) * | 2003-02-20 | 2006-08-17 | サーノフ コーポレーション | 最適なフィンガー間結合のための最小寸法のフルシリサイドmosドライバ及びesd保護の設計 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6624487B1 (en) * | 2002-05-07 | 2003-09-23 | Texas Instruments Incorporated | Drain-extended MOS ESD protection structure |
WO2004112139A1 (ja) * | 2003-06-10 | 2004-12-23 | Fujitsu Limited | 半導体装置とその製造方法 |
US7045830B1 (en) * | 2004-12-07 | 2006-05-16 | Fairchild Semiconductor Corporation | High-voltage diodes formed in advanced power integrated circuit devices |
-
2006
- 2006-02-15 JP JP2006038580A patent/JP4728833B2/ja not_active Expired - Fee Related
-
2007
- 2007-01-18 US US11/624,656 patent/US7791148B2/en not_active Expired - Fee Related
- 2007-01-18 CN CN2007100042184A patent/CN101022106B/zh not_active Expired - Fee Related
- 2007-01-19 KR KR1020070005900A patent/KR20070082506A/ko not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10313065A (ja) * | 1997-05-13 | 1998-11-24 | Seiko Epson Corp | 半導体装置 |
JP2003031668A (ja) * | 2001-07-13 | 2003-01-31 | Hitachi Ltd | 半導体装置 |
JP2006518941A (ja) * | 2003-02-20 | 2006-08-17 | サーノフ コーポレーション | 最適なフィンガー間結合のための最小寸法のフルシリサイドmosドライバ及びesd保護の設計 |
JP2005354014A (ja) * | 2004-06-14 | 2005-12-22 | Nec Electronics Corp | 静電気放電保護素子 |
Also Published As
Publication number | Publication date |
---|---|
KR20070082506A (ko) | 2007-08-21 |
US20070187782A1 (en) | 2007-08-16 |
JP2007220831A (ja) | 2007-08-30 |
CN101022106A (zh) | 2007-08-22 |
US7791148B2 (en) | 2010-09-07 |
CN101022106B (zh) | 2010-06-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4728833B2 (ja) | 半導体装置 | |
JP4854934B2 (ja) | 静電気放電保護素子 | |
US8008723B2 (en) | Semiconductor device including a plurality of diffusion layers and diffusion resistance layer | |
JP4209432B2 (ja) | 静電破壊保護装置 | |
JP3400215B2 (ja) | 半導体装置 | |
JP2006303110A (ja) | 半導体装置 | |
JP4209433B2 (ja) | 静電破壊保護装置 | |
JP2010182727A (ja) | 半導体装置 | |
US6670678B2 (en) | Semiconductor device having ESD protective transistor | |
JP2010067846A (ja) | 静電放電保護回路を備えた半導体装置 | |
JP2005045016A (ja) | 半導体集積回路 | |
JP6471557B2 (ja) | 半導体装置および半導体装置の試験方法 | |
JP2004304136A (ja) | 半導体装置 | |
JP2008205148A (ja) | 縦型pnpバイポーラトランジスタ用静電破壊保護素子 | |
US9385116B2 (en) | Semiconductor ESD device | |
JP2010050328A (ja) | 静電気保護素子 | |
JP5297495B2 (ja) | 静電気放電保護素子 | |
JP2001077305A (ja) | 半導体装置 | |
JP2005333120A (ja) | 静電保護素子 | |
JP3123489B2 (ja) | 半導体集積回路における静電保護回路及びその製造方法 | |
JP4504664B2 (ja) | 静電気放電保護素子及び静電気放電保護回路 | |
JP2003179226A (ja) | 半導体集積回路装置 | |
JP3544499B2 (ja) | 半導体集積回路装置 | |
JP2005079287A (ja) | 集積回路 | |
JP2009141071A (ja) | 静電気保護用半導体素子 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080729 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081210 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20090206 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101224 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110105 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110307 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110412 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110415 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140422 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |