JP4564166B2 - ウエハ・パッシベーション層の形成方法 - Google Patents

ウエハ・パッシベーション層の形成方法 Download PDF

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JP4564166B2
JP4564166B2 JP2000526962A JP2000526962A JP4564166B2 JP 4564166 B2 JP4564166 B2 JP 4564166B2 JP 2000526962 A JP2000526962 A JP 2000526962A JP 2000526962 A JP2000526962 A JP 2000526962A JP 4564166 B2 JP4564166 B2 JP 4564166B2
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layer
material layer
bond pad
dielectric layer
silicon nitride
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JP2002500440A5 (enExample
JP2002500440A (ja
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ボーア，マーク・ティ
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Intel Corp
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Intel Corp
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)
JP2000526962A 1997-12-31 1998-11-16 ウエハ・パッシベーション層の形成方法 Expired - Lifetime JP4564166B2 (ja)

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US09/002,178 1997-12-31
US09/002,178 US6875681B1 (en) 1997-12-31 1997-12-31 Wafer passivation structure and method of fabrication
PCT/US1998/024358 WO1999034423A1 (en) 1997-12-31 1998-11-16 Wafer passivation structure and method of fabrication

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US20050158978A1 (en) 2005-07-21
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US6875681B1 (en) 2005-04-05
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US7145235B2 (en) 2006-12-05
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