AU1410999A - Wafer passivation structure and method of fabrication - Google Patents

Wafer passivation structure and method of fabrication

Info

Publication number
AU1410999A
AU1410999A AU14109/99A AU1410999A AU1410999A AU 1410999 A AU1410999 A AU 1410999A AU 14109/99 A AU14109/99 A AU 14109/99A AU 1410999 A AU1410999 A AU 1410999A AU 1410999 A AU1410999 A AU 1410999A
Authority
AU
Australia
Prior art keywords
fabrication
passivation structure
wafer passivation
wafer
passivation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU14109/99A
Other languages
English (en)
Inventor
Mark T Bohr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU1410999A publication Critical patent/AU1410999A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer
AU14109/99A 1997-12-31 1998-11-16 Wafer passivation structure and method of fabrication Abandoned AU1410999A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/002,178 US6875681B1 (en) 1997-12-31 1997-12-31 Wafer passivation structure and method of fabrication
US09002178 1997-12-31
PCT/US1998/024358 WO1999034423A1 (en) 1997-12-31 1998-11-16 Wafer passivation structure and method of fabrication

Publications (1)

Publication Number Publication Date
AU1410999A true AU1410999A (en) 1999-07-19

Family

ID=21699571

Family Applications (1)

Application Number Title Priority Date Filing Date
AU14109/99A Abandoned AU1410999A (en) 1997-12-31 1998-11-16 Wafer passivation structure and method of fabrication

Country Status (5)

Country Link
US (2) US6875681B1 (enExample)
JP (1) JP4564166B2 (enExample)
KR (2) KR100526445B1 (enExample)
AU (1) AU1410999A (enExample)
WO (1) WO1999034423A1 (enExample)

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US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US6521996B1 (en) 2000-06-30 2003-02-18 Intel Corporation Ball limiting metallurgy for input/outputs and methods of fabrication
FR2828009B1 (fr) * 2001-07-25 2003-10-10 Novatec Methode de realisation de bossages presentant des performances thermomecaniques ameliorees
US7180195B2 (en) 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing
US9222169B2 (en) * 2004-03-15 2015-12-29 Sharp Laboratories Of America, Inc. Silicon oxide-nitride-carbide thin-film with embedded nanocrystalline semiconductor particles
JP4525129B2 (ja) * 2004-03-26 2010-08-18 ソニー株式会社 固体撮像素子とその製造方法、及び半導体集積回路装置とその製造方法
US7452803B2 (en) * 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
JP4504791B2 (ja) * 2004-11-24 2010-07-14 パナソニック株式会社 半導体回路装置及びその製造方法
US7956460B2 (en) * 2004-12-28 2011-06-07 Rohm Co., Ltd. Semiconductor chip and method for manufacturing same, electrode structure of semiconductor chip and method for forming same, and semiconductor device
US7927933B2 (en) * 2005-02-16 2011-04-19 Imec Method to enhance the initiation of film growth
US20060211232A1 (en) * 2005-03-16 2006-09-21 Mei-Jen Liu Method for Manufacturing Gold Bumps
CN1901161B (zh) 2005-07-22 2010-10-27 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
KR100660893B1 (ko) * 2005-11-22 2006-12-26 삼성전자주식회사 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법
JP4854675B2 (ja) * 2005-11-28 2012-01-18 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US20080163897A1 (en) * 2007-01-10 2008-07-10 Applied Materials, Inc. Two step process for post ash cleaning for cu/low-k dual damascene structure with metal hard mask
US20080237822A1 (en) * 2007-03-30 2008-10-02 Raravikar Nachiket R Microelectronic die having nano-particle containing passivation layer and package including same
US8373275B2 (en) * 2008-01-29 2013-02-12 International Business Machines Corporation Fine pitch solder bump structure with built-in stress buffer
KR101037832B1 (ko) * 2008-05-09 2011-05-31 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101140063B1 (ko) * 2010-09-14 2012-04-30 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US8580672B2 (en) * 2011-10-25 2013-11-12 Globalfoundries Inc. Methods of forming bump structures that include a protection layer
US8765531B2 (en) * 2012-08-21 2014-07-01 Infineon Technologies Ag Method for manufacturing a metal pad structure of a die, a method for manufacturing a bond pad of a chip, a die arrangement and a chip arrangement
US9502343B1 (en) * 2015-09-18 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy metal with zigzagged edges
US11365117B2 (en) 2019-12-23 2022-06-21 Industrial Technology Research Institute MEMS device and manufacturing method of the same
US11939212B2 (en) 2019-12-23 2024-03-26 Industrial Technology Research Institute MEMS device, manufacturing method of the same, and integrated MEMS module using the same
US11251114B2 (en) * 2020-05-01 2022-02-15 Taiwan Semiconductor Manufacturing Co., Ltd. Package substrate insulation opening design

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KR890005819A (ko) * 1987-09-21 1989-05-17 강진구 반도체 소자의 보호막 제조방법
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Also Published As

Publication number Publication date
JP2002500440A (ja) 2002-01-08
KR100522130B1 (ko) 2005-10-19
US6875681B1 (en) 2005-04-05
US7145235B2 (en) 2006-12-05
KR100526445B1 (ko) 2005-11-08
KR20010033662A (ko) 2001-04-25
WO1999034423A1 (en) 1999-07-08
US20050158978A1 (en) 2005-07-21
JP4564166B2 (ja) 2010-10-20
KR20050065684A (ko) 2005-06-29

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase