AU2461801A - Interconnect structure and method of fabrication therefor - Google Patents

Interconnect structure and method of fabrication therefor

Info

Publication number
AU2461801A
AU2461801A AU24618/01A AU2461801A AU2461801A AU 2461801 A AU2461801 A AU 2461801A AU 24618/01 A AU24618/01 A AU 24618/01A AU 2461801 A AU2461801 A AU 2461801A AU 2461801 A AU2461801 A AU 2461801A
Authority
AU
Australia
Prior art keywords
interconnect structure
fabrication therefor
therefor
fabrication
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU24618/01A
Inventor
Bob Sankman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2461801A publication Critical patent/AU2461801A/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AU24618/01A 1999-12-28 2000-12-28 Interconnect structure and method of fabrication therefor Abandoned AU2461801A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US47327299A 1999-12-28 1999-12-28
US09473272 1999-12-28
PCT/US2000/035483 WO2001048819A2 (en) 1999-12-28 2000-12-28 Interconnect structure and method of fabrication therefor

Publications (1)

Publication Number Publication Date
AU2461801A true AU2461801A (en) 2001-07-09

Family

ID=23878876

Family Applications (1)

Application Number Title Priority Date Filing Date
AU24618/01A Abandoned AU2461801A (en) 1999-12-28 2000-12-28 Interconnect structure and method of fabrication therefor

Country Status (2)

Country Link
AU (1) AU2461801A (en)
WO (1) WO2001048819A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7102892B2 (en) 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
AU2003216362A1 (en) * 2002-02-26 2003-09-09 Legacy Electronics, Inc. A modular integrated circuit chip carrier
CN104519658B (en) * 2013-09-30 2017-09-29 北大方正集团有限公司 The preparation method and circuit board of a kind of circuit board skip floor blind hole
CN106653318B (en) * 2017-02-28 2019-06-18 华为技术有限公司 Inductance component and crisscross parallel DC converter

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3426278C2 (en) * 1984-07-17 1987-02-26 Schroff Gmbh, 7541 Straubenhardt Circuit board
JPH0294693A (en) * 1988-09-30 1990-04-05 Nec Corp Printed wiring board having coaxial through-hole
JPH04348595A (en) * 1991-05-27 1992-12-03 Hitachi Ltd Method for repairing multilayer printed circuit board
JP2819523B2 (en) * 1992-10-09 1998-10-30 インターナショナル・ビジネス・マシーンズ・コーポレイション Printed wiring board and method of manufacturing the same
US5421083A (en) * 1994-04-01 1995-06-06 Motorola, Inc. Method of manufacturing a circuit carrying substrate having coaxial via holes
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US5949030A (en) * 1997-11-14 1999-09-07 International Business Machines Corporation Vias and method for making the same in organic board and chip carriers

Also Published As

Publication number Publication date
WO2001048819A3 (en) 2002-03-07
WO2001048819A2 (en) 2001-07-05

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase