JP4452463B2 - レイアウト面積を減らし、バンクごとに独立的な動作を実行することができるデコーダを有するフラッシュメモリ装置 - Google Patents
レイアウト面積を減らし、バンクごとに独立的な動作を実行することができるデコーダを有するフラッシュメモリ装置 Download PDFInfo
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- JP4452463B2 JP4452463B2 JP2003286360A JP2003286360A JP4452463B2 JP 4452463 B2 JP4452463 B2 JP 4452463B2 JP 2003286360 A JP2003286360 A JP 2003286360A JP 2003286360 A JP2003286360 A JP 2003286360A JP 4452463 B2 JP4452463 B2 JP 4452463B2
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- 230000004044 response Effects 0.000 claims description 28
- 239000011159 matrix material Substances 0.000 claims description 11
- 102100021568 B-cell scaffold protein with ankyrin repeats Human genes 0.000 description 6
- 101000971155 Homo sapiens B-cell scaffold protein with ankyrin repeats Proteins 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 102100040428 Chitobiosyldiphosphodolichol beta-mannosyltransferase Human genes 0.000 description 5
- 101000891557 Homo sapiens Chitobiosyldiphosphodolichol beta-mannosyltransferase Proteins 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Description
BANK0〜BANKn バンク
GDEC グローバルデコーダ
LDEC ローカルデコーダ
MAT0〜MATm マトリックスブロック
Claims (5)
- 行及び列に配列される複数個のメモリセルを有する多数個のバンクと、
前記バンクのロウ配列方向に分けられたマトリックスブロックごとに位置し、読み出しアドレス信号と書き込みアドレス信号とが個別的に供給され、その読み出しアドレス信号と書き込みアドレス信号に各々応答して、グローバル読み出し信号とグローバル書き込み信号とをそれぞれ出力するアドレスデコーディング部分を含み、
前記グローバル読み出し信号と前記グローバル書き込み信号を個別的に発生するグローバルデコーダと、
前記マトリックスブロック内セクタごとに位置し、読み出しセクタ選択信号に応答して前記グローバル読み出し信号を、そして書き込みセクタ選択信号に応答して前記グローバル書き込み信号をワードラインイネーブル信号に伝達し、前記ワードラインイネーブル信号に応答してワードライン駆動信号をワードラインに伝達するローカルデコーダとを具備
し、
バンクごとに独立的に読み出し動作と書き込み動作が行われることを特徴とするフラッシュメモリ装置。 - 前記グローバルデコーダは、
前記読み出しアドレス信号を入力して前記グローバル読み出し信号を出力する第1NANDゲートと、
前記書き込みアドレス信号を入力して前記グローバル書き込み信号を出力する第2NANDゲートとを具備することを特徴とする請求項1に記載のフラッシュメモリ装置。 - 前記ローカルデコーダは、
デコーダイネーブル信号と読み出しセクタ選択信号に応答して前記グローバル読み出し信号を、そして書き込みセクタ選択信号に応答して前記グローバル書き込み信号をワードラインイネーブル信号に伝達するコーディング部と、
前記ワードラインイネーブル信号に応答してワードライン駆動信号をワードラインに伝達するドライバ部と、
前記ワードライン駆動信号の反転信号に応答して前記ワードラインをリセットさせるリセット部とを具備することを特徴とする請求項1に記載のフラッシュメモリ装置。 - 前記コーディング部は、
電源電圧がそのソースに連結され、前記デコーダイネーブル信号がそのゲートに、そして前記ワードラインイネーブル信号にそのドレインが連結される第1トランジスタと、
前記ワードラインイネーブル信号がそのドレインに連結され、前記読み出しセクタ選択信号がそのゲートに、そして前記グローバル読み出し信号がそのソースに連結される第2トランジスタと、
前記ワードラインイネーブル信号がそのドレインに連結され、前記書き込みセクタ選択信号がそのゲートに、そして前記グローバル書き込み信号がそのソースに連結される第3トランジスタとを具備することを特徴とする請求項3に記載のフラッシュメモリ装置。 - 前記コーディング部は、
電源電圧がそのソースに連結され、前記デコーダイネーブル信号がそのゲートに、そして前記ワードラインイネーブル信号にそのドレインが連結される第1トランジスタと、
前記ワードラインイネーブル信号がそのドレインに連結され、前記読み出しセクタ選択信号がそのゲートに連結される第2トランジスタと、
前記第2トランジスタのソースと接地電圧との間に連結され、前記グローバル読み出し信号にゲーティングされる第3トランジスタと、
前記ワードラインイネーブル信号がそのドレインに連結され、前記書き込みセクタ選択信号がそのゲートに連結される第4トランジスタと、
前記4トランジスタのソースと前記接地電圧との間に連結され、前記グローバル書き込み信号にゲーティングされる第5トランジスタとを具備することを特徴とする請求項3に記載のフラッシュメモリ装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0048045A KR100481857B1 (ko) | 2002-08-14 | 2002-08-14 | 레이아웃 면적을 줄이고 뱅크 마다 독립적인 동작을수행할 수 있는 디코더를 갖는 플레쉬 메모리 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004079161A JP2004079161A (ja) | 2004-03-11 |
JP4452463B2 true JP4452463B2 (ja) | 2010-04-21 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003286360A Expired - Fee Related JP4452463B2 (ja) | 2002-08-14 | 2003-08-05 | レイアウト面積を減らし、バンクごとに独立的な動作を実行することができるデコーダを有するフラッシュメモリ装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7079417B2 (ja) |
EP (1) | EP1389781A3 (ja) |
JP (1) | JP4452463B2 (ja) |
KR (1) | KR100481857B1 (ja) |
CN (1) | CN100520974C (ja) |
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KR100664866B1 (ko) * | 2005-04-26 | 2007-01-03 | 매그나칩 반도체 유한회사 | 어드레스 디코더 회로 |
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-
2002
- 2002-08-14 KR KR10-2002-0048045A patent/KR100481857B1/ko active IP Right Grant
-
2003
- 2003-07-18 US US10/622,278 patent/US7079417B2/en not_active Expired - Lifetime
- 2003-08-05 JP JP2003286360A patent/JP4452463B2/ja not_active Expired - Fee Related
- 2003-08-06 EP EP03017907A patent/EP1389781A3/en not_active Withdrawn
- 2003-08-14 CN CNB031540384A patent/CN100520974C/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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US7079417B2 (en) | 2006-07-18 |
EP1389781A2 (en) | 2004-02-18 |
JP2004079161A (ja) | 2004-03-11 |
CN1484251A (zh) | 2004-03-24 |
CN100520974C (zh) | 2009-07-29 |
EP1389781A3 (en) | 2006-02-08 |
KR20040015901A (ko) | 2004-02-21 |
US20040090825A1 (en) | 2004-05-13 |
KR100481857B1 (ko) | 2005-04-11 |
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